Added new atomic functions, renamed some old ones. Some #defines have
been added for backward compatibility.
Merged the pre- and post-ARMv6 implementations into a single file.
Renamed the semi-private __android_membar_full_smp to USE_SCREAMING_CAPS
since that's more appropriate for a macro.
Added lots of comments.
Note Mac OS X primitives have not been tested.
Change-Id: If827260750aeb61ad5c2b760e30658e29dbb26f2
Added atomic-inline.h. Added a platform-specific memory barrier call
there.
Added android_atomic_acquire_cmpxchg() and android_atomic_release_store().
Not tested on Mac OS X or SH.
Added memory barrier calls to linux-x86 atomics. Mac OS X has barrier
functions already. sh isn't really SMP-ready. linux-arm needs work
(to be done in a separate change).
Updated the makefile to make the SMP state visible to the code here.
Note that host binaries are NOT built with SMP enabled; while our hosts
are very likely SMP, it's not worth figuring out e.g. whether it's okay
to use the SSE2 mfence instruction or have to use something else. We
haven't had barriers enabled in host tools before, so there's probably
no need to stat now.
Removed quasiatomic 64-bit calls (now part of Dalvik).
Change-Id: I49e5e6c8abe70f304cdedb9d7b8e6e65f8925815
ARMv6 onwards. These architectures provide the load-linked, store-conditional pair of ldrex/strex whose use
is recommended in place of 'swp'. Also, the description of the 'swp' instruction in the ARMv6 reference
manual states that the swap operation does not include any memory barrier guarantees.This fix attempts to
address these issues by providing an atomic swap implementation using ldrex/strex under _ARM_HAVE_LDREX_STREX
macro. _ARM_HAVE_LDREX_STREX macro is defined in cpu-features.h file and patch is submitted under change ID 11088.
This Fix is verified on ST Ericsson's U8500 platform and Submitted on behalf of a third-party:
Surinder-pal SINGH from STMicroelectronics.
Andy McFadden