c27a444e54
Add Silvermont architecture cache sizes
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Adds Silvermont specific cache sizes for memset16/32 SSE optimization.
Change-Id: Ib5ea086d57544e74ac384ee1ef516b8511392f70
Signed-off-by: Henrik Smiding <henrik.smiding@intel.com>
2014-04-18 11:31:54 +08:00
9ff8767bc6
Eliminate text relocations in x86 optimized memset versions
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Change-Id: Ieb72af8cf7f93210a68a87b1e2538deb5642f4d5
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
2013-10-24 21:42:30 +04:00
4aa51cd468
Cleanup x86 flags and memset versions
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ARCH_X86_HAVE_SSE2 is always true
Change-Id: I680493d14280aafad5448aec727e8d9a84a6db00
Signed-off-by: Pavel Chupin <pavel.v.chupin@intel.com>
2013-10-10 20:20:16 +04:00
bb12ac9b85
Assembly coded android_memset16 and android_memset32
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Change-Id: Ife2dd406e1dcb962e5e97788c515ac96f5c52e44
2011-01-07 11:26:34 -08:00
Henrik Smiding