2011-02-18 06:45:11 +08:00
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/*
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* QEMU model of the LatticeMico32 UART block.
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*
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* Copyright (c) 2010 Michael Walle <michael@walle.cc>
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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* You should have received a copy of the GNU Lesser General Public
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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*
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*
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* Specification available at:
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* http://www.latticesemi.com/documents/mico32uart.pdf
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*/
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2016-01-27 02:16:57 +08:00
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#include "qemu/osdep.h"
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2013-02-04 22:40:22 +08:00
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#include "hw/hw.h"
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#include "hw/sysbus.h"
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2011-02-18 06:45:11 +08:00
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#include "trace.h"
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2013-04-08 22:55:25 +08:00
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#include "sysemu/char.h"
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2012-12-18 01:20:00 +08:00
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#include "qemu/error-report.h"
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2011-02-18 06:45:11 +08:00
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enum {
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R_RXTX = 0,
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R_IER,
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R_IIR,
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R_LCR,
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R_MCR,
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R_LSR,
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R_MSR,
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R_DIV,
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R_MAX
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};
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enum {
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IER_RBRI = (1<<0),
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IER_THRI = (1<<1),
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IER_RLSI = (1<<2),
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IER_MSI = (1<<3),
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};
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enum {
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IIR_STAT = (1<<0),
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IIR_ID0 = (1<<1),
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IIR_ID1 = (1<<2),
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};
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enum {
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LCR_WLS0 = (1<<0),
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LCR_WLS1 = (1<<1),
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LCR_STB = (1<<2),
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LCR_PEN = (1<<3),
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LCR_EPS = (1<<4),
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LCR_SP = (1<<5),
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LCR_SB = (1<<6),
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};
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enum {
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MCR_DTR = (1<<0),
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MCR_RTS = (1<<1),
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};
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enum {
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LSR_DR = (1<<0),
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LSR_OE = (1<<1),
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LSR_PE = (1<<2),
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LSR_FE = (1<<3),
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LSR_BI = (1<<4),
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LSR_THRE = (1<<5),
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LSR_TEMT = (1<<6),
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};
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enum {
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MSR_DCTS = (1<<0),
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MSR_DDSR = (1<<1),
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MSR_TERI = (1<<2),
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MSR_DDCD = (1<<3),
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MSR_CTS = (1<<4),
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MSR_DSR = (1<<5),
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MSR_RI = (1<<6),
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MSR_DCD = (1<<7),
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};
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2013-07-25 04:59:55 +08:00
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#define TYPE_LM32_UART "lm32-uart"
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#define LM32_UART(obj) OBJECT_CHECK(LM32UartState, (obj), TYPE_LM32_UART)
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2011-02-18 06:45:11 +08:00
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struct LM32UartState {
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2013-07-25 04:59:55 +08:00
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SysBusDevice parent_obj;
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2011-11-24 21:31:16 +08:00
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MemoryRegion iomem;
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2011-02-18 06:45:11 +08:00
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CharDriverState *chr;
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qemu_irq irq;
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uint32_t regs[R_MAX];
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};
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typedef struct LM32UartState LM32UartState;
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static void uart_update_irq(LM32UartState *s)
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{
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unsigned int irq;
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if ((s->regs[R_LSR] & (LSR_OE | LSR_PE | LSR_FE | LSR_BI))
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&& (s->regs[R_IER] & IER_RLSI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID1 | IIR_ID0;
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} else if ((s->regs[R_LSR] & LSR_DR) && (s->regs[R_IER] & IER_RBRI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID1;
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} else if ((s->regs[R_LSR] & LSR_THRE) && (s->regs[R_IER] & IER_THRI)) {
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irq = 1;
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s->regs[R_IIR] = IIR_ID0;
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} else if ((s->regs[R_MSR] & 0x0f) && (s->regs[R_IER] & IER_MSI)) {
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irq = 1;
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s->regs[R_IIR] = 0;
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} else {
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irq = 0;
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s->regs[R_IIR] = IIR_STAT;
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}
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trace_lm32_uart_irq_state(irq);
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qemu_set_irq(s->irq, irq);
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}
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2012-10-23 18:30:10 +08:00
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static uint64_t uart_read(void *opaque, hwaddr addr,
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2011-11-24 21:31:16 +08:00
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unsigned size)
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2011-02-18 06:45:11 +08:00
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{
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LM32UartState *s = opaque;
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uint32_t r = 0;
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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r = s->regs[R_RXTX];
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s->regs[R_LSR] &= ~LSR_DR;
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uart_update_irq(s);
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2012-07-31 06:04:57 +08:00
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qemu_chr_accept_input(s->chr);
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2011-02-18 06:45:11 +08:00
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break;
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case R_IIR:
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case R_LSR:
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case R_MSR:
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r = s->regs[addr];
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break;
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case R_IER:
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case R_LCR:
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case R_MCR:
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case R_DIV:
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error_report("lm32_uart: read access to write only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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2011-06-22 20:03:56 +08:00
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error_report("lm32_uart: read access to unknown register 0x"
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2011-02-18 06:45:11 +08:00
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TARGET_FMT_plx, addr << 2);
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break;
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}
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trace_lm32_uart_memory_read(addr << 2, r);
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return r;
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}
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2012-10-23 18:30:10 +08:00
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static void uart_write(void *opaque, hwaddr addr,
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2011-11-24 21:31:16 +08:00
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uint64_t value, unsigned size)
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2011-02-18 06:45:11 +08:00
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{
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LM32UartState *s = opaque;
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unsigned char ch = value;
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trace_lm32_uart_memory_write(addr, value);
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addr >>= 2;
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switch (addr) {
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case R_RXTX:
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if (s->chr) {
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2013-09-17 00:29:32 +08:00
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qemu_chr_fe_write_all(s->chr, &ch, 1);
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2011-02-18 06:45:11 +08:00
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}
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break;
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case R_IER:
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case R_LCR:
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case R_MCR:
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case R_DIV:
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s->regs[addr] = value;
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break;
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case R_IIR:
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case R_LSR:
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case R_MSR:
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error_report("lm32_uart: write access to read only register 0x"
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TARGET_FMT_plx, addr << 2);
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break;
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default:
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2011-06-22 20:03:56 +08:00
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error_report("lm32_uart: write access to unknown register 0x"
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2011-02-18 06:45:11 +08:00
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TARGET_FMT_plx, addr << 2);
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break;
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}
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uart_update_irq(s);
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}
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2011-11-24 21:31:16 +08:00
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static const MemoryRegionOps uart_ops = {
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.read = uart_read,
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.write = uart_write,
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.endianness = DEVICE_NATIVE_ENDIAN,
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.valid = {
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.min_access_size = 4,
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.max_access_size = 4,
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},
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2011-02-18 06:45:11 +08:00
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};
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static void uart_rx(void *opaque, const uint8_t *buf, int size)
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{
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LM32UartState *s = opaque;
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if (s->regs[R_LSR] & LSR_DR) {
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s->regs[R_LSR] |= LSR_OE;
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}
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s->regs[R_LSR] |= LSR_DR;
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s->regs[R_RXTX] = *buf;
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uart_update_irq(s);
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}
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static int uart_can_rx(void *opaque)
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{
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LM32UartState *s = opaque;
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return !(s->regs[R_LSR] & LSR_DR);
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}
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static void uart_event(void *opaque, int event)
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{
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}
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static void uart_reset(DeviceState *d)
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{
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2013-07-25 04:59:55 +08:00
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LM32UartState *s = LM32_UART(d);
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2011-02-18 06:45:11 +08:00
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int i;
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for (i = 0; i < R_MAX; i++) {
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s->regs[i] = 0;
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}
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/* defaults */
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s->regs[R_LSR] = LSR_THRE | LSR_TEMT;
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}
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static int lm32_uart_init(SysBusDevice *dev)
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{
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2013-07-25 04:59:55 +08:00
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LM32UartState *s = LM32_UART(dev);
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2011-02-18 06:45:11 +08:00
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sysbus_init_irq(dev, &s->irq);
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2013-06-07 09:25:08 +08:00
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memory_region_init_io(&s->iomem, OBJECT(s), &uart_ops, s,
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"uart", R_MAX * 4);
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2011-11-27 17:38:10 +08:00
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sysbus_init_mmio(dev, &s->iomem);
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2011-02-18 06:45:11 +08:00
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2015-03-25 16:29:20 +08:00
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/* FIXME use a qdev chardev prop instead of qemu_char_get_next_serial() */
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2011-12-23 05:29:25 +08:00
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s->chr = qemu_char_get_next_serial();
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2011-02-18 06:45:11 +08:00
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if (s->chr) {
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qemu_chr_add_handlers(s->chr, uart_can_rx, uart_rx, uart_event, s);
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}
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return 0;
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}
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static const VMStateDescription vmstate_lm32_uart = {
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.name = "lm32-uart",
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.version_id = 1,
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.minimum_version_id = 1,
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2014-04-16 22:01:33 +08:00
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.fields = (VMStateField[]) {
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2011-02-18 06:45:11 +08:00
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VMSTATE_UINT32_ARRAY(regs, LM32UartState, R_MAX),
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VMSTATE_END_OF_LIST()
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}
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};
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2012-01-25 03:12:29 +08:00
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static void lm32_uart_class_init(ObjectClass *klass, void *data)
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{
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2011-12-08 11:34:16 +08:00
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DeviceClass *dc = DEVICE_CLASS(klass);
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2012-01-25 03:12:29 +08:00
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SysBusDeviceClass *k = SYS_BUS_DEVICE_CLASS(klass);
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k->init = lm32_uart_init;
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2011-12-08 11:34:16 +08:00
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dc->reset = uart_reset;
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dc->vmsd = &vmstate_lm32_uart;
|
sysbus: Make devices picking up backends unavailable with -device
Device models aren't supposed to go on fishing expeditions for
backends. They should expose suitable properties for the user to set.
For onboard devices, board code sets them.
A number of sysbus devices pick up block backends in their init() /
instance_init() methods with drive_get_next() instead: sl-nand,
milkymist-memcard, pl181, generic-sdhci.
Likewise, a number of sysbus devices pick up character backends in
their init() / realize() methods with qemu_char_get_next_serial():
cadence_uart, digic-uart, etraxfs,serial, lm32-juart, lm32-uart,
milkymist-uart, pl011, stm32f2xx-usart, xlnx.xps-uartlite.
All these mistakes are already marked FIXME. See the commit that
added these FIXMEs for a more detailed explanation of what's wrong.
Fortunately, only machines ppce500 and pseries-* support -device with
sysbus devices, and none of the devices above is supported with these
machines.
Set cannot_instantiate_with_device_add_yet to preserve our luck.
Cc: Andrzej Zaborowski <balrogg@gmail.com>
Cc: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Cc: Antony Pavlov <antonynpavlov@gmail.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>
Cc: Michael Walle <michael@walle.cc>
Signed-off-by: Markus Armbruster <armbru@redhat.com>
2015-03-24 02:34:40 +08:00
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/* Reason: init() method uses qemu_char_get_next_serial() */
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dc->cannot_instantiate_with_device_add_yet = true;
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2012-01-25 03:12:29 +08:00
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}
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2013-01-10 23:19:07 +08:00
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static const TypeInfo lm32_uart_info = {
|
2013-07-25 04:59:55 +08:00
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.name = TYPE_LM32_UART,
|
2011-12-08 11:34:16 +08:00
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.parent = TYPE_SYS_BUS_DEVICE,
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.instance_size = sizeof(LM32UartState),
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.class_init = lm32_uart_class_init,
|
2011-02-18 06:45:11 +08:00
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};
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|
2012-02-09 22:20:55 +08:00
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static void lm32_uart_register_types(void)
|
2011-02-18 06:45:11 +08:00
|
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{
|
2011-12-08 11:34:16 +08:00
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type_register_static(&lm32_uart_info);
|
2011-02-18 06:45:11 +08:00
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}
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|
2012-02-09 22:20:55 +08:00
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type_init(lm32_uart_register_types)
|