2004-05-19 07:05:28 +08:00
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/*
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* QEMU PCI bus manager
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*
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* Copyright (c) 2004 Fabrice Bellard
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2007-09-17 05:08:06 +08:00
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*
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2004-05-19 07:05:28 +08:00
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* Permission is hereby granted, free of charge, to any person obtaining a copy
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* of this software and associated documentation files (the "Software"), to deal
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* in the Software without restriction, including without limitation the rights
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* to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
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* copies of the Software, and to permit persons to whom the Software is
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* furnished to do so, subject to the following conditions:
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*
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* The above copyright notice and this permission notice shall be included in
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* all copies or substantial portions of the Software.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
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* IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
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* FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
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* THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
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* LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
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* OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
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* THE SOFTWARE.
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*/
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2007-11-18 01:14:51 +08:00
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#include "hw.h"
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#include "pci.h"
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2010-07-13 12:01:39 +08:00
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#include "pci_bridge.h"
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2010-07-12 18:36:40 +08:00
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#include "pci_internals.h"
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2009-03-06 07:01:23 +08:00
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#include "monitor.h"
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2007-11-18 01:14:51 +08:00
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#include "net.h"
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2009-02-11 23:21:48 +08:00
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#include "sysemu.h"
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2009-12-18 19:01:07 +08:00
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#include "loader.h"
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2010-01-22 05:15:40 +08:00
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#include "qemu-objects.h"
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2004-05-19 07:05:28 +08:00
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//#define DEBUG_PCI
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2009-07-07 14:59:22 +08:00
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#ifdef DEBUG_PCI
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2009-10-30 20:20:55 +08:00
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# define PCI_DPRINTF(format, ...) printf(format, ## __VA_ARGS__)
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2009-07-07 14:59:22 +08:00
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#else
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# define PCI_DPRINTF(format, ...) do { } while (0)
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#endif
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2004-05-19 07:05:28 +08:00
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2009-06-30 20:12:08 +08:00
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static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent);
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2010-06-26 01:08:59 +08:00
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static char *pcibus_get_dev_path(DeviceState *dev);
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2009-06-30 20:12:08 +08:00
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2010-07-12 18:36:40 +08:00
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struct BusInfo pci_bus_info = {
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2009-06-30 20:12:08 +08:00
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.name = "PCI",
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.size = sizeof(PCIBus),
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.print_dev = pcibus_dev_print,
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2010-06-26 01:08:59 +08:00
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.get_dev_path = pcibus_get_dev_path,
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2009-07-15 19:43:31 +08:00
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.props = (Property[]) {
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2009-08-03 23:35:19 +08:00
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DEFINE_PROP_PCI_DEVFN("addr", PCIDevice, devfn, -1),
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2009-12-18 19:01:08 +08:00
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DEFINE_PROP_STRING("romfile", PCIDevice, romfile),
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2010-01-08 22:25:41 +08:00
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DEFINE_PROP_UINT32("rombar", PCIDevice, rom_bar, 1),
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2010-06-23 15:15:30 +08:00
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DEFINE_PROP_BIT("multifunction", PCIDevice, cap_present,
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QEMU_PCI_CAP_MULTIFUNCTION_BITNR, false),
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2009-08-03 23:35:19 +08:00
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DEFINE_PROP_END_OF_LIST()
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2009-07-15 19:43:31 +08:00
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}
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2004-06-22 03:45:35 +08:00
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};
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2004-05-19 07:05:28 +08:00
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2006-08-17 18:46:34 +08:00
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static void pci_update_mappings(PCIDevice *d);
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2007-04-08 02:14:41 +08:00
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static void pci_set_irq(void *opaque, int irq_num, int level);
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2009-12-18 19:01:08 +08:00
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static int pci_add_option_rom(PCIDevice *pdev);
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2010-06-26 01:10:19 +08:00
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static void pci_del_option_rom(PCIDevice *pdev);
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2006-08-17 18:46:34 +08:00
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2008-12-12 05:15:42 +08:00
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static uint16_t pci_default_sub_vendor_id = PCI_SUBVENDOR_ID_REDHAT_QUMRANET;
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static uint16_t pci_default_sub_device_id = PCI_SUBDEVICE_ID_QEMU;
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2009-10-30 20:21:13 +08:00
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struct PCIHostBus {
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int domain;
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struct PCIBus *bus;
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QLIST_ENTRY(PCIHostBus) next;
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};
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static QLIST_HEAD(, PCIHostBus) host_buses;
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2004-06-22 03:45:35 +08:00
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2009-08-21 01:42:34 +08:00
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static const VMStateDescription vmstate_pcibus = {
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.name = "PCIBUS",
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.version_id = 1,
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.minimum_version_id = 1,
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.minimum_version_id_old = 1,
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.fields = (VMStateField []) {
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VMSTATE_INT32_EQUAL(nirq, PCIBus),
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2009-10-16 19:29:48 +08:00
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VMSTATE_VARRAY_INT32(irq_count, PCIBus, nirq, 0, vmstate_info_int32, int32_t),
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2009-08-21 01:42:34 +08:00
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VMSTATE_END_OF_LIST()
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2007-12-10 07:56:13 +08:00
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}
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2009-08-21 01:42:34 +08:00
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};
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2007-12-10 07:56:13 +08:00
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2009-10-30 20:21:05 +08:00
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static int pci_bar(PCIDevice *d, int reg)
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2009-09-16 18:40:57 +08:00
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{
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2009-10-30 20:21:05 +08:00
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uint8_t type;
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if (reg != PCI_ROM_SLOT)
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return PCI_BASE_ADDRESS_0 + reg * 4;
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type = d->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
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return type == PCI_HEADER_TYPE_BRIDGE ? PCI_ROM_ADDRESS1 : PCI_ROM_ADDRESS;
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2009-09-16 18:40:57 +08:00
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}
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2009-11-25 21:20:51 +08:00
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static inline int pci_irq_state(PCIDevice *d, int irq_num)
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{
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return (d->irq_state >> irq_num) & 0x1;
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}
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static inline void pci_set_irq_state(PCIDevice *d, int irq_num, int level)
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{
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d->irq_state &= ~(0x1 << irq_num);
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d->irq_state |= level << irq_num;
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}
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static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
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{
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PCIBus *bus;
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for (;;) {
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bus = pci_dev->bus;
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irq_num = bus->map_irq(pci_dev, irq_num);
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if (bus->set_irq)
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break;
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pci_dev = bus->parent_dev;
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}
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bus->irq_count[irq_num] += change;
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bus->set_irq(bus->irq_opaque, irq_num, bus->irq_count[irq_num] != 0);
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}
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2009-11-25 21:44:40 +08:00
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/* Update interrupt status bit in config space on interrupt
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* state change. */
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static void pci_update_irq_status(PCIDevice *dev)
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{
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if (dev->irq_state) {
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dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
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} else {
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dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
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}
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}
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2009-09-16 18:40:57 +08:00
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static void pci_device_reset(PCIDevice *dev)
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{
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2009-09-16 18:41:09 +08:00
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int r;
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2009-11-25 21:20:51 +08:00
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dev->irq_state = 0;
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2009-11-25 21:44:40 +08:00
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pci_update_irq_status(dev);
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2010-06-17 14:15:45 +08:00
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/* Clear all writeable bits */
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pci_set_word(dev->config + PCI_COMMAND,
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pci_get_word(dev->config + PCI_COMMAND) &
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~pci_get_word(dev->wmask + PCI_COMMAND));
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2009-09-16 18:41:09 +08:00
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dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
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dev->config[PCI_INTERRUPT_LINE] = 0x0;
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for (r = 0; r < PCI_NUM_REGIONS; ++r) {
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2010-06-17 14:15:45 +08:00
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PCIIORegion *region = &dev->io_regions[r];
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if (!region->size) {
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2009-09-16 18:41:09 +08:00
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continue;
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}
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2010-06-17 14:15:45 +08:00
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if (!(region->type & PCI_BASE_ADDRESS_SPACE_IO) &&
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region->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
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pci_set_quad(dev->config + pci_bar(dev, r), region->type);
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} else {
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pci_set_long(dev->config + pci_bar(dev, r), region->type);
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}
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2009-09-16 18:41:09 +08:00
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}
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pci_update_mappings(dev);
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2009-09-16 18:40:57 +08:00
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}
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2009-06-18 00:32:00 +08:00
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static void pci_bus_reset(void *opaque)
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{
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2009-08-25 00:42:53 +08:00
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PCIBus *bus = opaque;
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2009-06-18 00:32:00 +08:00
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int i;
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for (i = 0; i < bus->nirq; i++) {
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bus->irq_count[i] = 0;
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}
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2009-09-16 18:40:57 +08:00
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for (i = 0; i < ARRAY_SIZE(bus->devices); ++i) {
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if (bus->devices[i]) {
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pci_device_reset(bus->devices[i]);
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}
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2009-06-18 00:32:00 +08:00
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}
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}
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2009-10-30 20:21:13 +08:00
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static void pci_host_bus_register(int domain, PCIBus *bus)
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{
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struct PCIHostBus *host;
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host = qemu_mallocz(sizeof(*host));
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host->domain = domain;
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host->bus = bus;
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QLIST_INSERT_HEAD(&host_buses, host, next);
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}
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2009-11-12 13:58:36 +08:00
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PCIBus *pci_find_root_bus(int domain)
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2009-10-30 20:21:13 +08:00
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{
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struct PCIHostBus *host;
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QLIST_FOREACH(host, &host_buses, next) {
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if (host->domain == domain) {
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return host->bus;
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}
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}
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return NULL;
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}
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2010-05-28 17:30:46 +08:00
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int pci_find_domain(const PCIBus *bus)
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{
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PCIDevice *d;
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struct PCIHostBus *host;
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/* obtain root bus */
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while ((d = bus->parent_dev) != NULL) {
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bus = d->bus;
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}
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QLIST_FOREACH(host, &host_buses, next) {
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if (host->bus == bus) {
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return host->domain;
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}
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}
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abort(); /* should not be reached */
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return -1;
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}
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2009-09-17 04:25:31 +08:00
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void pci_bus_new_inplace(PCIBus *bus, DeviceState *parent,
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const char *name, int devfn_min)
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2004-06-22 03:45:35 +08:00
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{
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2009-09-17 04:25:31 +08:00
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qbus_create_inplace(&bus->qbus, &pci_bus_info, parent, name);
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2010-06-23 15:15:26 +08:00
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assert(PCI_FUNC(devfn_min) == 0);
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2006-05-14 00:11:23 +08:00
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bus->devfn_min = devfn_min;
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2009-10-30 20:21:13 +08:00
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/* host bridge */
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QLIST_INIT(&bus->child);
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pci_host_bus_register(0, bus); /* for now only pci domain 0 is supported */
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2010-06-26 01:09:07 +08:00
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vmstate_register(NULL, -1, &vmstate_pcibus, bus);
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2009-06-27 15:25:07 +08:00
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qemu_register_reset(pci_bus_reset, bus);
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2009-09-17 04:25:31 +08:00
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}
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PCIBus *pci_bus_new(DeviceState *parent, const char *name, int devfn_min)
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{
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PCIBus *bus;
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bus = qemu_mallocz(sizeof(*bus));
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bus->qbus.qdev_allocated = 1;
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pci_bus_new_inplace(bus, parent, name, devfn_min);
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return bus;
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}
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void pci_bus_irqs(PCIBus *bus, pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int nirq)
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{
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bus->set_irq = set_irq;
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bus->map_irq = map_irq;
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bus->irq_opaque = irq_opaque;
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bus->nirq = nirq;
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bus->irq_count = qemu_mallocz(nirq * sizeof(bus->irq_count[0]));
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}
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2010-05-14 15:29:19 +08:00
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void pci_bus_hotplug(PCIBus *bus, pci_hotplug_fn hotplug, DeviceState *qdev)
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2009-09-26 03:42:44 +08:00
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{
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bus->qbus.allow_hotplug = 1;
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bus->hotplug = hotplug;
|
2010-05-14 15:29:19 +08:00
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bus->hotplug_qdev = qdev;
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2009-09-26 03:42:44 +08:00
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}
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2009-12-26 00:50:36 +08:00
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void pci_bus_set_mem_base(PCIBus *bus, target_phys_addr_t base)
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{
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bus->mem_base = base;
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}
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2009-09-17 04:25:31 +08:00
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PCIBus *pci_register_bus(DeviceState *parent, const char *name,
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pci_set_irq_fn set_irq, pci_map_irq_fn map_irq,
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void *irq_opaque, int devfn_min, int nirq)
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{
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PCIBus *bus;
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bus = pci_bus_new(parent, name, devfn_min);
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pci_bus_irqs(bus, set_irq, map_irq, irq_opaque, nirq);
|
2004-06-22 03:45:35 +08:00
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return bus;
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}
|
2004-05-19 07:05:28 +08:00
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2006-05-14 00:11:23 +08:00
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int pci_bus_num(PCIBus *s)
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{
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2009-10-30 20:21:12 +08:00
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if (!s->parent_dev)
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return 0; /* pci host bridge */
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return s->parent_dev->config[PCI_SECONDARY_BUS];
|
2006-05-14 00:11:23 +08:00
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}
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2009-08-21 01:42:39 +08:00
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static int get_pci_config_device(QEMUFile *f, void *pv, size_t size)
|
2004-10-03 21:56:00 +08:00
|
|
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{
|
2009-08-21 01:42:39 +08:00
|
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PCIDevice *s = container_of(pv, PCIDevice, config);
|
2009-10-30 20:21:18 +08:00
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uint8_t *config;
|
2007-12-10 07:56:13 +08:00
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int i;
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|
2009-10-30 20:21:18 +08:00
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assert(size == pci_config_size(s));
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config = qemu_malloc(size);
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qemu_get_buffer(f, config, size);
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|
for (i = 0; i < size; ++i) {
|
|
|
|
if ((config[i] ^ s->config[i]) & s->cmask[i] & ~s->wmask[i]) {
|
|
|
|
qemu_free(config);
|
2009-06-22 00:49:40 +08:00
|
|
|
return -EINVAL;
|
2009-10-30 20:21:18 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
memcpy(s->config, config, size);
|
2009-06-22 00:49:40 +08:00
|
|
|
|
2006-08-17 18:46:34 +08:00
|
|
|
pci_update_mappings(s);
|
2007-12-10 07:56:13 +08:00
|
|
|
|
2009-10-30 20:21:18 +08:00
|
|
|
qemu_free(config);
|
2004-10-03 21:56:00 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-08-21 01:42:39 +08:00
|
|
|
/* just put buffer */
|
2009-09-30 04:48:20 +08:00
|
|
|
static void put_pci_config_device(QEMUFile *f, void *pv, size_t size)
|
2009-08-21 01:42:39 +08:00
|
|
|
{
|
2009-11-12 07:39:14 +08:00
|
|
|
const uint8_t **v = pv;
|
2009-10-30 20:21:18 +08:00
|
|
|
assert(size == pci_config_size(container_of(pv, PCIDevice, config)));
|
2009-11-12 07:39:14 +08:00
|
|
|
qemu_put_buffer(f, *v, size);
|
2009-08-21 01:42:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static VMStateInfo vmstate_info_pci_config = {
|
|
|
|
.name = "pci config",
|
|
|
|
.get = get_pci_config_device,
|
|
|
|
.put = put_pci_config_device,
|
|
|
|
};
|
|
|
|
|
2009-11-25 21:20:51 +08:00
|
|
|
static int get_pci_irq_state(QEMUFile *f, void *pv, size_t size)
|
|
|
|
{
|
2010-05-10 00:15:16 +08:00
|
|
|
PCIDevice *s = container_of(pv, PCIDevice, irq_state);
|
2009-11-25 21:20:51 +08:00
|
|
|
uint32_t irq_state[PCI_NUM_PINS];
|
|
|
|
int i;
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; ++i) {
|
|
|
|
irq_state[i] = qemu_get_be32(f);
|
|
|
|
if (irq_state[i] != 0x1 && irq_state[i] != 0) {
|
|
|
|
fprintf(stderr, "irq state %d: must be 0 or 1.\n",
|
|
|
|
irq_state[i]);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; ++i) {
|
|
|
|
pci_set_irq_state(s, i, irq_state[i]);
|
|
|
|
}
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void put_pci_irq_state(QEMUFile *f, void *pv, size_t size)
|
|
|
|
{
|
|
|
|
int i;
|
2010-05-10 00:15:16 +08:00
|
|
|
PCIDevice *s = container_of(pv, PCIDevice, irq_state);
|
2009-11-25 21:20:51 +08:00
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; ++i) {
|
|
|
|
qemu_put_be32(f, pci_irq_state(s, i));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static VMStateInfo vmstate_info_pci_irq_state = {
|
|
|
|
.name = "pci irq state",
|
|
|
|
.get = get_pci_irq_state,
|
|
|
|
.put = put_pci_irq_state,
|
|
|
|
};
|
|
|
|
|
2009-08-21 01:42:39 +08:00
|
|
|
const VMStateDescription vmstate_pci_device = {
|
|
|
|
.name = "PCIDevice",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32_LE(version_id, PCIDevice),
|
2009-10-30 20:21:18 +08:00
|
|
|
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
|
|
|
vmstate_info_pci_config,
|
|
|
|
PCI_CONFIG_SPACE_SIZE),
|
2009-11-25 21:20:51 +08:00
|
|
|
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
|
|
|
vmstate_info_pci_irq_state,
|
|
|
|
PCI_NUM_PINS * sizeof(int32_t)),
|
2009-10-30 20:21:18 +08:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
|
|
|
const VMStateDescription vmstate_pcie_device = {
|
|
|
|
.name = "PCIDevice",
|
|
|
|
.version_id = 2,
|
|
|
|
.minimum_version_id = 1,
|
|
|
|
.minimum_version_id_old = 1,
|
|
|
|
.fields = (VMStateField []) {
|
|
|
|
VMSTATE_INT32_LE(version_id, PCIDevice),
|
|
|
|
VMSTATE_BUFFER_UNSAFE_INFO(config, PCIDevice, 0,
|
|
|
|
vmstate_info_pci_config,
|
|
|
|
PCIE_CONFIG_SPACE_SIZE),
|
2009-11-25 21:20:51 +08:00
|
|
|
VMSTATE_BUFFER_UNSAFE_INFO(irq_state, PCIDevice, 2,
|
|
|
|
vmstate_info_pci_irq_state,
|
|
|
|
PCI_NUM_PINS * sizeof(int32_t)),
|
2009-08-21 01:42:39 +08:00
|
|
|
VMSTATE_END_OF_LIST()
|
|
|
|
}
|
|
|
|
};
|
|
|
|
|
2009-10-30 20:21:18 +08:00
|
|
|
static inline const VMStateDescription *pci_get_vmstate(PCIDevice *s)
|
|
|
|
{
|
|
|
|
return pci_is_express(s) ? &vmstate_pcie_device : &vmstate_pci_device;
|
|
|
|
}
|
|
|
|
|
2009-08-21 01:42:39 +08:00
|
|
|
void pci_device_save(PCIDevice *s, QEMUFile *f)
|
|
|
|
{
|
2009-11-25 21:44:40 +08:00
|
|
|
/* Clear interrupt status bit: it is implicit
|
|
|
|
* in irq_state which we are saving.
|
|
|
|
* This makes us compatible with old devices
|
|
|
|
* which never set or clear this bit. */
|
|
|
|
s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
|
2009-10-30 20:21:18 +08:00
|
|
|
vmstate_save_state(f, pci_get_vmstate(s), s);
|
2009-11-25 21:44:40 +08:00
|
|
|
/* Restore the interrupt status bit. */
|
|
|
|
pci_update_irq_status(s);
|
2009-08-21 01:42:39 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
int pci_device_load(PCIDevice *s, QEMUFile *f)
|
|
|
|
{
|
2009-11-25 21:44:40 +08:00
|
|
|
int ret;
|
|
|
|
ret = vmstate_load_state(f, pci_get_vmstate(s), s, s->version_id);
|
|
|
|
/* Restore the interrupt status bit. */
|
|
|
|
pci_update_irq_status(s);
|
|
|
|
return ret;
|
2009-08-21 01:42:39 +08:00
|
|
|
}
|
|
|
|
|
2010-05-27 13:42:06 +08:00
|
|
|
static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
|
2008-12-12 05:15:42 +08:00
|
|
|
{
|
2010-05-27 13:42:06 +08:00
|
|
|
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_VENDOR_ID,
|
|
|
|
pci_default_sub_vendor_id);
|
|
|
|
pci_set_word(pci_dev->config + PCI_SUBSYSTEM_ID,
|
|
|
|
pci_default_sub_device_id);
|
2008-12-12 05:15:42 +08:00
|
|
|
}
|
|
|
|
|
2009-02-11 23:21:48 +08:00
|
|
|
/*
|
2010-09-06 15:46:19 +08:00
|
|
|
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
|
|
|
|
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
|
2009-02-11 23:21:48 +08:00
|
|
|
*/
|
2010-09-06 15:46:19 +08:00
|
|
|
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
|
|
|
|
unsigned int *slotp, unsigned int *funcp)
|
2009-02-11 23:21:48 +08:00
|
|
|
{
|
|
|
|
const char *p;
|
|
|
|
char *e;
|
|
|
|
unsigned long val;
|
|
|
|
unsigned long dom = 0, bus = 0;
|
2010-09-06 15:46:19 +08:00
|
|
|
unsigned int slot = 0;
|
|
|
|
unsigned int func = 0;
|
2009-02-11 23:21:48 +08:00
|
|
|
|
|
|
|
p = addr;
|
|
|
|
val = strtoul(p, &e, 16);
|
|
|
|
if (e == p)
|
|
|
|
return -1;
|
|
|
|
if (*e == ':') {
|
|
|
|
bus = val;
|
|
|
|
p = e + 1;
|
|
|
|
val = strtoul(p, &e, 16);
|
|
|
|
if (e == p)
|
|
|
|
return -1;
|
|
|
|
if (*e == ':') {
|
|
|
|
dom = bus;
|
|
|
|
bus = val;
|
|
|
|
p = e + 1;
|
|
|
|
val = strtoul(p, &e, 16);
|
|
|
|
if (e == p)
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
slot = val;
|
|
|
|
|
2010-09-06 15:46:19 +08:00
|
|
|
if (funcp != NULL) {
|
|
|
|
if (*e != '.')
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
p = e + 1;
|
|
|
|
val = strtoul(p, &e, 16);
|
|
|
|
if (e == p)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
func = val;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* if funcp == NULL func is 0 */
|
|
|
|
if (dom > 0xffff || bus > 0xff || slot > 0x1f || func > 7)
|
|
|
|
return -1;
|
|
|
|
|
2009-02-11 23:21:48 +08:00
|
|
|
if (*e)
|
|
|
|
return -1;
|
|
|
|
|
|
|
|
/* Note: QEMU doesn't implement domains other than 0 */
|
2009-11-12 13:58:36 +08:00
|
|
|
if (!pci_find_bus(pci_find_root_bus(dom), bus))
|
2009-02-11 23:21:48 +08:00
|
|
|
return -1;
|
|
|
|
|
|
|
|
*domp = dom;
|
|
|
|
*busp = bus;
|
|
|
|
*slotp = slot;
|
2010-09-06 15:46:19 +08:00
|
|
|
if (funcp != NULL)
|
|
|
|
*funcp = func;
|
2009-02-11 23:21:48 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-26 06:04:00 +08:00
|
|
|
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
|
|
|
|
unsigned *slotp)
|
2009-02-11 23:21:48 +08:00
|
|
|
{
|
2009-06-26 06:04:00 +08:00
|
|
|
/* strip legacy tag */
|
|
|
|
if (!strncmp(addr, "pci_addr=", 9)) {
|
|
|
|
addr += 9;
|
|
|
|
}
|
2010-09-06 15:46:19 +08:00
|
|
|
if (pci_parse_devaddr(addr, domp, busp, slotp, NULL)) {
|
2009-06-26 06:04:00 +08:00
|
|
|
monitor_printf(mon, "Invalid pci address\n");
|
2009-02-11 23:21:48 +08:00
|
|
|
return -1;
|
2009-06-26 06:04:00 +08:00
|
|
|
}
|
|
|
|
return 0;
|
2009-02-11 23:21:48 +08:00
|
|
|
}
|
|
|
|
|
2009-09-25 09:53:49 +08:00
|
|
|
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr)
|
2009-06-18 21:14:08 +08:00
|
|
|
{
|
|
|
|
int dom, bus;
|
|
|
|
unsigned slot;
|
|
|
|
|
|
|
|
if (!devaddr) {
|
|
|
|
*devfnp = -1;
|
2009-11-12 13:58:36 +08:00
|
|
|
return pci_find_bus(pci_find_root_bus(0), 0);
|
2009-06-18 21:14:08 +08:00
|
|
|
}
|
|
|
|
|
2010-09-06 15:46:19 +08:00
|
|
|
if (pci_parse_devaddr(devaddr, &dom, &bus, &slot, NULL) < 0) {
|
2009-06-18 21:14:08 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
|
|
|
*devfnp = slot << 3;
|
2010-05-28 17:30:46 +08:00
|
|
|
return pci_find_bus(pci_find_root_bus(dom), bus);
|
2009-06-18 21:14:08 +08:00
|
|
|
}
|
|
|
|
|
2009-06-22 00:49:40 +08:00
|
|
|
static void pci_init_cmask(PCIDevice *dev)
|
|
|
|
{
|
|
|
|
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
|
|
|
|
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
|
|
|
|
dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
|
|
|
|
dev->cmask[PCI_REVISION_ID] = 0xff;
|
|
|
|
dev->cmask[PCI_CLASS_PROG] = 0xff;
|
|
|
|
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
|
|
|
|
dev->cmask[PCI_HEADER_TYPE] = 0xff;
|
|
|
|
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
|
|
|
|
}
|
|
|
|
|
2009-06-22 00:45:18 +08:00
|
|
|
static void pci_init_wmask(PCIDevice *dev)
|
|
|
|
{
|
2009-10-30 20:21:18 +08:00
|
|
|
int config_size = pci_config_size(dev);
|
|
|
|
|
2009-06-22 00:45:18 +08:00
|
|
|
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
|
|
|
|
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
|
2009-10-30 20:21:02 +08:00
|
|
|
pci_set_word(dev->wmask + PCI_COMMAND,
|
2009-12-23 22:33:56 +08:00
|
|
|
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
|
|
|
|
PCI_COMMAND_INTX_DISABLE);
|
2009-11-12 13:58:39 +08:00
|
|
|
|
|
|
|
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
|
|
|
|
config_size - PCI_CONFIG_HEADER_SIZE);
|
2009-06-22 00:45:18 +08:00
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:22 +08:00
|
|
|
static void pci_init_wmask_bridge(PCIDevice *d)
|
|
|
|
{
|
|
|
|
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
|
|
|
|
PCI_SEC_LETENCY_TIMER */
|
|
|
|
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
|
|
|
|
|
|
|
|
/* base and limit */
|
|
|
|
d->wmask[PCI_IO_BASE] = PCI_IO_RANGE_MASK & 0xff;
|
|
|
|
d->wmask[PCI_IO_LIMIT] = PCI_IO_RANGE_MASK & 0xff;
|
|
|
|
pci_set_word(d->wmask + PCI_MEMORY_BASE,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_set_word(d->wmask + PCI_MEMORY_LIMIT,
|
|
|
|
PCI_MEMORY_RANGE_MASK & 0xffff);
|
|
|
|
pci_set_word(d->wmask + PCI_PREF_MEMORY_BASE,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
|
|
|
pci_set_word(d->wmask + PCI_PREF_MEMORY_LIMIT,
|
|
|
|
PCI_PREF_RANGE_MASK & 0xffff);
|
|
|
|
|
|
|
|
/* PCI_PREF_BASE_UPPER32 and PCI_PREF_LIMIT_UPPER32 */
|
|
|
|
memset(d->wmask + PCI_PREF_BASE_UPPER32, 0xff, 8);
|
|
|
|
|
|
|
|
pci_set_word(d->wmask + PCI_BRIDGE_CONTROL, 0xffff);
|
|
|
|
}
|
|
|
|
|
2010-06-23 15:15:33 +08:00
|
|
|
static int pci_init_multifunction(PCIBus *bus, PCIDevice *dev)
|
|
|
|
{
|
|
|
|
uint8_t slot = PCI_SLOT(dev->devfn);
|
|
|
|
uint8_t func;
|
|
|
|
|
|
|
|
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
|
|
|
dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* multifuction bit is interpreted in two ways as follows.
|
|
|
|
* - all functions must set the bit to 1.
|
|
|
|
* Example: Intel X53
|
|
|
|
* - function 0 must set the bit, but the rest function (> 0)
|
|
|
|
* is allowed to leave the bit to 0.
|
|
|
|
* Example: PIIX3(also in qemu), PIIX4(also in qemu), ICH10,
|
|
|
|
*
|
|
|
|
* So OS (at least Linux) checks the bit of only function 0,
|
|
|
|
* and doesn't see the bit of function > 0.
|
|
|
|
*
|
|
|
|
* The below check allows both interpretation.
|
|
|
|
*/
|
|
|
|
if (PCI_FUNC(dev->devfn)) {
|
|
|
|
PCIDevice *f0 = bus->devices[PCI_DEVFN(slot, 0)];
|
|
|
|
if (f0 && !(f0->cap_present & QEMU_PCI_CAP_MULTIFUNCTION)) {
|
|
|
|
/* function 0 should set multifunction bit */
|
|
|
|
error_report("PCI: single function device can't be populated "
|
|
|
|
"in function %x.%x", slot, PCI_FUNC(dev->devfn));
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) {
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
/* function 0 indicates single function, so function > 0 must be NULL */
|
|
|
|
for (func = 1; func < PCI_FUNC_MAX; ++func) {
|
|
|
|
if (bus->devices[PCI_DEVFN(slot, func)]) {
|
|
|
|
error_report("PCI: %x.0 indicates single function, "
|
|
|
|
"but %x.%x is already populated.",
|
|
|
|
slot, slot, func);
|
|
|
|
return -1;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:18 +08:00
|
|
|
static void pci_config_alloc(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
int config_size = pci_config_size(pci_dev);
|
|
|
|
|
|
|
|
pci_dev->config = qemu_mallocz(config_size);
|
|
|
|
pci_dev->cmask = qemu_mallocz(config_size);
|
|
|
|
pci_dev->wmask = qemu_mallocz(config_size);
|
|
|
|
pci_dev->used = qemu_mallocz(config_size);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_config_free(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
qemu_free(pci_dev->config);
|
|
|
|
qemu_free(pci_dev->cmask);
|
|
|
|
qemu_free(pci_dev->wmask);
|
|
|
|
qemu_free(pci_dev->used);
|
|
|
|
}
|
|
|
|
|
2004-05-19 07:05:28 +08:00
|
|
|
/* -1 for devfn means auto assign */
|
2009-05-15 05:35:07 +08:00
|
|
|
static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
|
|
|
|
const char *name, int devfn,
|
|
|
|
PCIConfigReadFunc *config_read,
|
2009-10-30 20:21:22 +08:00
|
|
|
PCIConfigWriteFunc *config_write,
|
2010-06-23 15:15:28 +08:00
|
|
|
bool is_bridge)
|
2004-05-19 07:05:28 +08:00
|
|
|
{
|
|
|
|
if (devfn < 0) {
|
2009-11-12 13:58:45 +08:00
|
|
|
for(devfn = bus->devfn_min ; devfn < ARRAY_SIZE(bus->devices);
|
2010-06-23 15:15:26 +08:00
|
|
|
devfn += PCI_FUNC_MAX) {
|
2004-06-22 03:45:35 +08:00
|
|
|
if (!bus->devices[devfn])
|
2004-05-19 07:05:28 +08:00
|
|
|
goto found;
|
|
|
|
}
|
Clarify error message when a PCI slot is already in use (v2)
When mistakenly configuring two devices in the same PCI slot,
QEMU gives a not entirely obvious message about a 'devfn' being
in use:
$ qemu -device rtl8139 -device virtio-balloon-pci,bus=pci.0,addr=0x3
qemu-kvm: -device virtio-balloon-pci,bus=pci.0,addr=0x3: PCI: devfn 24 not available for virtio-balloon-pci, in use by rtl8139
The user does not configure 'devfn' numbers, they use slot+function.
Thus the error messages should be reported back to the user with that
same terminology rather than the internal QEMU terminology. This
patch makes it report:
$ qemu -device rtl8139 -device virtio-balloon-pci,bus=pci.0,addr=0x3
qemu: -device virtio-balloon-pci,bus=pci.0,addr=0x3.7: PCI: slot 3 function 0 not available for virtio-balloon-pci, in use by rtl8139
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-06-08 22:24:25 +08:00
|
|
|
error_report("PCI: no slot/function available for %s, all in use", name);
|
2009-12-10 18:11:06 +08:00
|
|
|
return NULL;
|
2004-05-19 07:05:28 +08:00
|
|
|
found: ;
|
2009-06-18 21:14:07 +08:00
|
|
|
} else if (bus->devices[devfn]) {
|
Clarify error message when a PCI slot is already in use (v2)
When mistakenly configuring two devices in the same PCI slot,
QEMU gives a not entirely obvious message about a 'devfn' being
in use:
$ qemu -device rtl8139 -device virtio-balloon-pci,bus=pci.0,addr=0x3
qemu-kvm: -device virtio-balloon-pci,bus=pci.0,addr=0x3: PCI: devfn 24 not available for virtio-balloon-pci, in use by rtl8139
The user does not configure 'devfn' numbers, they use slot+function.
Thus the error messages should be reported back to the user with that
same terminology rather than the internal QEMU terminology. This
patch makes it report:
$ qemu -device rtl8139 -device virtio-balloon-pci,bus=pci.0,addr=0x3
qemu: -device virtio-balloon-pci,bus=pci.0,addr=0x3.7: PCI: slot 3 function 0 not available for virtio-balloon-pci, in use by rtl8139
Signed-off-by: Daniel P. Berrange <berrange@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
2010-06-08 22:24:25 +08:00
|
|
|
error_report("PCI: slot %d function %d not available for %s, in use by %s",
|
|
|
|
PCI_SLOT(devfn), PCI_FUNC(devfn), name, bus->devices[devfn]->name);
|
2009-12-10 18:11:06 +08:00
|
|
|
return NULL;
|
2004-05-19 07:05:28 +08:00
|
|
|
}
|
2004-06-22 03:45:35 +08:00
|
|
|
pci_dev->bus = bus;
|
2004-05-19 07:05:28 +08:00
|
|
|
pci_dev->devfn = devfn;
|
|
|
|
pstrcpy(pci_dev->name, sizeof(pci_dev->name), name);
|
2009-11-25 21:20:51 +08:00
|
|
|
pci_dev->irq_state = 0;
|
2009-10-30 20:21:18 +08:00
|
|
|
pci_config_alloc(pci_dev);
|
2009-10-30 20:21:22 +08:00
|
|
|
|
2010-06-23 15:15:28 +08:00
|
|
|
if (!is_bridge) {
|
2009-10-30 20:21:22 +08:00
|
|
|
pci_set_default_subsystem_id(pci_dev);
|
|
|
|
}
|
2009-06-22 00:49:40 +08:00
|
|
|
pci_init_cmask(pci_dev);
|
2009-06-22 00:45:18 +08:00
|
|
|
pci_init_wmask(pci_dev);
|
2010-06-23 15:15:28 +08:00
|
|
|
if (is_bridge) {
|
2009-10-30 20:21:22 +08:00
|
|
|
pci_init_wmask_bridge(pci_dev);
|
|
|
|
}
|
2010-06-23 15:15:33 +08:00
|
|
|
if (pci_init_multifunction(bus, pci_dev)) {
|
|
|
|
pci_config_free(pci_dev);
|
|
|
|
return NULL;
|
|
|
|
}
|
2004-05-20 20:45:00 +08:00
|
|
|
|
|
|
|
if (!config_read)
|
|
|
|
config_read = pci_default_read_config;
|
|
|
|
if (!config_write)
|
|
|
|
config_write = pci_default_write_config;
|
2004-05-19 07:05:28 +08:00
|
|
|
pci_dev->config_read = config_read;
|
|
|
|
pci_dev->config_write = config_write;
|
2004-06-22 03:45:35 +08:00
|
|
|
bus->devices[devfn] = pci_dev;
|
2009-10-30 20:20:56 +08:00
|
|
|
pci_dev->irq = qemu_allocate_irqs(pci_set_irq, pci_dev, PCI_NUM_PINS);
|
2009-08-21 01:42:38 +08:00
|
|
|
pci_dev->version_id = 2; /* Current pci device vmstate version */
|
2004-05-19 07:05:28 +08:00
|
|
|
return pci_dev;
|
|
|
|
}
|
|
|
|
|
2010-05-11 18:44:21 +08:00
|
|
|
static void do_pci_unregister_device(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
qemu_free_irqs(pci_dev->irq);
|
|
|
|
pci_dev->bus->devices[pci_dev->devfn] = NULL;
|
|
|
|
pci_config_free(pci_dev);
|
|
|
|
}
|
|
|
|
|
2009-05-15 05:35:07 +08:00
|
|
|
PCIDevice *pci_register_device(PCIBus *bus, const char *name,
|
|
|
|
int instance_size, int devfn,
|
|
|
|
PCIConfigReadFunc *config_read,
|
|
|
|
PCIConfigWriteFunc *config_write)
|
|
|
|
{
|
|
|
|
PCIDevice *pci_dev;
|
|
|
|
|
|
|
|
pci_dev = qemu_mallocz(instance_size);
|
|
|
|
pci_dev = do_pci_register_device(pci_dev, bus, name, devfn,
|
2009-10-30 20:21:22 +08:00
|
|
|
config_read, config_write,
|
|
|
|
PCI_HEADER_TYPE_NORMAL);
|
2009-12-10 18:11:06 +08:00
|
|
|
if (pci_dev == NULL) {
|
|
|
|
hw_error("PCI: can't register device\n");
|
|
|
|
}
|
2009-05-15 05:35:07 +08:00
|
|
|
return pci_dev;
|
|
|
|
}
|
2009-12-26 00:50:36 +08:00
|
|
|
|
|
|
|
static target_phys_addr_t pci_to_cpu_addr(PCIBus *bus,
|
|
|
|
target_phys_addr_t addr)
|
2009-02-11 23:21:10 +08:00
|
|
|
{
|
2009-12-26 00:50:36 +08:00
|
|
|
return addr + bus->mem_base;
|
2009-02-11 23:21:10 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_unregister_io_regions(PCIDevice *pci_dev)
|
|
|
|
{
|
|
|
|
PCIIORegion *r;
|
|
|
|
int i;
|
|
|
|
|
|
|
|
for(i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
|
|
r = &pci_dev->io_regions[i];
|
2009-10-30 20:20:58 +08:00
|
|
|
if (!r->size || r->addr == PCI_BAR_UNMAPPED)
|
2009-02-11 23:21:10 +08:00
|
|
|
continue;
|
2009-10-30 20:21:03 +08:00
|
|
|
if (r->type == PCI_BASE_ADDRESS_SPACE_IO) {
|
2009-10-30 20:21:25 +08:00
|
|
|
isa_unassign_ioport(r->addr, r->filtered_size);
|
2009-02-11 23:21:10 +08:00
|
|
|
} else {
|
2009-12-26 00:50:36 +08:00
|
|
|
cpu_register_physical_memory(pci_to_cpu_addr(pci_dev->bus,
|
|
|
|
r->addr),
|
|
|
|
r->filtered_size,
|
|
|
|
IO_MEM_UNASSIGNED);
|
2009-02-11 23:21:10 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-09-26 03:42:37 +08:00
|
|
|
static int pci_unregister_device(DeviceState *dev)
|
2009-02-11 23:21:10 +08:00
|
|
|
{
|
2009-09-26 03:42:37 +08:00
|
|
|
PCIDevice *pci_dev = DO_UPCAST(PCIDevice, qdev, dev);
|
2009-09-26 03:42:38 +08:00
|
|
|
PCIDeviceInfo *info = DO_UPCAST(PCIDeviceInfo, qdev, dev->info);
|
2009-02-11 23:21:10 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
2009-09-26 03:42:38 +08:00
|
|
|
if (info->exit)
|
|
|
|
ret = info->exit(pci_dev);
|
2009-02-11 23:21:10 +08:00
|
|
|
if (ret)
|
|
|
|
return ret;
|
|
|
|
|
|
|
|
pci_unregister_io_regions(pci_dev);
|
2010-06-26 01:10:19 +08:00
|
|
|
pci_del_option_rom(pci_dev);
|
2010-05-11 18:44:21 +08:00
|
|
|
do_pci_unregister_device(pci_dev);
|
2009-02-11 23:21:10 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-06-14 16:38:53 +08:00
|
|
|
void pci_register_bar(PCIDevice *pci_dev, int region_num,
|
2009-10-30 20:21:08 +08:00
|
|
|
pcibus_t size, int type,
|
2004-05-19 07:05:28 +08:00
|
|
|
PCIMapIORegionFunc *map_func)
|
|
|
|
{
|
|
|
|
PCIIORegion *r;
|
2006-04-19 00:55:22 +08:00
|
|
|
uint32_t addr;
|
2009-10-30 20:21:08 +08:00
|
|
|
pcibus_t wmask;
|
2004-05-19 07:05:28 +08:00
|
|
|
|
2004-06-03 22:06:32 +08:00
|
|
|
if ((unsigned int)region_num >= PCI_NUM_REGIONS)
|
2004-05-19 07:05:28 +08:00
|
|
|
return;
|
2009-02-11 23:21:16 +08:00
|
|
|
|
|
|
|
if (size & (size-1)) {
|
|
|
|
fprintf(stderr, "ERROR: PCI region size must be pow2 "
|
2009-10-30 20:21:09 +08:00
|
|
|
"type=0x%x, size=0x%"FMT_PCIBUS"\n", type, size);
|
2009-02-11 23:21:16 +08:00
|
|
|
exit(1);
|
|
|
|
}
|
|
|
|
|
2004-05-19 07:05:28 +08:00
|
|
|
r = &pci_dev->io_regions[region_num];
|
2009-10-30 20:20:58 +08:00
|
|
|
r->addr = PCI_BAR_UNMAPPED;
|
2004-05-19 07:05:28 +08:00
|
|
|
r->size = size;
|
2009-10-30 20:21:25 +08:00
|
|
|
r->filtered_size = size;
|
2004-05-19 07:05:28 +08:00
|
|
|
r->type = type;
|
|
|
|
r->map_func = map_func;
|
2009-06-22 00:45:18 +08:00
|
|
|
|
|
|
|
wmask = ~(size - 1);
|
2009-10-30 20:21:05 +08:00
|
|
|
addr = pci_bar(pci_dev, region_num);
|
2006-04-19 00:55:22 +08:00
|
|
|
if (region_num == PCI_ROM_SLOT) {
|
2009-06-22 00:45:18 +08:00
|
|
|
/* ROM enable bit is writeable */
|
2009-09-16 18:40:57 +08:00
|
|
|
wmask |= PCI_ROM_ADDRESS_ENABLE;
|
2006-04-19 00:55:22 +08:00
|
|
|
}
|
2009-10-30 20:21:00 +08:00
|
|
|
pci_set_long(pci_dev->config + addr, type);
|
2009-10-30 20:21:11 +08:00
|
|
|
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
|
|
|
|
r->type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
|
|
|
pci_set_quad(pci_dev->wmask + addr, wmask);
|
|
|
|
pci_set_quad(pci_dev->cmask + addr, ~0ULL);
|
|
|
|
} else {
|
|
|
|
pci_set_long(pci_dev->wmask + addr, wmask & 0xffffffff);
|
|
|
|
pci_set_long(pci_dev->cmask + addr, 0xffffffff);
|
|
|
|
}
|
2004-05-19 07:05:28 +08:00
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:25 +08:00
|
|
|
static void pci_bridge_filter(PCIDevice *d, pcibus_t *addr, pcibus_t *size,
|
|
|
|
uint8_t type)
|
|
|
|
{
|
|
|
|
pcibus_t base = *addr;
|
|
|
|
pcibus_t limit = *addr + *size - 1;
|
|
|
|
PCIDevice *br;
|
|
|
|
|
|
|
|
for (br = d->bus->parent_dev; br; br = br->bus->parent_dev) {
|
|
|
|
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
|
|
|
|
|
|
|
|
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
if (!(cmd & PCI_COMMAND_IO)) {
|
|
|
|
goto no_map;
|
|
|
|
}
|
|
|
|
} else {
|
|
|
|
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
|
|
|
goto no_map;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
base = MAX(base, pci_bridge_get_base(br, type));
|
|
|
|
limit = MIN(limit, pci_bridge_get_limit(br, type));
|
|
|
|
}
|
|
|
|
|
|
|
|
if (base > limit) {
|
2009-11-12 19:54:31 +08:00
|
|
|
goto no_map;
|
2009-10-30 20:21:25 +08:00
|
|
|
}
|
2009-11-12 19:54:31 +08:00
|
|
|
*addr = base;
|
|
|
|
*size = limit - base + 1;
|
|
|
|
return;
|
|
|
|
no_map:
|
|
|
|
*addr = PCI_BAR_UNMAPPED;
|
|
|
|
*size = 0;
|
2009-10-30 20:21:25 +08:00
|
|
|
}
|
|
|
|
|
2009-11-12 19:47:17 +08:00
|
|
|
static pcibus_t pci_bar_address(PCIDevice *d,
|
|
|
|
int reg, uint8_t type, pcibus_t size)
|
|
|
|
{
|
|
|
|
pcibus_t new_addr, last_addr;
|
|
|
|
int bar = pci_bar(d, reg);
|
|
|
|
uint16_t cmd = pci_get_word(d->config + PCI_COMMAND);
|
|
|
|
|
|
|
|
if (type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
if (!(cmd & PCI_COMMAND_IO)) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
new_addr = pci_get_long(d->config + bar) & ~(size - 1);
|
|
|
|
last_addr = new_addr + size - 1;
|
|
|
|
/* NOTE: we have only 64K ioports on PC */
|
|
|
|
if (last_addr <= new_addr || new_addr == 0 || last_addr > UINT16_MAX) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
return new_addr;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (!(cmd & PCI_COMMAND_MEMORY)) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
if (type & PCI_BASE_ADDRESS_MEM_TYPE_64) {
|
|
|
|
new_addr = pci_get_quad(d->config + bar);
|
|
|
|
} else {
|
|
|
|
new_addr = pci_get_long(d->config + bar);
|
|
|
|
}
|
|
|
|
/* the ROM slot has a specific enable bit */
|
|
|
|
if (reg == PCI_ROM_SLOT && !(new_addr & PCI_ROM_ADDRESS_ENABLE)) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
new_addr &= ~(size - 1);
|
|
|
|
last_addr = new_addr + size - 1;
|
|
|
|
/* NOTE: we do not support wrapping */
|
|
|
|
/* XXX: as we cannot support really dynamic
|
|
|
|
mappings, we handle specific values as invalid
|
|
|
|
mappings. */
|
|
|
|
if (last_addr <= new_addr || new_addr == 0 ||
|
|
|
|
last_addr == PCI_BAR_UNMAPPED) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Now pcibus_t is 64bit.
|
|
|
|
* Check if 32 bit BAR wraps around explicitly.
|
|
|
|
* Without this, PC ide doesn't work well.
|
|
|
|
* TODO: remove this work around.
|
|
|
|
*/
|
|
|
|
if (!(type & PCI_BASE_ADDRESS_MEM_TYPE_64) && last_addr >= UINT32_MAX) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
|
|
|
|
/*
|
|
|
|
* OS is allowed to set BAR beyond its addressable
|
|
|
|
* bits. For example, 32 bit OS can set 64bit bar
|
|
|
|
* to >4G. Check it. TODO: we might need to support
|
|
|
|
* it in the future for e.g. PAE.
|
|
|
|
*/
|
|
|
|
if (last_addr >= TARGET_PHYS_ADDR_MAX) {
|
|
|
|
return PCI_BAR_UNMAPPED;
|
|
|
|
}
|
|
|
|
|
|
|
|
return new_addr;
|
|
|
|
}
|
|
|
|
|
2004-05-20 20:45:00 +08:00
|
|
|
static void pci_update_mappings(PCIDevice *d)
|
|
|
|
{
|
|
|
|
PCIIORegion *r;
|
2009-11-12 19:47:17 +08:00
|
|
|
int i;
|
2009-12-26 02:18:29 +08:00
|
|
|
pcibus_t new_addr, filtered_size;
|
2007-09-17 16:09:54 +08:00
|
|
|
|
2004-06-03 22:06:32 +08:00
|
|
|
for(i = 0; i < PCI_NUM_REGIONS; i++) {
|
2004-05-20 20:45:00 +08:00
|
|
|
r = &d->io_regions[i];
|
2009-10-30 20:21:23 +08:00
|
|
|
|
|
|
|
/* this region isn't registered */
|
2009-11-12 13:58:43 +08:00
|
|
|
if (!r->size)
|
2009-10-30 20:21:23 +08:00
|
|
|
continue;
|
|
|
|
|
2009-11-12 19:47:17 +08:00
|
|
|
new_addr = pci_bar_address(d, i, r->type, r->size);
|
2009-10-30 20:21:23 +08:00
|
|
|
|
2009-10-30 20:21:25 +08:00
|
|
|
/* bridge filtering */
|
|
|
|
filtered_size = r->size;
|
|
|
|
if (new_addr != PCI_BAR_UNMAPPED) {
|
|
|
|
pci_bridge_filter(d, &new_addr, &filtered_size, r->type);
|
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:23 +08:00
|
|
|
/* This bar isn't changed */
|
2009-10-30 20:21:25 +08:00
|
|
|
if (new_addr == r->addr && filtered_size == r->filtered_size)
|
2009-10-30 20:21:23 +08:00
|
|
|
continue;
|
|
|
|
|
|
|
|
/* now do the real mapping */
|
|
|
|
if (r->addr != PCI_BAR_UNMAPPED) {
|
|
|
|
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
int class;
|
|
|
|
/* NOTE: specific hack for IDE in PC case:
|
|
|
|
only one byte must be mapped. */
|
|
|
|
class = pci_get_word(d->config + PCI_CLASS_DEVICE);
|
|
|
|
if (class == 0x0101 && r->size == 4) {
|
|
|
|
isa_unassign_ioport(r->addr + 2, 1);
|
|
|
|
} else {
|
2009-10-30 20:21:25 +08:00
|
|
|
isa_unassign_ioport(r->addr, r->filtered_size);
|
2004-05-20 20:45:00 +08:00
|
|
|
}
|
2009-10-30 20:21:23 +08:00
|
|
|
} else {
|
2009-12-26 02:18:29 +08:00
|
|
|
cpu_register_physical_memory(pci_to_cpu_addr(d->bus, r->addr),
|
2009-10-30 20:21:25 +08:00
|
|
|
r->filtered_size,
|
2009-10-30 20:21:23 +08:00
|
|
|
IO_MEM_UNASSIGNED);
|
2009-10-30 20:21:25 +08:00
|
|
|
qemu_unregister_coalesced_mmio(r->addr, r->filtered_size);
|
2004-05-20 20:45:00 +08:00
|
|
|
}
|
|
|
|
}
|
2009-10-30 20:21:23 +08:00
|
|
|
r->addr = new_addr;
|
2009-10-30 20:21:25 +08:00
|
|
|
r->filtered_size = filtered_size;
|
2009-10-30 20:21:23 +08:00
|
|
|
if (r->addr != PCI_BAR_UNMAPPED) {
|
2009-10-30 20:21:25 +08:00
|
|
|
/*
|
|
|
|
* TODO: currently almost all the map funcions assumes
|
|
|
|
* filtered_size == size and addr & ~(size - 1) == addr.
|
|
|
|
* However with bridge filtering, they aren't always true.
|
|
|
|
* Teach them such cases, such that filtered_size < size and
|
|
|
|
* addr & (size - 1) != 0.
|
|
|
|
*/
|
2009-12-28 04:52:36 +08:00
|
|
|
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
r->map_func(d, i, r->addr, r->filtered_size, r->type);
|
|
|
|
} else {
|
|
|
|
r->map_func(d, i, pci_to_cpu_addr(d->bus, r->addr),
|
|
|
|
r->filtered_size, r->type);
|
|
|
|
}
|
2009-10-30 20:21:23 +08:00
|
|
|
}
|
2004-05-20 20:45:00 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-12-23 22:33:56 +08:00
|
|
|
static inline int pci_irq_disabled(PCIDevice *d)
|
|
|
|
{
|
|
|
|
return pci_get_word(d->config + PCI_COMMAND) & PCI_COMMAND_INTX_DISABLE;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Called after interrupt disabled field update in config space,
|
|
|
|
* assert/deassert interrupts if necessary.
|
|
|
|
* Gets original interrupt disable bit value (before update). */
|
|
|
|
static void pci_update_irq_disabled(PCIDevice *d, int was_irq_disabled)
|
|
|
|
{
|
|
|
|
int i, disabled = pci_irq_disabled(d);
|
|
|
|
if (disabled == was_irq_disabled)
|
|
|
|
return;
|
|
|
|
for (i = 0; i < PCI_NUM_PINS; ++i) {
|
|
|
|
int state = pci_irq_state(d, i);
|
|
|
|
pci_change_irq_level(d, i, disabled ? -state : state);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2007-09-17 05:08:06 +08:00
|
|
|
uint32_t pci_default_read_config(PCIDevice *d,
|
2004-05-20 20:45:00 +08:00
|
|
|
uint32_t address, int len)
|
2004-05-19 07:05:28 +08:00
|
|
|
{
|
2009-10-30 20:21:04 +08:00
|
|
|
uint32_t val = 0;
|
|
|
|
assert(len == 1 || len == 2 || len == 4);
|
2009-10-30 20:21:18 +08:00
|
|
|
len = MIN(len, pci_config_size(d) - address);
|
2009-10-30 20:21:04 +08:00
|
|
|
memcpy(&val, d->config + address, len);
|
|
|
|
return le32_to_cpu(val);
|
2004-05-20 20:45:00 +08:00
|
|
|
}
|
|
|
|
|
2009-06-22 00:45:18 +08:00
|
|
|
void pci_default_write_config(PCIDevice *d, uint32_t addr, uint32_t val, int l)
|
2004-05-20 20:45:00 +08:00
|
|
|
{
|
2009-12-23 22:33:56 +08:00
|
|
|
int i, was_irq_disabled = pci_irq_disabled(d);
|
2009-10-30 20:21:18 +08:00
|
|
|
uint32_t config_size = pci_config_size(d);
|
2004-05-20 20:45:00 +08:00
|
|
|
|
2009-11-14 06:26:27 +08:00
|
|
|
for (i = 0; i < l && addr + i < config_size; val >>= 8, ++i) {
|
|
|
|
uint8_t wmask = d->wmask[addr + i];
|
|
|
|
d->config[addr + i] = (d->config[addr + i] & ~wmask) | (val & wmask);
|
2004-05-20 20:45:00 +08:00
|
|
|
}
|
2009-10-30 20:21:20 +08:00
|
|
|
if (ranges_overlap(addr, l, PCI_BASE_ADDRESS_0, 24) ||
|
2009-10-30 20:21:21 +08:00
|
|
|
ranges_overlap(addr, l, PCI_ROM_ADDRESS, 4) ||
|
|
|
|
ranges_overlap(addr, l, PCI_ROM_ADDRESS1, 4) ||
|
2009-10-30 20:21:20 +08:00
|
|
|
range_covers_byte(addr, l, PCI_COMMAND))
|
2004-05-20 20:45:00 +08:00
|
|
|
pci_update_mappings(d);
|
2009-12-23 22:33:56 +08:00
|
|
|
|
|
|
|
if (range_covers_byte(addr, l, PCI_COMMAND))
|
|
|
|
pci_update_irq_disabled(d, was_irq_disabled);
|
2004-05-19 07:05:28 +08:00
|
|
|
}
|
|
|
|
|
2006-05-14 00:11:23 +08:00
|
|
|
/***********************************************************/
|
|
|
|
/* generic PCI irq support */
|
2004-06-22 03:45:35 +08:00
|
|
|
|
2006-05-14 00:11:23 +08:00
|
|
|
/* 0 <= irq_num <= 3. level must be 0 or 1 */
|
2007-04-08 02:14:41 +08:00
|
|
|
static void pci_set_irq(void *opaque, int irq_num, int level)
|
2004-05-19 07:05:28 +08:00
|
|
|
{
|
2009-08-25 00:42:53 +08:00
|
|
|
PCIDevice *pci_dev = opaque;
|
2006-09-25 01:01:44 +08:00
|
|
|
int change;
|
2007-09-17 16:09:54 +08:00
|
|
|
|
2009-11-25 21:20:51 +08:00
|
|
|
change = level - pci_irq_state(pci_dev, irq_num);
|
2006-09-25 01:01:44 +08:00
|
|
|
if (!change)
|
|
|
|
return;
|
2006-09-24 08:16:34 +08:00
|
|
|
|
2009-11-25 21:20:51 +08:00
|
|
|
pci_set_irq_state(pci_dev, irq_num, level);
|
2009-11-25 21:44:40 +08:00
|
|
|
pci_update_irq_status(pci_dev);
|
2009-12-23 22:33:56 +08:00
|
|
|
if (pci_irq_disabled(pci_dev))
|
|
|
|
return;
|
2009-11-25 21:20:51 +08:00
|
|
|
pci_change_irq_level(pci_dev, irq_num, change);
|
2004-05-19 07:05:28 +08:00
|
|
|
}
|
|
|
|
|
2006-05-14 00:11:23 +08:00
|
|
|
/***********************************************************/
|
|
|
|
/* monitor info on PCI */
|
2004-05-20 20:45:00 +08:00
|
|
|
|
2006-05-21 21:45:09 +08:00
|
|
|
typedef struct {
|
|
|
|
uint16_t class;
|
|
|
|
const char *desc;
|
|
|
|
} pci_class_desc;
|
|
|
|
|
2008-10-03 02:33:50 +08:00
|
|
|
static const pci_class_desc pci_class_descriptions[] =
|
2006-05-21 21:45:09 +08:00
|
|
|
{
|
2006-08-10 09:03:35 +08:00
|
|
|
{ 0x0100, "SCSI controller"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0101, "IDE controller"},
|
2007-04-14 20:24:46 +08:00
|
|
|
{ 0x0102, "Floppy controller"},
|
|
|
|
{ 0x0103, "IPI controller"},
|
|
|
|
{ 0x0104, "RAID controller"},
|
|
|
|
{ 0x0106, "SATA controller"},
|
|
|
|
{ 0x0107, "SAS controller"},
|
|
|
|
{ 0x0180, "Storage controller"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0200, "Ethernet controller"},
|
2007-04-14 20:24:46 +08:00
|
|
|
{ 0x0201, "Token Ring controller"},
|
|
|
|
{ 0x0202, "FDDI controller"},
|
|
|
|
{ 0x0203, "ATM controller"},
|
|
|
|
{ 0x0280, "Network controller"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0300, "VGA controller"},
|
2007-04-14 20:24:46 +08:00
|
|
|
{ 0x0301, "XGA controller"},
|
|
|
|
{ 0x0302, "3D controller"},
|
|
|
|
{ 0x0380, "Display controller"},
|
|
|
|
{ 0x0400, "Video controller"},
|
|
|
|
{ 0x0401, "Audio controller"},
|
|
|
|
{ 0x0402, "Phone"},
|
|
|
|
{ 0x0480, "Multimedia controller"},
|
|
|
|
{ 0x0500, "RAM controller"},
|
|
|
|
{ 0x0501, "Flash controller"},
|
|
|
|
{ 0x0580, "Memory controller"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0600, "Host bridge"},
|
|
|
|
{ 0x0601, "ISA bridge"},
|
2007-04-14 20:24:46 +08:00
|
|
|
{ 0x0602, "EISA bridge"},
|
|
|
|
{ 0x0603, "MC bridge"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0604, "PCI bridge"},
|
2007-04-14 20:24:46 +08:00
|
|
|
{ 0x0605, "PCMCIA bridge"},
|
|
|
|
{ 0x0606, "NUBUS bridge"},
|
|
|
|
{ 0x0607, "CARDBUS bridge"},
|
|
|
|
{ 0x0608, "RACEWAY bridge"},
|
|
|
|
{ 0x0680, "Bridge"},
|
2006-05-21 21:45:09 +08:00
|
|
|
{ 0x0c03, "USB controller"},
|
|
|
|
{ 0, NULL}
|
|
|
|
};
|
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
static void pci_for_each_device_under_bus(PCIBus *bus,
|
|
|
|
void (*fn)(PCIBus *b, PCIDevice *d))
|
2004-06-22 03:45:35 +08:00
|
|
|
{
|
2010-01-22 05:15:40 +08:00
|
|
|
PCIDevice *d;
|
|
|
|
int devfn;
|
2004-06-22 03:45:35 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
for(devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
|
|
|
|
d = bus->devices[devfn];
|
|
|
|
if (d) {
|
|
|
|
fn(bus, d);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
void pci_for_each_device(PCIBus *bus, int bus_num,
|
|
|
|
void (*fn)(PCIBus *b, PCIDevice *d))
|
|
|
|
{
|
|
|
|
bus = pci_find_bus(bus, bus_num);
|
|
|
|
|
|
|
|
if (bus) {
|
|
|
|
pci_for_each_device_under_bus(bus, fn);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static void pci_device_print(Monitor *mon, QDict *device)
|
|
|
|
{
|
|
|
|
QDict *qdict;
|
|
|
|
QListEntry *entry;
|
|
|
|
uint64_t addr, size;
|
|
|
|
|
|
|
|
monitor_printf(mon, " Bus %2" PRId64 ", ", qdict_get_int(device, "bus"));
|
|
|
|
monitor_printf(mon, "device %3" PRId64 ", function %" PRId64 ":\n",
|
|
|
|
qdict_get_int(device, "slot"),
|
|
|
|
qdict_get_int(device, "function"));
|
2009-03-06 07:01:23 +08:00
|
|
|
monitor_printf(mon, " ");
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
qdict = qdict_get_qdict(device, "class_info");
|
|
|
|
if (qdict_haskey(qdict, "desc")) {
|
|
|
|
monitor_printf(mon, "%s", qdict_get_str(qdict, "desc"));
|
2006-05-21 21:45:09 +08:00
|
|
|
} else {
|
2010-01-22 05:15:40 +08:00
|
|
|
monitor_printf(mon, "Class %04" PRId64, qdict_get_int(qdict, "class"));
|
2005-05-14 07:08:13 +08:00
|
|
|
}
|
2004-06-22 03:45:35 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
qdict = qdict_get_qdict(device, "id");
|
|
|
|
monitor_printf(mon, ": PCI device %04" PRIx64 ":%04" PRIx64 "\n",
|
|
|
|
qdict_get_int(qdict, "device"),
|
|
|
|
qdict_get_int(qdict, "vendor"));
|
|
|
|
|
|
|
|
if (qdict_haskey(device, "irq")) {
|
|
|
|
monitor_printf(mon, " IRQ %" PRId64 ".\n",
|
|
|
|
qdict_get_int(device, "irq"));
|
2004-06-22 03:45:35 +08:00
|
|
|
}
|
2009-10-30 20:21:26 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
if (qdict_haskey(device, "pci_bridge")) {
|
|
|
|
QDict *info;
|
|
|
|
|
|
|
|
qdict = qdict_get_qdict(device, "pci_bridge");
|
|
|
|
|
|
|
|
info = qdict_get_qdict(qdict, "bus");
|
|
|
|
monitor_printf(mon, " BUS %" PRId64 ".\n",
|
|
|
|
qdict_get_int(info, "number"));
|
|
|
|
monitor_printf(mon, " secondary bus %" PRId64 ".\n",
|
|
|
|
qdict_get_int(info, "secondary"));
|
|
|
|
monitor_printf(mon, " subordinate bus %" PRId64 ".\n",
|
|
|
|
qdict_get_int(info, "subordinate"));
|
2009-10-30 20:21:26 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
info = qdict_get_qdict(qdict, "io_range");
|
2009-10-30 20:21:26 +08:00
|
|
|
monitor_printf(mon, " IO range [0x%04"PRIx64", 0x%04"PRIx64"]\n",
|
2010-01-22 05:15:40 +08:00
|
|
|
qdict_get_int(info, "base"),
|
|
|
|
qdict_get_int(info, "limit"));
|
2009-10-30 20:21:26 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
info = qdict_get_qdict(qdict, "memory_range");
|
2009-10-30 20:21:26 +08:00
|
|
|
monitor_printf(mon,
|
|
|
|
" memory range [0x%08"PRIx64", 0x%08"PRIx64"]\n",
|
2010-01-22 05:15:40 +08:00
|
|
|
qdict_get_int(info, "base"),
|
|
|
|
qdict_get_int(info, "limit"));
|
2009-10-30 20:21:26 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
info = qdict_get_qdict(qdict, "prefetchable_range");
|
2009-10-30 20:21:26 +08:00
|
|
|
monitor_printf(mon, " prefetchable memory range "
|
2010-01-22 05:15:40 +08:00
|
|
|
"[0x%08"PRIx64", 0x%08"PRIx64"]\n",
|
|
|
|
qdict_get_int(info, "base"),
|
|
|
|
qdict_get_int(info, "limit"));
|
2006-09-25 01:01:44 +08:00
|
|
|
}
|
2009-10-30 20:21:11 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
QLIST_FOREACH_ENTRY(qdict_get_qlist(device, "regions"), entry) {
|
|
|
|
qdict = qobject_to_qdict(qlist_entry_obj(entry));
|
|
|
|
monitor_printf(mon, " BAR%d: ", (int) qdict_get_int(qdict, "bar"));
|
|
|
|
|
|
|
|
addr = qdict_get_int(qdict, "address");
|
|
|
|
size = qdict_get_int(qdict, "size");
|
|
|
|
|
|
|
|
if (!strcmp(qdict_get_str(qdict, "type"), "io")) {
|
|
|
|
monitor_printf(mon, "I/O at 0x%04"FMT_PCIBUS
|
|
|
|
" [0x%04"FMT_PCIBUS"].\n",
|
|
|
|
addr, addr + size - 1);
|
|
|
|
} else {
|
|
|
|
monitor_printf(mon, "%d bit%s memory at 0x%08"FMT_PCIBUS
|
2009-10-30 20:21:09 +08:00
|
|
|
" [0x%08"FMT_PCIBUS"].\n",
|
2010-01-22 05:15:40 +08:00
|
|
|
qdict_get_bool(qdict, "mem_type_64") ? 64 : 32,
|
|
|
|
qdict_get_bool(qdict, "prefetch") ?
|
|
|
|
" prefetchable" : "", addr, addr + size - 1);
|
2006-05-14 00:11:23 +08:00
|
|
|
}
|
2004-05-27 06:13:53 +08:00
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
monitor_printf(mon, " id \"%s\"\n", qdict_get_str(device, "qdev_id"));
|
|
|
|
|
2010-01-22 05:15:41 +08:00
|
|
|
if (qdict_haskey(device, "pci_bridge")) {
|
|
|
|
qdict = qdict_get_qdict(device, "pci_bridge");
|
|
|
|
if (qdict_haskey(qdict, "devices")) {
|
|
|
|
QListEntry *dev;
|
|
|
|
QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
|
|
|
|
pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
|
|
|
|
}
|
|
|
|
}
|
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
void do_pci_info_print(Monitor *mon, const QObject *data)
|
|
|
|
{
|
|
|
|
QListEntry *bus, *dev;
|
|
|
|
|
|
|
|
QLIST_FOREACH_ENTRY(qobject_to_qlist(data), bus) {
|
|
|
|
QDict *qdict = qobject_to_qdict(qlist_entry_obj(bus));
|
|
|
|
QLIST_FOREACH_ENTRY(qdict_get_qlist(qdict, "devices"), dev) {
|
|
|
|
pci_device_print(mon, qobject_to_qdict(qlist_entry_obj(dev)));
|
|
|
|
}
|
2006-09-25 01:01:44 +08:00
|
|
|
}
|
2005-06-05 23:16:50 +08:00
|
|
|
}
|
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
static QObject *pci_get_dev_class(const PCIDevice *dev)
|
|
|
|
{
|
|
|
|
int class;
|
|
|
|
const pci_class_desc *desc;
|
|
|
|
|
|
|
|
class = pci_get_word(dev->config + PCI_CLASS_DEVICE);
|
|
|
|
desc = pci_class_descriptions;
|
|
|
|
while (desc->desc && class != desc->class)
|
|
|
|
desc++;
|
|
|
|
|
|
|
|
if (desc->desc) {
|
|
|
|
return qobject_from_jsonf("{ 'desc': %s, 'class': %d }",
|
|
|
|
desc->desc, class);
|
|
|
|
} else {
|
|
|
|
return qobject_from_jsonf("{ 'class': %d }", class);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
static QObject *pci_get_dev_id(const PCIDevice *dev)
|
|
|
|
{
|
|
|
|
return qobject_from_jsonf("{ 'device': %d, 'vendor': %d }",
|
|
|
|
pci_get_word(dev->config + PCI_VENDOR_ID),
|
|
|
|
pci_get_word(dev->config + PCI_DEVICE_ID));
|
|
|
|
}
|
|
|
|
|
|
|
|
static QObject *pci_get_regions_list(const PCIDevice *dev)
|
|
|
|
{
|
|
|
|
int i;
|
|
|
|
QList *regions_list;
|
|
|
|
|
|
|
|
regions_list = qlist_new();
|
|
|
|
|
|
|
|
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
|
|
QObject *obj;
|
|
|
|
const PCIIORegion *r = &dev->io_regions[i];
|
|
|
|
|
|
|
|
if (!r->size) {
|
|
|
|
continue;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
|
|
|
|
obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'io', "
|
|
|
|
"'address': %" PRId64 ", "
|
|
|
|
"'size': %" PRId64 " }",
|
|
|
|
i, r->addr, r->size);
|
|
|
|
} else {
|
|
|
|
int mem_type_64 = r->type & PCI_BASE_ADDRESS_MEM_TYPE_64;
|
|
|
|
|
|
|
|
obj = qobject_from_jsonf("{ 'bar': %d, 'type': 'memory', "
|
|
|
|
"'mem_type_64': %i, 'prefetch': %i, "
|
|
|
|
"'address': %" PRId64 ", "
|
|
|
|
"'size': %" PRId64 " }",
|
|
|
|
i, mem_type_64,
|
|
|
|
r->type & PCI_BASE_ADDRESS_MEM_PREFETCH,
|
|
|
|
r->addr, r->size);
|
|
|
|
}
|
|
|
|
|
|
|
|
qlist_append_obj(regions_list, obj);
|
|
|
|
}
|
|
|
|
|
|
|
|
return QOBJECT(regions_list);
|
|
|
|
}
|
|
|
|
|
2010-01-22 05:15:41 +08:00
|
|
|
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num);
|
|
|
|
|
|
|
|
static QObject *pci_get_dev_dict(PCIDevice *dev, PCIBus *bus, int bus_num)
|
2010-01-22 05:15:40 +08:00
|
|
|
{
|
2010-02-08 14:40:38 +08:00
|
|
|
uint8_t type;
|
2010-01-22 05:15:40 +08:00
|
|
|
QObject *obj;
|
|
|
|
|
|
|
|
obj = qobject_from_jsonf("{ 'bus': %d, 'slot': %d, 'function': %d," "'class_info': %p, 'id': %p, 'regions': %p,"
|
|
|
|
" 'qdev_id': %s }",
|
|
|
|
bus_num,
|
|
|
|
PCI_SLOT(dev->devfn), PCI_FUNC(dev->devfn),
|
|
|
|
pci_get_dev_class(dev), pci_get_dev_id(dev),
|
|
|
|
pci_get_regions_list(dev),
|
|
|
|
dev->qdev.id ? dev->qdev.id : "");
|
|
|
|
|
|
|
|
if (dev->config[PCI_INTERRUPT_PIN] != 0) {
|
|
|
|
QDict *qdict = qobject_to_qdict(obj);
|
|
|
|
qdict_put(qdict, "irq", qint_from_int(dev->config[PCI_INTERRUPT_LINE]));
|
|
|
|
}
|
|
|
|
|
2010-02-08 14:40:38 +08:00
|
|
|
type = dev->config[PCI_HEADER_TYPE] & ~PCI_HEADER_TYPE_MULTI_FUNCTION;
|
|
|
|
if (type == PCI_HEADER_TYPE_BRIDGE) {
|
2010-01-22 05:15:40 +08:00
|
|
|
QDict *qdict;
|
|
|
|
QObject *pci_bridge;
|
|
|
|
|
|
|
|
pci_bridge = qobject_from_jsonf("{ 'bus': "
|
|
|
|
"{ 'number': %d, 'secondary': %d, 'subordinate': %d }, "
|
|
|
|
"'io_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
|
|
|
|
"'memory_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "}, "
|
|
|
|
"'prefetchable_range': { 'base': %" PRId64 ", 'limit': %" PRId64 "} }",
|
2010-02-06 17:20:13 +08:00
|
|
|
dev->config[PCI_PRIMARY_BUS], dev->config[PCI_SECONDARY_BUS],
|
2010-01-22 05:15:40 +08:00
|
|
|
dev->config[PCI_SUBORDINATE_BUS],
|
|
|
|
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_IO),
|
|
|
|
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_IO),
|
|
|
|
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
|
|
|
|
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY),
|
|
|
|
pci_bridge_get_base(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
|
|
|
|
PCI_BASE_ADDRESS_MEM_PREFETCH),
|
|
|
|
pci_bridge_get_limit(dev, PCI_BASE_ADDRESS_SPACE_MEMORY |
|
|
|
|
PCI_BASE_ADDRESS_MEM_PREFETCH));
|
|
|
|
|
2010-02-06 17:20:13 +08:00
|
|
|
if (dev->config[PCI_SECONDARY_BUS] != 0) {
|
|
|
|
PCIBus *child_bus = pci_find_bus(bus, dev->config[PCI_SECONDARY_BUS]);
|
2010-01-22 05:15:41 +08:00
|
|
|
|
2010-02-06 17:20:13 +08:00
|
|
|
if (child_bus) {
|
|
|
|
qdict = qobject_to_qdict(pci_bridge);
|
|
|
|
qdict_put_obj(qdict, "devices",
|
|
|
|
pci_get_devices_list(child_bus,
|
|
|
|
dev->config[PCI_SECONDARY_BUS]));
|
|
|
|
}
|
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
qdict = qobject_to_qdict(obj);
|
|
|
|
qdict_put_obj(qdict, "pci_bridge", pci_bridge);
|
|
|
|
}
|
|
|
|
|
|
|
|
return obj;
|
|
|
|
}
|
|
|
|
|
|
|
|
static QObject *pci_get_devices_list(PCIBus *bus, int bus_num)
|
2005-06-05 23:16:50 +08:00
|
|
|
{
|
2006-05-14 00:11:23 +08:00
|
|
|
int devfn;
|
2010-01-22 05:15:40 +08:00
|
|
|
PCIDevice *dev;
|
|
|
|
QList *dev_list;
|
2007-09-17 16:09:54 +08:00
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
dev_list = qlist_new();
|
|
|
|
|
|
|
|
for (devfn = 0; devfn < ARRAY_SIZE(bus->devices); devfn++) {
|
|
|
|
dev = bus->devices[devfn];
|
|
|
|
if (dev) {
|
2010-01-22 05:15:41 +08:00
|
|
|
qlist_append_obj(dev_list, pci_get_dev_dict(dev, bus, bus_num));
|
2010-01-22 05:15:40 +08:00
|
|
|
}
|
2009-10-30 20:21:24 +08:00
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
return QOBJECT(dev_list);
|
2009-10-30 20:21:24 +08:00
|
|
|
}
|
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
static QObject *pci_get_bus_dict(PCIBus *bus, int bus_num)
|
2009-10-30 20:21:24 +08:00
|
|
|
{
|
2009-10-30 20:21:13 +08:00
|
|
|
bus = pci_find_bus(bus, bus_num);
|
2006-05-14 00:11:23 +08:00
|
|
|
if (bus) {
|
2010-01-22 05:15:40 +08:00
|
|
|
return qobject_from_jsonf("{ 'bus': %d, 'devices': %p }",
|
|
|
|
bus_num, pci_get_devices_list(bus, bus_num));
|
2004-06-22 00:52:24 +08:00
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
return NULL;
|
2004-06-22 00:52:24 +08:00
|
|
|
}
|
|
|
|
|
2010-01-22 05:15:40 +08:00
|
|
|
void do_pci_info(Monitor *mon, QObject **ret_data)
|
2004-06-22 00:52:24 +08:00
|
|
|
{
|
2010-01-22 05:15:40 +08:00
|
|
|
QList *bus_list;
|
2009-10-30 20:21:13 +08:00
|
|
|
struct PCIHostBus *host;
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
bus_list = qlist_new();
|
|
|
|
|
2009-10-30 20:21:13 +08:00
|
|
|
QLIST_FOREACH(host, &host_buses, next) {
|
2010-01-22 05:15:40 +08:00
|
|
|
QObject *obj = pci_get_bus_dict(host->bus, 0);
|
|
|
|
if (obj) {
|
|
|
|
qlist_append_obj(bus_list, obj);
|
|
|
|
}
|
2009-10-30 20:21:13 +08:00
|
|
|
}
|
2010-01-22 05:15:40 +08:00
|
|
|
|
|
|
|
*ret_data = QOBJECT(bus_list);
|
2004-05-27 06:13:53 +08:00
|
|
|
}
|
2006-02-05 12:14:41 +08:00
|
|
|
|
2009-01-14 03:47:10 +08:00
|
|
|
static const char * const pci_nic_models[] = {
|
|
|
|
"ne2k_pci",
|
|
|
|
"i82551",
|
|
|
|
"i82557b",
|
|
|
|
"i82559er",
|
|
|
|
"rtl8139",
|
|
|
|
"e1000",
|
|
|
|
"pcnet",
|
|
|
|
"virtio",
|
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
2009-05-15 05:35:07 +08:00
|
|
|
static const char * const pci_nic_names[] = {
|
|
|
|
"ne2k_pci",
|
|
|
|
"i82551",
|
|
|
|
"i82557b",
|
|
|
|
"i82559er",
|
|
|
|
"rtl8139",
|
|
|
|
"e1000",
|
|
|
|
"pcnet",
|
2009-05-18 21:51:59 +08:00
|
|
|
"virtio-net-pci",
|
2009-01-14 03:47:10 +08:00
|
|
|
NULL
|
|
|
|
};
|
|
|
|
|
2006-02-05 12:14:41 +08:00
|
|
|
/* Initialize a PCI NIC. */
|
2009-10-07 07:15:57 +08:00
|
|
|
/* FIXME callers should check for failure, but don't */
|
2009-06-18 21:14:08 +08:00
|
|
|
PCIDevice *pci_nic_init(NICInfo *nd, const char *default_model,
|
|
|
|
const char *default_devaddr)
|
2006-02-05 12:14:41 +08:00
|
|
|
{
|
2009-06-18 21:14:08 +08:00
|
|
|
const char *devaddr = nd->devaddr ? nd->devaddr : default_devaddr;
|
2009-09-25 09:53:51 +08:00
|
|
|
PCIBus *bus;
|
|
|
|
int devfn;
|
2009-06-18 21:14:08 +08:00
|
|
|
PCIDevice *pci_dev;
|
2009-05-15 05:35:07 +08:00
|
|
|
DeviceState *dev;
|
2009-01-14 03:47:10 +08:00
|
|
|
int i;
|
|
|
|
|
2009-09-25 09:53:51 +08:00
|
|
|
i = qemu_find_nic_model(nd, pci_nic_models, default_model);
|
|
|
|
if (i < 0)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
bus = pci_get_bus_devfn(&devfn, devaddr);
|
|
|
|
if (!bus) {
|
2010-02-19 00:25:24 +08:00
|
|
|
error_report("Invalid PCI device address %s for device %s",
|
|
|
|
devaddr, pci_nic_names[i]);
|
2009-09-25 09:53:51 +08:00
|
|
|
return NULL;
|
|
|
|
}
|
|
|
|
|
2009-09-25 09:53:53 +08:00
|
|
|
pci_dev = pci_create(bus, devfn, pci_nic_names[i]);
|
2009-09-25 09:53:50 +08:00
|
|
|
dev = &pci_dev->qdev;
|
2009-10-21 21:25:41 +08:00
|
|
|
qdev_set_nic_properties(dev, nd);
|
2009-09-25 09:53:51 +08:00
|
|
|
if (qdev_init(dev) < 0)
|
|
|
|
return NULL;
|
2009-09-25 09:53:50 +08:00
|
|
|
return pci_dev;
|
2006-02-05 12:14:41 +08:00
|
|
|
}
|
|
|
|
|
2009-09-25 09:53:51 +08:00
|
|
|
PCIDevice *pci_nic_init_nofail(NICInfo *nd, const char *default_model,
|
|
|
|
const char *default_devaddr)
|
|
|
|
{
|
|
|
|
PCIDevice *res;
|
|
|
|
|
|
|
|
if (qemu_show_nic_models(nd->model, pci_nic_models))
|
|
|
|
exit(0);
|
|
|
|
|
|
|
|
res = pci_nic_init(nd, default_model, default_devaddr);
|
|
|
|
if (!res)
|
|
|
|
exit(1);
|
|
|
|
return res;
|
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:25 +08:00
|
|
|
static void pci_bridge_update_mappings_fn(PCIBus *b, PCIDevice *d)
|
|
|
|
{
|
|
|
|
pci_update_mappings(d);
|
|
|
|
}
|
|
|
|
|
2010-07-13 12:01:39 +08:00
|
|
|
void pci_bridge_update_mappings(PCIBus *b)
|
2009-10-30 20:21:25 +08:00
|
|
|
{
|
|
|
|
PCIBus *child;
|
|
|
|
|
|
|
|
pci_for_each_device_under_bus(b, pci_bridge_update_mappings_fn);
|
|
|
|
|
|
|
|
QLIST_FOREACH(child, &b->child, sibling) {
|
|
|
|
pci_bridge_update_mappings(child);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:13 +08:00
|
|
|
PCIBus *pci_find_bus(PCIBus *bus, int bus_num)
|
2009-02-11 23:19:46 +08:00
|
|
|
{
|
2010-04-12 10:58:59 +08:00
|
|
|
PCIBus *sec;
|
2009-02-11 23:19:46 +08:00
|
|
|
|
2010-04-12 10:58:59 +08:00
|
|
|
if (!bus) {
|
2009-10-30 20:21:13 +08:00
|
|
|
return NULL;
|
2010-04-12 10:58:59 +08:00
|
|
|
}
|
2009-02-11 23:19:46 +08:00
|
|
|
|
2009-10-30 20:21:13 +08:00
|
|
|
if (pci_bus_num(bus) == bus_num) {
|
|
|
|
return bus;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* try child bus */
|
2010-04-12 10:58:59 +08:00
|
|
|
if (!bus->parent_dev /* host pci bridge */ ||
|
|
|
|
(bus->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
|
|
|
|
bus_num <= bus->parent_dev->config[PCI_SUBORDINATE_BUS])) {
|
|
|
|
for (; bus; bus = sec) {
|
|
|
|
QLIST_FOREACH(sec, &bus->child, sibling) {
|
|
|
|
assert(sec->parent_dev);
|
|
|
|
if (sec->parent_dev->config[PCI_SECONDARY_BUS] == bus_num) {
|
|
|
|
return sec;
|
|
|
|
}
|
|
|
|
if (sec->parent_dev->config[PCI_SECONDARY_BUS] < bus_num &&
|
|
|
|
bus_num <= sec->parent_dev->config[PCI_SUBORDINATE_BUS]) {
|
|
|
|
break;
|
|
|
|
}
|
2010-02-06 17:20:13 +08:00
|
|
|
}
|
2009-10-30 20:21:13 +08:00
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
return NULL;
|
2009-02-11 23:19:46 +08:00
|
|
|
}
|
|
|
|
|
2009-10-30 20:21:13 +08:00
|
|
|
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function)
|
2009-02-11 23:19:46 +08:00
|
|
|
{
|
2009-10-30 20:21:13 +08:00
|
|
|
bus = pci_find_bus(bus, bus_num);
|
2009-02-11 23:19:46 +08:00
|
|
|
|
|
|
|
if (!bus)
|
|
|
|
return NULL;
|
|
|
|
|
|
|
|
return bus->devices[PCI_DEVFN(slot, function)];
|
|
|
|
}
|
|
|
|
|
2009-08-14 16:36:05 +08:00
|
|
|
static int pci_qdev_init(DeviceState *qdev, DeviceInfo *base)
|
2009-05-15 05:35:07 +08:00
|
|
|
{
|
|
|
|
PCIDevice *pci_dev = (PCIDevice *)qdev;
|
2009-05-23 07:05:19 +08:00
|
|
|
PCIDeviceInfo *info = container_of(base, PCIDeviceInfo, qdev);
|
2009-05-15 05:35:07 +08:00
|
|
|
PCIBus *bus;
|
2009-09-26 03:42:44 +08:00
|
|
|
int devfn, rc;
|
2009-05-15 05:35:07 +08:00
|
|
|
|
2009-10-30 20:21:18 +08:00
|
|
|
/* initialize cap_present for pci_is_express() and pci_config_size() */
|
|
|
|
if (info->is_express) {
|
|
|
|
pci_dev->cap_present |= QEMU_PCI_CAP_EXPRESS;
|
|
|
|
}
|
|
|
|
|
2009-05-23 07:05:19 +08:00
|
|
|
bus = FROM_QBUS(PCIBus, qdev_get_parent_bus(qdev));
|
2009-07-15 19:43:31 +08:00
|
|
|
devfn = pci_dev->devfn;
|
2009-06-30 20:12:11 +08:00
|
|
|
pci_dev = do_pci_register_device(pci_dev, bus, base->name, devfn,
|
2009-10-30 20:21:22 +08:00
|
|
|
info->config_read, info->config_write,
|
2010-06-23 15:15:28 +08:00
|
|
|
info->is_bridge);
|
2009-12-10 18:11:06 +08:00
|
|
|
if (pci_dev == NULL)
|
|
|
|
return -1;
|
2009-09-26 03:42:44 +08:00
|
|
|
rc = info->init(pci_dev);
|
2010-05-11 18:44:21 +08:00
|
|
|
if (rc != 0) {
|
|
|
|
do_pci_unregister_device(pci_dev);
|
2009-09-26 03:42:44 +08:00
|
|
|
return rc;
|
2010-05-11 18:44:21 +08:00
|
|
|
}
|
2009-12-18 19:01:08 +08:00
|
|
|
|
|
|
|
/* rom loading */
|
|
|
|
if (pci_dev->romfile == NULL && info->romfile != NULL)
|
|
|
|
pci_dev->romfile = qemu_strdup(info->romfile);
|
|
|
|
pci_add_option_rom(pci_dev);
|
|
|
|
|
2010-09-06 15:46:18 +08:00
|
|
|
if (bus->hotplug) {
|
|
|
|
/* lower layer must check qdev->hotplugged */
|
2010-06-22 10:55:35 +08:00
|
|
|
rc = bus->hotplug(bus->hotplug_qdev, pci_dev, 1);
|
|
|
|
if (rc != 0) {
|
|
|
|
int r = pci_unregister_device(&pci_dev->qdev);
|
|
|
|
assert(!r);
|
|
|
|
return rc;
|
|
|
|
}
|
|
|
|
}
|
2009-09-26 03:42:44 +08:00
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static int pci_unplug_device(DeviceState *qdev)
|
|
|
|
{
|
|
|
|
PCIDevice *dev = DO_UPCAST(PCIDevice, qdev, qdev);
|
|
|
|
|
2010-06-22 10:55:35 +08:00
|
|
|
return dev->bus->hotplug(dev->bus->hotplug_qdev, dev, 0);
|
2009-05-15 05:35:07 +08:00
|
|
|
}
|
|
|
|
|
2009-06-30 20:12:07 +08:00
|
|
|
void pci_qdev_register(PCIDeviceInfo *info)
|
2009-05-15 05:35:07 +08:00
|
|
|
{
|
2009-05-23 07:05:19 +08:00
|
|
|
info->qdev.init = pci_qdev_init;
|
2009-09-26 03:42:44 +08:00
|
|
|
info->qdev.unplug = pci_unplug_device;
|
2009-09-26 03:42:37 +08:00
|
|
|
info->qdev.exit = pci_unregister_device;
|
2009-06-30 20:12:08 +08:00
|
|
|
info->qdev.bus_info = &pci_bus_info;
|
2009-06-10 15:41:42 +08:00
|
|
|
qdev_register(&info->qdev);
|
2009-05-15 05:35:07 +08:00
|
|
|
}
|
|
|
|
|
2009-06-30 20:12:07 +08:00
|
|
|
void pci_qdev_register_many(PCIDeviceInfo *info)
|
|
|
|
{
|
|
|
|
while (info->qdev.name) {
|
|
|
|
pci_qdev_register(info);
|
|
|
|
info++;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
2010-06-23 15:15:30 +08:00
|
|
|
PCIDevice *pci_create_multifunction(PCIBus *bus, int devfn, bool multifunction,
|
|
|
|
const char *name)
|
2009-05-15 05:35:07 +08:00
|
|
|
{
|
|
|
|
DeviceState *dev;
|
|
|
|
|
2009-05-23 07:05:19 +08:00
|
|
|
dev = qdev_create(&bus->qbus, name);
|
2009-07-15 19:59:23 +08:00
|
|
|
qdev_prop_set_uint32(dev, "addr", devfn);
|
2010-06-23 15:15:30 +08:00
|
|
|
qdev_prop_set_bit(dev, "multifunction", multifunction);
|
2009-09-16 03:23:25 +08:00
|
|
|
return DO_UPCAST(PCIDevice, qdev, dev);
|
|
|
|
}
|
2009-05-15 05:35:07 +08:00
|
|
|
|
2010-06-23 15:15:30 +08:00
|
|
|
PCIDevice *pci_create_simple_multifunction(PCIBus *bus, int devfn,
|
|
|
|
bool multifunction,
|
|
|
|
const char *name)
|
2009-09-16 03:23:25 +08:00
|
|
|
{
|
2010-06-23 15:15:30 +08:00
|
|
|
PCIDevice *dev = pci_create_multifunction(bus, devfn, multifunction, name);
|
2009-10-07 07:15:58 +08:00
|
|
|
qdev_init_nofail(&dev->qdev);
|
2009-09-16 03:23:25 +08:00
|
|
|
return dev;
|
2009-05-15 05:35:07 +08:00
|
|
|
}
|
2009-06-22 00:45:40 +08:00
|
|
|
|
2010-06-23 15:15:30 +08:00
|
|
|
PCIDevice *pci_create(PCIBus *bus, int devfn, const char *name)
|
|
|
|
{
|
|
|
|
return pci_create_multifunction(bus, devfn, false, name);
|
|
|
|
}
|
|
|
|
|
|
|
|
PCIDevice *pci_create_simple(PCIBus *bus, int devfn, const char *name)
|
|
|
|
{
|
|
|
|
return pci_create_simple_multifunction(bus, devfn, false, name);
|
|
|
|
}
|
|
|
|
|
2009-06-22 00:45:40 +08:00
|
|
|
static int pci_find_space(PCIDevice *pdev, uint8_t size)
|
|
|
|
{
|
2009-10-30 20:21:18 +08:00
|
|
|
int config_size = pci_config_size(pdev);
|
2009-06-22 00:45:40 +08:00
|
|
|
int offset = PCI_CONFIG_HEADER_SIZE;
|
|
|
|
int i;
|
2009-10-30 20:21:18 +08:00
|
|
|
for (i = PCI_CONFIG_HEADER_SIZE; i < config_size; ++i)
|
2009-06-22 00:45:40 +08:00
|
|
|
if (pdev->used[i])
|
|
|
|
offset = i + 1;
|
|
|
|
else if (i - offset + 1 == size)
|
|
|
|
return offset;
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
|
|
|
|
uint8_t *prev_p)
|
|
|
|
{
|
|
|
|
uint8_t next, prev;
|
|
|
|
|
|
|
|
if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
|
|
|
|
return 0;
|
|
|
|
|
|
|
|
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
|
|
|
|
prev = next + PCI_CAP_LIST_NEXT)
|
|
|
|
if (pdev->config[next + PCI_CAP_LIST_ID] == cap_id)
|
|
|
|
break;
|
|
|
|
|
|
|
|
if (prev_p)
|
|
|
|
*prev_p = prev;
|
|
|
|
return next;
|
|
|
|
}
|
|
|
|
|
2009-12-18 19:01:07 +08:00
|
|
|
static void pci_map_option_rom(PCIDevice *pdev, int region_num, pcibus_t addr, pcibus_t size, int type)
|
|
|
|
{
|
|
|
|
cpu_register_physical_memory(addr, size, pdev->rom_offset);
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Add an option rom for the device */
|
2009-12-18 19:01:08 +08:00
|
|
|
static int pci_add_option_rom(PCIDevice *pdev)
|
2009-12-18 19:01:07 +08:00
|
|
|
{
|
|
|
|
int size;
|
|
|
|
char *path;
|
|
|
|
void *ptr;
|
2010-06-26 01:09:35 +08:00
|
|
|
char name[32];
|
2009-12-18 19:01:07 +08:00
|
|
|
|
2009-12-18 19:01:08 +08:00
|
|
|
if (!pdev->romfile)
|
|
|
|
return 0;
|
|
|
|
if (strlen(pdev->romfile) == 0)
|
|
|
|
return 0;
|
|
|
|
|
2010-01-08 22:25:41 +08:00
|
|
|
if (!pdev->rom_bar) {
|
|
|
|
/*
|
|
|
|
* Load rom via fw_cfg instead of creating a rom bar,
|
|
|
|
* for 0.11 compatibility.
|
|
|
|
*/
|
|
|
|
int class = pci_get_word(pdev->config + PCI_CLASS_DEVICE);
|
|
|
|
if (class == 0x0300) {
|
|
|
|
rom_add_vga(pdev->romfile);
|
|
|
|
} else {
|
|
|
|
rom_add_option(pdev->romfile);
|
|
|
|
}
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2009-12-18 19:01:08 +08:00
|
|
|
path = qemu_find_file(QEMU_FILE_TYPE_BIOS, pdev->romfile);
|
2009-12-18 19:01:07 +08:00
|
|
|
if (path == NULL) {
|
2009-12-18 19:01:08 +08:00
|
|
|
path = qemu_strdup(pdev->romfile);
|
2009-12-18 19:01:07 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
size = get_image_size(path);
|
2009-12-18 19:01:08 +08:00
|
|
|
if (size < 0) {
|
2010-02-19 00:25:24 +08:00
|
|
|
error_report("%s: failed to find romfile \"%s\"",
|
|
|
|
__FUNCTION__, pdev->romfile);
|
2009-12-18 19:01:08 +08:00
|
|
|
return -1;
|
|
|
|
}
|
2009-12-18 19:01:07 +08:00
|
|
|
if (size & (size - 1)) {
|
|
|
|
size = 1 << qemu_fls(size);
|
|
|
|
}
|
|
|
|
|
2010-06-26 01:09:35 +08:00
|
|
|
if (pdev->qdev.info->vmsd)
|
|
|
|
snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->vmsd->name);
|
|
|
|
else
|
|
|
|
snprintf(name, sizeof(name), "%s.rom", pdev->qdev.info->name);
|
|
|
|
pdev->rom_offset = qemu_ram_alloc(&pdev->qdev, name, size);
|
2009-12-18 19:01:07 +08:00
|
|
|
|
|
|
|
ptr = qemu_get_ram_ptr(pdev->rom_offset);
|
|
|
|
load_image(path, ptr);
|
|
|
|
qemu_free(path);
|
|
|
|
|
|
|
|
pci_register_bar(pdev, PCI_ROM_SLOT, size,
|
|
|
|
0, pci_map_option_rom);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2010-06-26 01:10:19 +08:00
|
|
|
static void pci_del_option_rom(PCIDevice *pdev)
|
|
|
|
{
|
|
|
|
if (!pdev->rom_offset)
|
|
|
|
return;
|
|
|
|
|
|
|
|
qemu_ram_free(pdev->rom_offset);
|
|
|
|
pdev->rom_offset = 0;
|
|
|
|
}
|
|
|
|
|
2010-09-06 15:46:16 +08:00
|
|
|
/*
|
|
|
|
* if !offset
|
|
|
|
* Reserve space and add capability to the linked list in pci config space
|
|
|
|
*
|
|
|
|
* if offset = 0,
|
|
|
|
* Find and reserve space and add capability to the linked list
|
|
|
|
* in pci config space */
|
|
|
|
int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
|
|
|
|
uint8_t offset, uint8_t size)
|
2009-06-22 00:45:40 +08:00
|
|
|
{
|
2010-09-06 15:46:16 +08:00
|
|
|
uint8_t *config;
|
|
|
|
if (!offset) {
|
|
|
|
offset = pci_find_space(pdev, size);
|
|
|
|
if (!offset) {
|
|
|
|
return -ENOSPC;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
config = pdev->config + offset;
|
2009-06-22 00:45:40 +08:00
|
|
|
config[PCI_CAP_LIST_ID] = cap_id;
|
|
|
|
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
|
|
|
|
pdev->config[PCI_CAPABILITY_LIST] = offset;
|
|
|
|
pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
|
|
|
|
memset(pdev->used + offset, 0xFF, size);
|
|
|
|
/* Make capability read-only by default */
|
|
|
|
memset(pdev->wmask + offset, 0, size);
|
2009-06-22 00:49:40 +08:00
|
|
|
/* Check capability by default */
|
|
|
|
memset(pdev->cmask + offset, 0xFF, size);
|
2009-06-22 00:45:40 +08:00
|
|
|
return offset;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Unlink capability from the pci config space. */
|
|
|
|
void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
|
|
|
|
{
|
|
|
|
uint8_t prev, offset = pci_find_capability_list(pdev, cap_id, &prev);
|
|
|
|
if (!offset)
|
|
|
|
return;
|
|
|
|
pdev->config[prev] = pdev->config[offset + PCI_CAP_LIST_NEXT];
|
|
|
|
/* Make capability writeable again */
|
|
|
|
memset(pdev->wmask + offset, 0xff, size);
|
2009-06-22 00:49:40 +08:00
|
|
|
/* Clear cmask as device-specific registers can't be checked */
|
|
|
|
memset(pdev->cmask + offset, 0, size);
|
2009-06-22 00:45:40 +08:00
|
|
|
memset(pdev->used + offset, 0, size);
|
|
|
|
|
|
|
|
if (!pdev->config[PCI_CAPABILITY_LIST])
|
|
|
|
pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* Reserve space for capability at a known offset (to call after load). */
|
|
|
|
void pci_reserve_capability(PCIDevice *pdev, uint8_t offset, uint8_t size)
|
|
|
|
{
|
|
|
|
memset(pdev->used + offset, 0xff, size);
|
|
|
|
}
|
|
|
|
|
|
|
|
uint8_t pci_find_capability(PCIDevice *pdev, uint8_t cap_id)
|
|
|
|
{
|
|
|
|
return pci_find_capability_list(pdev, cap_id, NULL);
|
|
|
|
}
|
2009-06-30 20:12:08 +08:00
|
|
|
|
|
|
|
static void pcibus_dev_print(Monitor *mon, DeviceState *dev, int indent)
|
|
|
|
{
|
|
|
|
PCIDevice *d = (PCIDevice *)dev;
|
|
|
|
const pci_class_desc *desc;
|
|
|
|
char ctxt[64];
|
|
|
|
PCIIORegion *r;
|
|
|
|
int i, class;
|
|
|
|
|
2009-10-30 20:21:00 +08:00
|
|
|
class = pci_get_word(d->config + PCI_CLASS_DEVICE);
|
2009-06-30 20:12:08 +08:00
|
|
|
desc = pci_class_descriptions;
|
|
|
|
while (desc->desc && class != desc->class)
|
|
|
|
desc++;
|
|
|
|
if (desc->desc) {
|
|
|
|
snprintf(ctxt, sizeof(ctxt), "%s", desc->desc);
|
|
|
|
} else {
|
|
|
|
snprintf(ctxt, sizeof(ctxt), "Class %04x", class);
|
|
|
|
}
|
|
|
|
|
|
|
|
monitor_printf(mon, "%*sclass %s, addr %02x:%02x.%x, "
|
|
|
|
"pci id %04x:%04x (sub %04x:%04x)\n",
|
|
|
|
indent, "", ctxt,
|
2009-10-30 20:21:13 +08:00
|
|
|
d->config[PCI_SECONDARY_BUS],
|
|
|
|
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn),
|
2009-10-30 20:21:00 +08:00
|
|
|
pci_get_word(d->config + PCI_VENDOR_ID),
|
|
|
|
pci_get_word(d->config + PCI_DEVICE_ID),
|
|
|
|
pci_get_word(d->config + PCI_SUBSYSTEM_VENDOR_ID),
|
|
|
|
pci_get_word(d->config + PCI_SUBSYSTEM_ID));
|
2009-06-30 20:12:08 +08:00
|
|
|
for (i = 0; i < PCI_NUM_REGIONS; i++) {
|
|
|
|
r = &d->io_regions[i];
|
|
|
|
if (!r->size)
|
|
|
|
continue;
|
2009-10-30 20:21:09 +08:00
|
|
|
monitor_printf(mon, "%*sbar %d: %s at 0x%"FMT_PCIBUS
|
|
|
|
" [0x%"FMT_PCIBUS"]\n",
|
|
|
|
indent, "",
|
2009-10-30 20:21:03 +08:00
|
|
|
i, r->type & PCI_BASE_ADDRESS_SPACE_IO ? "i/o" : "mem",
|
2009-06-30 20:12:08 +08:00
|
|
|
r->addr, r->addr + r->size - 1);
|
|
|
|
}
|
|
|
|
}
|
2009-09-17 04:25:32 +08:00
|
|
|
|
2010-06-26 01:08:59 +08:00
|
|
|
static char *pcibus_get_dev_path(DeviceState *dev)
|
|
|
|
{
|
|
|
|
PCIDevice *d = (PCIDevice *)dev;
|
|
|
|
char path[16];
|
|
|
|
|
|
|
|
snprintf(path, sizeof(path), "%04x:%02x:%02x.%x",
|
|
|
|
pci_find_domain(d->bus), d->config[PCI_SECONDARY_BUS],
|
|
|
|
PCI_SLOT(d->devfn), PCI_FUNC(d->devfn));
|
|
|
|
|
|
|
|
return strdup(path);
|
|
|
|
}
|
|
|
|
|