2009-12-05 19:44:21 +08:00
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/*
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* S/390 virtual CPU header
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*
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* Copyright (c) 2009 Ulrich Hecht
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*
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* This library is free software; you can redistribute it and/or
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* modify it under the terms of the GNU Lesser General Public
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* License as published by the Free Software Foundation; either
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* version 2 of the License, or (at your option) any later version.
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*
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* This library is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU
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* Lesser General Public License for more details.
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*
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2012-11-12 09:44:10 +08:00
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* Contributions after 2012-10-29 are licensed under the terms of the
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* GNU GPL, version 2 or (at your option) any later version.
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*
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* You should have received a copy of the GNU (Lesser) General Public
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2010-03-07 23:48:43 +08:00
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* License along with this library; if not, see <http://www.gnu.org/licenses/>.
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2009-12-05 19:44:21 +08:00
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*/
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2016-06-29 17:05:55 +08:00
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#ifndef S390X_CPU_H
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#define S390X_CPU_H
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2012-02-02 03:56:52 +08:00
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#include "qemu-common.h"
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2016-03-15 20:49:25 +08:00
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#include "cpu-qom.h"
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2017-09-13 21:24:02 +08:00
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#include "cpu_models.h"
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2009-12-05 19:44:21 +08:00
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#define TARGET_LONG_BITS 64
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2014-02-18 14:11:37 +08:00
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#define ELF_MACHINE_UNAME "S390X"
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2009-12-05 19:44:21 +08:00
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2012-03-14 08:38:32 +08:00
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#define CPUArchState struct CPUS390XState
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2009-12-05 19:44:21 +08:00
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2012-12-18 01:19:49 +08:00
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#include "exec/cpu-defs.h"
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2011-04-15 23:32:47 +08:00
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#define TARGET_PAGE_BITS 12
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2013-05-27 19:18:06 +08:00
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#define TARGET_PHYS_ADDR_SPACE_BITS 64
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2011-04-15 23:32:47 +08:00
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#define TARGET_VIRT_ADDR_SPACE_BITS 64
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2012-12-18 01:19:49 +08:00
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#include "exec/cpu-all.h"
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2009-12-05 19:44:21 +08:00
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2012-10-24 19:12:00 +08:00
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#include "fpu/softfloat.h"
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2009-12-05 19:44:21 +08:00
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2017-09-27 02:33:14 +08:00
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#define NB_MMU_MODES 4
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2015-08-31 00:26:10 +08:00
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#define TARGET_INSN_START_EXTRA_WORDS 1
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2009-12-05 19:44:21 +08:00
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2011-04-15 23:32:47 +08:00
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#define MMU_MODE0_SUFFIX _primary
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#define MMU_MODE1_SUFFIX _secondary
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#define MMU_MODE2_SUFFIX _home
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2017-09-27 02:33:14 +08:00
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#define MMU_MODE3_SUFFIX _real
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2011-04-15 23:32:47 +08:00
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2015-05-25 07:47:23 +08:00
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#define MMU_USER_IDX 0
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2011-04-15 23:32:47 +08:00
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2013-01-24 10:28:04 +08:00
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#define MAX_IO_QUEUE 16
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#define MAX_MCHK_QUEUE 16
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#define PSW_MCHK_MASK 0x0004000000000000
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#define PSW_IO_MASK 0x0200000000000000
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2011-04-15 23:32:47 +08:00
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2017-09-28 21:46:09 +08:00
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#define S390_MAX_CPUS 248
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2011-04-15 23:32:47 +08:00
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typedef struct PSW {
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uint64_t mask;
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uint64_t addr;
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} PSW;
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2013-01-24 10:28:04 +08:00
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typedef struct IOIntQueue {
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uint16_t id;
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uint16_t nr;
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uint32_t parm;
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uint32_t word;
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} IOIntQueue;
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typedef struct MchkQueue {
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uint16_t type;
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} MchkQueue;
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2017-09-13 21:24:02 +08:00
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struct CPUS390XState {
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2012-09-26 06:26:59 +08:00
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uint64_t regs[16]; /* GP registers */
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2014-08-19 03:33:39 +08:00
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/*
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* The floating point registers are part of the vector registers.
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* vregs[0][0] -> vregs[15][0] are 16 floating point registers
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*/
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CPU_DoubleU vregs[32][2]; /* vector registers */
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2012-09-26 06:26:59 +08:00
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uint32_t aregs[16]; /* access registers */
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2017-05-12 19:47:30 +08:00
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uint8_t riccb[64]; /* runtime instrumentation control */
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2017-02-15 11:47:49 +08:00
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uint64_t gscb[4]; /* guarded storage control */
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2017-05-12 19:47:30 +08:00
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/* Fields up to this point are not cleared by initial CPU reset */
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struct {} start_initial_reset_fields;
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2009-12-05 19:44:21 +08:00
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2012-09-26 06:26:59 +08:00
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uint32_t fpc; /* floating-point control register */
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uint32_t cc_op;
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2009-12-05 19:44:21 +08:00
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float_status fpu_status; /* passed to softfloat lib */
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2012-09-26 06:26:59 +08:00
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/* The low part of a 128-bit return, or remainder of a divide. */
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uint64_t retxl;
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2011-04-15 23:32:47 +08:00
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PSW psw;
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2009-12-05 19:44:21 +08:00
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2011-04-15 23:32:47 +08:00
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uint64_t cc_src;
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uint64_t cc_dst;
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uint64_t cc_vr;
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2009-12-05 19:44:21 +08:00
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2017-05-22 00:50:00 +08:00
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uint64_t ex_value;
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2009-12-05 19:44:21 +08:00
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uint64_t __excp_addr;
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2011-04-15 23:32:47 +08:00
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uint64_t psa;
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uint32_t int_pgm_code;
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2012-09-15 10:31:57 +08:00
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uint32_t int_pgm_ilen;
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2011-04-15 23:32:47 +08:00
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uint32_t int_svc_code;
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2012-09-15 10:31:57 +08:00
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uint32_t int_svc_ilen;
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2011-04-15 23:32:47 +08:00
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2015-06-13 06:45:56 +08:00
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uint64_t per_address;
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uint16_t per_perc_atmid;
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2011-04-15 23:32:47 +08:00
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uint64_t cregs[16]; /* control registers */
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2013-01-24 10:28:04 +08:00
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IOIntQueue io_queue[MAX_IO_QUEUE][8];
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MchkQueue mchk_queue[MAX_MCHK_QUEUE];
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2011-04-15 23:32:47 +08:00
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2013-01-24 10:28:04 +08:00
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int pending_int;
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2017-09-29 04:36:40 +08:00
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uint32_t service_param;
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2017-09-29 04:36:41 +08:00
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uint16_t external_call_addr;
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DECLARE_BITMAP(emergency_signals, S390_MAX_CPUS);
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2013-01-24 10:28:04 +08:00
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int io_index[8];
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int mchk_index;
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uint64_t ckc;
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uint64_t cputm;
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uint32_t todpr;
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2011-05-02 16:11:40 +08:00
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2013-09-05 19:54:39 +08:00
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uint64_t pfault_token;
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uint64_t pfault_compare;
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uint64_t pfault_select;
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2014-04-03 17:01:13 +08:00
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uint64_t gbea;
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uint64_t pp;
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2016-11-14 22:19:17 +08:00
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/* Fields up to this point are cleared by a CPU reset */
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struct {} end_reset_fields;
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2011-05-02 16:11:40 +08:00
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2016-11-14 22:19:17 +08:00
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CPU_COMMON
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2011-04-15 23:32:47 +08:00
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2017-09-28 21:46:08 +08:00
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#if !defined(CONFIG_USER_ONLY)
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2017-09-13 21:24:08 +08:00
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uint32_t core_id; /* PoP "CPU address", same as cpu_index */
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2017-06-09 21:34:26 +08:00
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uint64_t cpuid;
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2017-09-28 21:46:08 +08:00
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#endif
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2013-09-21 02:33:41 +08:00
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2011-04-15 23:32:47 +08:00
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uint64_t tod_offset;
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uint64_t tod_basetime;
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QEMUTimer *tod_timer;
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QEMUTimer *cpu_timer;
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2014-09-30 16:57:28 +08:00
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/*
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* The cpu state represents the logical state of a cpu. In contrast to other
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* architectures, there is a difference between a halt and a stop on s390.
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* If all cpus are either stopped (including check stop) or in the disabled
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* wait state, the vm can be shut down.
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*/
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#define CPU_STATE_UNINITIALIZED 0x00
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#define CPU_STATE_STOPPED 0x01
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#define CPU_STATE_CHECK_STOP 0x02
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#define CPU_STATE_OPERATING 0x03
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#define CPU_STATE_LOAD 0x04
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uint8_t cpu_state;
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2015-02-24 21:15:27 +08:00
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/* currently processed sigp order */
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uint8_t sigp_order;
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2017-09-13 21:24:02 +08:00
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};
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2009-12-05 19:44:21 +08:00
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2015-05-08 02:35:44 +08:00
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static inline CPU_DoubleU *get_freg(CPUS390XState *cs, int nr)
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{
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2014-08-19 03:33:39 +08:00
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return &cs->vregs[nr][0];
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2015-05-08 02:35:44 +08:00
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}
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2016-03-15 20:49:25 +08:00
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/**
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* S390CPU:
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* @env: #CPUS390XState.
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*
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* An S/390 CPU.
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*/
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struct S390CPU {
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/*< private >*/
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CPUState parent_obj;
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/*< public >*/
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CPUS390XState env;
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2016-09-05 16:52:23 +08:00
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S390CPUModel *model;
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2016-03-15 20:49:25 +08:00
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/* needed for live migration */
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void *irqstate;
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uint32_t irqstate_saved_size;
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};
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static inline S390CPU *s390_env_get_cpu(CPUS390XState *env)
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{
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return container_of(env, S390CPU, env);
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}
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#define ENV_GET_CPU(e) CPU(s390_env_get_cpu(e))
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#define ENV_OFFSET offsetof(S390CPU, env)
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#ifndef CONFIG_USER_ONLY
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extern const struct VMStateDescription vmstate_s390_cpu;
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#endif
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2013-01-24 10:28:05 +08:00
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/* distinguish between 24 bit and 31 bit addressing */
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#define HIGH_ORDER_BIT 0x80000000
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2011-04-15 23:32:47 +08:00
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/* Interrupt Codes */
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/* Program Interrupts */
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#define PGM_OPERATION 0x0001
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#define PGM_PRIVILEGED 0x0002
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#define PGM_EXECUTE 0x0003
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#define PGM_PROTECTION 0x0004
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#define PGM_ADDRESSING 0x0005
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#define PGM_SPECIFICATION 0x0006
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#define PGM_DATA 0x0007
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#define PGM_FIXPT_OVERFLOW 0x0008
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#define PGM_FIXPT_DIVIDE 0x0009
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#define PGM_DEC_OVERFLOW 0x000a
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#define PGM_DEC_DIVIDE 0x000b
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#define PGM_HFP_EXP_OVERFLOW 0x000c
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#define PGM_HFP_EXP_UNDERFLOW 0x000d
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#define PGM_HFP_SIGNIFICANCE 0x000e
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#define PGM_HFP_DIVIDE 0x000f
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#define PGM_SEGMENT_TRANS 0x0010
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#define PGM_PAGE_TRANS 0x0011
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#define PGM_TRANS_SPEC 0x0012
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#define PGM_SPECIAL_OP 0x0013
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#define PGM_OPERAND 0x0015
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#define PGM_TRACE_TABLE 0x0016
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#define PGM_SPACE_SWITCH 0x001c
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#define PGM_HFP_SQRT 0x001d
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#define PGM_PC_TRANS_SPEC 0x001f
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#define PGM_AFX_TRANS 0x0020
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#define PGM_ASX_TRANS 0x0021
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#define PGM_LX_TRANS 0x0022
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#define PGM_EX_TRANS 0x0023
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#define PGM_PRIM_AUTH 0x0024
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#define PGM_SEC_AUTH 0x0025
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#define PGM_ALET_SPEC 0x0028
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#define PGM_ALEN_SPEC 0x0029
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#define PGM_ALE_SEQ 0x002a
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#define PGM_ASTE_VALID 0x002b
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#define PGM_ASTE_SEQ 0x002c
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#define PGM_EXT_AUTH 0x002d
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#define PGM_STACK_FULL 0x0030
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#define PGM_STACK_EMPTY 0x0031
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#define PGM_STACK_SPEC 0x0032
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#define PGM_STACK_TYPE 0x0033
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#define PGM_STACK_OP 0x0034
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#define PGM_ASCE_TYPE 0x0038
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#define PGM_REG_FIRST_TRANS 0x0039
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#define PGM_REG_SEC_TRANS 0x003a
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#define PGM_REG_THIRD_TRANS 0x003b
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#define PGM_MONITOR 0x0040
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#define PGM_PER 0x0080
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#define PGM_CRYPTO 0x0119
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/* External Interrupts */
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#define EXT_INTERRUPT_KEY 0x0040
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#define EXT_CLOCK_COMP 0x1004
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#define EXT_CPU_TIMER 0x1005
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#define EXT_MALFUNCTION 0x1200
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#define EXT_EMERGENCY 0x1201
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#define EXT_EXTERNAL_CALL 0x1202
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#define EXT_ETR 0x1406
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#define EXT_SERVICE 0x2401
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#define EXT_VIRTIO 0x2603
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/* PSW defines */
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#undef PSW_MASK_PER
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#undef PSW_MASK_DAT
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#undef PSW_MASK_IO
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#undef PSW_MASK_EXT
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#undef PSW_MASK_KEY
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#undef PSW_SHIFT_KEY
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#undef PSW_MASK_MCHECK
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#undef PSW_MASK_WAIT
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#undef PSW_MASK_PSTATE
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#undef PSW_MASK_ASC
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2017-06-14 21:38:19 +08:00
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#undef PSW_SHIFT_ASC
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2011-04-15 23:32:47 +08:00
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#undef PSW_MASK_CC
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#undef PSW_MASK_PM
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2017-09-20 23:30:14 +08:00
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#undef PSW_SHIFT_MASK_PM
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2011-04-15 23:32:47 +08:00
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#undef PSW_MASK_64
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2013-07-25 22:45:51 +08:00
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#undef PSW_MASK_32
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#undef PSW_MASK_ESA_ADDR
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2011-04-15 23:32:47 +08:00
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#define PSW_MASK_PER 0x4000000000000000ULL
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#define PSW_MASK_DAT 0x0400000000000000ULL
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#define PSW_MASK_IO 0x0200000000000000ULL
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#define PSW_MASK_EXT 0x0100000000000000ULL
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#define PSW_MASK_KEY 0x00F0000000000000ULL
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2017-06-14 21:38:18 +08:00
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#define PSW_SHIFT_KEY 52
|
2011-04-15 23:32:47 +08:00
|
|
|
#define PSW_MASK_MCHECK 0x0004000000000000ULL
|
|
|
|
#define PSW_MASK_WAIT 0x0002000000000000ULL
|
|
|
|
#define PSW_MASK_PSTATE 0x0001000000000000ULL
|
|
|
|
#define PSW_MASK_ASC 0x0000C00000000000ULL
|
2017-06-14 21:38:19 +08:00
|
|
|
#define PSW_SHIFT_ASC 46
|
2011-04-15 23:32:47 +08:00
|
|
|
#define PSW_MASK_CC 0x0000300000000000ULL
|
|
|
|
#define PSW_MASK_PM 0x00000F0000000000ULL
|
2017-09-20 23:30:14 +08:00
|
|
|
#define PSW_SHIFT_MASK_PM 40
|
2011-04-15 23:32:47 +08:00
|
|
|
#define PSW_MASK_64 0x0000000100000000ULL
|
|
|
|
#define PSW_MASK_32 0x0000000080000000ULL
|
2013-07-25 22:45:51 +08:00
|
|
|
#define PSW_MASK_ESA_ADDR 0x000000007fffffffULL
|
2011-04-15 23:32:47 +08:00
|
|
|
|
|
|
|
#undef PSW_ASC_PRIMARY
|
|
|
|
#undef PSW_ASC_ACCREG
|
|
|
|
#undef PSW_ASC_SECONDARY
|
|
|
|
#undef PSW_ASC_HOME
|
|
|
|
|
|
|
|
#define PSW_ASC_PRIMARY 0x0000000000000000ULL
|
|
|
|
#define PSW_ASC_ACCREG 0x0000400000000000ULL
|
|
|
|
#define PSW_ASC_SECONDARY 0x0000800000000000ULL
|
|
|
|
#define PSW_ASC_HOME 0x0000C00000000000ULL
|
|
|
|
|
2017-06-14 21:38:19 +08:00
|
|
|
/* the address space values shifted */
|
|
|
|
#define AS_PRIMARY 0
|
|
|
|
#define AS_ACCREG 1
|
|
|
|
#define AS_SECONDARY 2
|
|
|
|
#define AS_HOME 3
|
|
|
|
|
2011-04-15 23:32:47 +08:00
|
|
|
/* tb flags */
|
|
|
|
|
2017-06-19 12:11:48 +08:00
|
|
|
#define FLAG_MASK_PSW_SHIFT 31
|
|
|
|
#define FLAG_MASK_PER (PSW_MASK_PER >> FLAG_MASK_PSW_SHIFT)
|
|
|
|
#define FLAG_MASK_PSTATE (PSW_MASK_PSTATE >> FLAG_MASK_PSW_SHIFT)
|
|
|
|
#define FLAG_MASK_ASC (PSW_MASK_ASC >> FLAG_MASK_PSW_SHIFT)
|
|
|
|
#define FLAG_MASK_64 (PSW_MASK_64 >> FLAG_MASK_PSW_SHIFT)
|
|
|
|
#define FLAG_MASK_32 (PSW_MASK_32 >> FLAG_MASK_PSW_SHIFT)
|
|
|
|
#define FLAG_MASK_PSW (FLAG_MASK_PER | FLAG_MASK_PSTATE \
|
|
|
|
| FLAG_MASK_ASC | FLAG_MASK_64 | FLAG_MASK_32)
|
2011-04-15 23:32:47 +08:00
|
|
|
|
2014-04-25 21:37:19 +08:00
|
|
|
/* Control register 0 bits */
|
2015-02-13 01:09:31 +08:00
|
|
|
#define CR0_LOWPROT 0x0000000010000000ULL
|
2017-06-14 21:38:19 +08:00
|
|
|
#define CR0_SECONDARY 0x0000000004000000ULL
|
2014-04-25 21:37:19 +08:00
|
|
|
#define CR0_EDAT 0x0000000000800000ULL
|
2017-09-29 04:36:43 +08:00
|
|
|
#define CR0_EMERGENCY_SIGNAL_SC 0x0000000000004000ULL
|
|
|
|
#define CR0_EXTERNAL_CALL_SC 0x0000000000002000ULL
|
|
|
|
#define CR0_CKC_SC 0x0000000000000800ULL
|
|
|
|
#define CR0_CPU_TIMER_SC 0x0000000000000400ULL
|
|
|
|
#define CR0_SERVICE_SC 0x0000000000000200ULL
|
2014-04-25 21:37:19 +08:00
|
|
|
|
2015-06-04 05:09:53 +08:00
|
|
|
/* MMU */
|
|
|
|
#define MMU_PRIMARY_IDX 0
|
|
|
|
#define MMU_SECONDARY_IDX 1
|
|
|
|
#define MMU_HOME_IDX 2
|
2017-09-27 02:33:14 +08:00
|
|
|
#define MMU_REAL_IDX 3
|
2015-06-04 05:09:53 +08:00
|
|
|
|
2017-06-14 21:38:19 +08:00
|
|
|
static inline int cpu_mmu_index(CPUS390XState *env, bool ifetch)
|
2009-12-05 19:44:26 +08:00
|
|
|
{
|
2015-05-25 07:47:23 +08:00
|
|
|
switch (env->psw.mask & PSW_MASK_ASC) {
|
|
|
|
case PSW_ASC_PRIMARY:
|
2015-06-04 05:09:53 +08:00
|
|
|
return MMU_PRIMARY_IDX;
|
2015-05-25 07:47:23 +08:00
|
|
|
case PSW_ASC_SECONDARY:
|
2015-06-04 05:09:53 +08:00
|
|
|
return MMU_SECONDARY_IDX;
|
2015-05-25 07:47:23 +08:00
|
|
|
case PSW_ASC_HOME:
|
2015-06-04 05:09:53 +08:00
|
|
|
return MMU_HOME_IDX;
|
2015-05-25 07:47:23 +08:00
|
|
|
case PSW_ASC_ACCREG:
|
|
|
|
/* Fallthrough: access register mode is not yet supported */
|
|
|
|
default:
|
|
|
|
abort();
|
2011-04-15 23:32:47 +08:00
|
|
|
}
|
2009-12-05 19:44:26 +08:00
|
|
|
}
|
|
|
|
|
2012-03-14 08:38:22 +08:00
|
|
|
static inline void cpu_get_tb_cpu_state(CPUS390XState* env, target_ulong *pc,
|
2016-04-08 01:19:22 +08:00
|
|
|
target_ulong *cs_base, uint32_t *flags)
|
2011-04-15 23:32:47 +08:00
|
|
|
{
|
|
|
|
*pc = env->psw.addr;
|
2017-05-22 00:50:00 +08:00
|
|
|
*cs_base = env->ex_value;
|
2017-06-19 12:11:48 +08:00
|
|
|
*flags = (env->psw.mask >> FLAG_MASK_PSW_SHIFT) & FLAG_MASK_PSW;
|
2011-04-15 23:32:47 +08:00
|
|
|
}
|
|
|
|
|
2015-06-13 06:45:53 +08:00
|
|
|
/* PER bits from control register 9 */
|
|
|
|
#define PER_CR9_EVENT_BRANCH 0x80000000
|
|
|
|
#define PER_CR9_EVENT_IFETCH 0x40000000
|
|
|
|
#define PER_CR9_EVENT_STORE 0x20000000
|
|
|
|
#define PER_CR9_EVENT_STORE_REAL 0x08000000
|
|
|
|
#define PER_CR9_EVENT_NULLIFICATION 0x01000000
|
|
|
|
#define PER_CR9_CONTROL_BRANCH_ADDRESS 0x00800000
|
|
|
|
#define PER_CR9_CONTROL_ALTERATION 0x00200000
|
|
|
|
|
|
|
|
/* PER bits from the PER CODE/ATMID/AI in lowcore */
|
|
|
|
#define PER_CODE_EVENT_BRANCH 0x8000
|
|
|
|
#define PER_CODE_EVENT_IFETCH 0x4000
|
|
|
|
#define PER_CODE_EVENT_STORE 0x2000
|
|
|
|
#define PER_CODE_EVENT_STORE_REAL 0x0800
|
|
|
|
#define PER_CODE_EVENT_NULLIFICATION 0x0100
|
|
|
|
|
2011-04-15 23:32:47 +08:00
|
|
|
#define EXCP_EXT 1 /* external interrupt */
|
|
|
|
#define EXCP_SVC 2 /* supervisor call (syscall) */
|
|
|
|
#define EXCP_PGM 3 /* program interruption */
|
2013-01-24 10:28:04 +08:00
|
|
|
#define EXCP_IO 7 /* I/O interrupt */
|
|
|
|
#define EXCP_MCHK 8 /* machine check */
|
2011-04-15 23:32:47 +08:00
|
|
|
|
2017-09-29 04:36:39 +08:00
|
|
|
#define INTERRUPT_IO (1 << 0)
|
|
|
|
#define INTERRUPT_MCHK (1 << 1)
|
|
|
|
#define INTERRUPT_EXT_SERVICE (1 << 2)
|
|
|
|
#define INTERRUPT_EXT_CPU_TIMER (1 << 3)
|
|
|
|
#define INTERRUPT_EXT_CLOCK_COMPARATOR (1 << 4)
|
2017-09-29 04:36:41 +08:00
|
|
|
#define INTERRUPT_EXTERNAL_CALL (1 << 5)
|
|
|
|
#define INTERRUPT_EMERGENCY_SIGNAL (1 << 6)
|
2009-12-05 19:44:26 +08:00
|
|
|
|
|
|
|
/* Program Status Word. */
|
|
|
|
#define S390_PSWM_REGNUM 0
|
|
|
|
#define S390_PSWA_REGNUM 1
|
|
|
|
/* General Purpose Registers. */
|
|
|
|
#define S390_R0_REGNUM 2
|
|
|
|
#define S390_R1_REGNUM 3
|
|
|
|
#define S390_R2_REGNUM 4
|
|
|
|
#define S390_R3_REGNUM 5
|
|
|
|
#define S390_R4_REGNUM 6
|
|
|
|
#define S390_R5_REGNUM 7
|
|
|
|
#define S390_R6_REGNUM 8
|
|
|
|
#define S390_R7_REGNUM 9
|
|
|
|
#define S390_R8_REGNUM 10
|
|
|
|
#define S390_R9_REGNUM 11
|
|
|
|
#define S390_R10_REGNUM 12
|
|
|
|
#define S390_R11_REGNUM 13
|
|
|
|
#define S390_R12_REGNUM 14
|
|
|
|
#define S390_R13_REGNUM 15
|
|
|
|
#define S390_R14_REGNUM 16
|
|
|
|
#define S390_R15_REGNUM 17
|
2014-08-29 21:52:16 +08:00
|
|
|
/* Total Core Registers. */
|
|
|
|
#define S390_NUM_CORE_REGS 18
|
2009-12-05 19:44:26 +08:00
|
|
|
|
2013-07-02 19:43:38 +08:00
|
|
|
static inline void setcc(S390CPU *cpu, uint64_t cc)
|
|
|
|
{
|
|
|
|
CPUS390XState *env = &cpu->env;
|
|
|
|
|
|
|
|
env->psw.mask &= ~(3ull << 44);
|
|
|
|
env->psw.mask |= (cc & 3) << 44;
|
2015-06-15 23:57:03 +08:00
|
|
|
env->cc_op = cc;
|
2013-07-02 19:43:38 +08:00
|
|
|
}
|
|
|
|
|
2011-04-15 23:32:47 +08:00
|
|
|
/* STSI */
|
|
|
|
#define STSI_LEVEL_MASK 0x00000000f0000000ULL
|
|
|
|
#define STSI_LEVEL_CURRENT 0x0000000000000000ULL
|
|
|
|
#define STSI_LEVEL_1 0x0000000010000000ULL
|
|
|
|
#define STSI_LEVEL_2 0x0000000020000000ULL
|
|
|
|
#define STSI_LEVEL_3 0x0000000030000000ULL
|
|
|
|
#define STSI_R0_RESERVED_MASK 0x000000000fffff00ULL
|
|
|
|
#define STSI_R0_SEL1_MASK 0x00000000000000ffULL
|
|
|
|
#define STSI_R1_RESERVED_MASK 0x00000000ffff0000ULL
|
|
|
|
#define STSI_R1_SEL2_MASK 0x000000000000ffffULL
|
|
|
|
|
|
|
|
/* Basic Machine Configuration */
|
|
|
|
struct sysib_111 {
|
|
|
|
uint32_t res1[8];
|
|
|
|
uint8_t manuf[16];
|
|
|
|
uint8_t type[4];
|
|
|
|
uint8_t res2[12];
|
|
|
|
uint8_t model[16];
|
|
|
|
uint8_t sequence[16];
|
|
|
|
uint8_t plant[4];
|
|
|
|
uint8_t res3[156];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Basic Machine CPU */
|
|
|
|
struct sysib_121 {
|
|
|
|
uint32_t res1[80];
|
|
|
|
uint8_t sequence[16];
|
|
|
|
uint8_t plant[4];
|
|
|
|
uint8_t res2[2];
|
|
|
|
uint16_t cpu_addr;
|
|
|
|
uint8_t res3[152];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* Basic Machine CPUs */
|
|
|
|
struct sysib_122 {
|
|
|
|
uint8_t res1[32];
|
|
|
|
uint32_t capability;
|
|
|
|
uint16_t total_cpus;
|
|
|
|
uint16_t active_cpus;
|
|
|
|
uint16_t standby_cpus;
|
|
|
|
uint16_t reserved_cpus;
|
|
|
|
uint16_t adjustments[2026];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* LPAR CPU */
|
|
|
|
struct sysib_221 {
|
|
|
|
uint32_t res1[80];
|
|
|
|
uint8_t sequence[16];
|
|
|
|
uint8_t plant[4];
|
|
|
|
uint16_t cpu_id;
|
|
|
|
uint16_t cpu_addr;
|
|
|
|
uint8_t res3[152];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* LPAR CPUs */
|
|
|
|
struct sysib_222 {
|
|
|
|
uint32_t res1[32];
|
|
|
|
uint16_t lpar_num;
|
|
|
|
uint8_t res2;
|
|
|
|
uint8_t lcpuc;
|
|
|
|
uint16_t total_cpus;
|
|
|
|
uint16_t conf_cpus;
|
|
|
|
uint16_t standby_cpus;
|
|
|
|
uint16_t reserved_cpus;
|
|
|
|
uint8_t name[8];
|
|
|
|
uint32_t caf;
|
|
|
|
uint8_t res3[16];
|
|
|
|
uint16_t dedicated_cpus;
|
|
|
|
uint16_t shared_cpus;
|
|
|
|
uint8_t res4[180];
|
|
|
|
};
|
|
|
|
|
|
|
|
/* VM CPUs */
|
|
|
|
struct sysib_322 {
|
|
|
|
uint8_t res1[31];
|
|
|
|
uint8_t count;
|
|
|
|
struct {
|
|
|
|
uint8_t res2[4];
|
|
|
|
uint16_t total_cpus;
|
|
|
|
uint16_t conf_cpus;
|
|
|
|
uint16_t standby_cpus;
|
|
|
|
uint16_t reserved_cpus;
|
|
|
|
uint8_t name[8];
|
|
|
|
uint32_t caf;
|
|
|
|
uint8_t cpi[16];
|
2015-03-04 01:35:27 +08:00
|
|
|
uint8_t res5[3];
|
|
|
|
uint8_t ext_name_encoding;
|
|
|
|
uint32_t res3;
|
|
|
|
uint8_t uuid[16];
|
2011-04-15 23:32:47 +08:00
|
|
|
} vm[8];
|
2015-03-04 01:35:27 +08:00
|
|
|
uint8_t res4[1504];
|
|
|
|
uint8_t ext_names[8][256];
|
2011-04-15 23:32:47 +08:00
|
|
|
};
|
|
|
|
|
|
|
|
/* MMU defines */
|
|
|
|
#define _ASCE_ORIGIN ~0xfffULL /* segment table origin */
|
|
|
|
#define _ASCE_SUBSPACE 0x200 /* subspace group control */
|
|
|
|
#define _ASCE_PRIVATE_SPACE 0x100 /* private space control */
|
|
|
|
#define _ASCE_ALT_EVENT 0x80 /* storage alteration event control */
|
|
|
|
#define _ASCE_SPACE_SWITCH 0x40 /* space switch event */
|
|
|
|
#define _ASCE_REAL_SPACE 0x20 /* real space control */
|
|
|
|
#define _ASCE_TYPE_MASK 0x0c /* asce table type mask */
|
|
|
|
#define _ASCE_TYPE_REGION1 0x0c /* region first table type */
|
|
|
|
#define _ASCE_TYPE_REGION2 0x08 /* region second table type */
|
|
|
|
#define _ASCE_TYPE_REGION3 0x04 /* region third table type */
|
|
|
|
#define _ASCE_TYPE_SEGMENT 0x00 /* segment table type */
|
|
|
|
#define _ASCE_TABLE_LENGTH 0x03 /* region table length */
|
|
|
|
|
|
|
|
#define _REGION_ENTRY_ORIGIN ~0xfffULL /* region/segment table origin */
|
2015-02-13 01:09:26 +08:00
|
|
|
#define _REGION_ENTRY_RO 0x200 /* region/segment protection bit */
|
2015-02-13 01:09:21 +08:00
|
|
|
#define _REGION_ENTRY_TF 0xc0 /* region/segment table offset */
|
2011-04-15 23:32:47 +08:00
|
|
|
#define _REGION_ENTRY_INV 0x20 /* invalid region table entry */
|
|
|
|
#define _REGION_ENTRY_TYPE_MASK 0x0c /* region/segment table type mask */
|
|
|
|
#define _REGION_ENTRY_TYPE_R1 0x0c /* region first table type */
|
|
|
|
#define _REGION_ENTRY_TYPE_R2 0x08 /* region second table type */
|
|
|
|
#define _REGION_ENTRY_TYPE_R3 0x04 /* region third table type */
|
|
|
|
#define _REGION_ENTRY_LENGTH 0x03 /* region third length */
|
|
|
|
|
|
|
|
#define _SEGMENT_ENTRY_ORIGIN ~0x7ffULL /* segment table origin */
|
2014-04-25 21:37:19 +08:00
|
|
|
#define _SEGMENT_ENTRY_FC 0x400 /* format control */
|
2011-04-15 23:32:47 +08:00
|
|
|
#define _SEGMENT_ENTRY_RO 0x200 /* page protection bit */
|
|
|
|
#define _SEGMENT_ENTRY_INV 0x20 /* invalid segment table entry */
|
|
|
|
|
2017-06-01 06:01:01 +08:00
|
|
|
#define VADDR_PX 0xff000 /* page index bits */
|
|
|
|
|
2011-04-15 23:32:47 +08:00
|
|
|
#define _PAGE_RO 0x200 /* HW read-only bit */
|
|
|
|
#define _PAGE_INVALID 0x400 /* HW invalid bit */
|
2015-02-13 01:09:28 +08:00
|
|
|
#define _PAGE_RES0 0x800 /* bit must be zero */
|
2011-04-15 23:32:47 +08:00
|
|
|
|
2011-07-14 17:49:08 +08:00
|
|
|
#define SK_C (0x1 << 1)
|
|
|
|
#define SK_R (0x1 << 2)
|
|
|
|
#define SK_F (0x1 << 3)
|
|
|
|
#define SK_ACC_MASK (0xf << 4)
|
2011-04-15 23:32:47 +08:00
|
|
|
|
2015-02-24 21:15:22 +08:00
|
|
|
/* SIGP order codes */
|
2011-04-15 23:32:47 +08:00
|
|
|
#define SIGP_SENSE 0x01
|
|
|
|
#define SIGP_EXTERNAL_CALL 0x02
|
|
|
|
#define SIGP_EMERGENCY 0x03
|
|
|
|
#define SIGP_START 0x04
|
|
|
|
#define SIGP_STOP 0x05
|
|
|
|
#define SIGP_RESTART 0x06
|
|
|
|
#define SIGP_STOP_STORE_STATUS 0x09
|
|
|
|
#define SIGP_INITIAL_CPU_RESET 0x0b
|
|
|
|
#define SIGP_CPU_RESET 0x0c
|
|
|
|
#define SIGP_SET_PREFIX 0x0d
|
|
|
|
#define SIGP_STORE_STATUS_ADDR 0x0e
|
|
|
|
#define SIGP_SET_ARCH 0x12
|
2017-09-29 04:36:57 +08:00
|
|
|
#define SIGP_SENSE_RUNNING 0x15
|
2015-01-14 22:57:16 +08:00
|
|
|
#define SIGP_STORE_ADTL_STATUS 0x17
|
2011-04-15 23:32:47 +08:00
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2015-02-24 21:15:22 +08:00
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/* SIGP condition codes */
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#define SIGP_CC_ORDER_CODE_ACCEPTED 0
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#define SIGP_CC_STATUS_STORED 1
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#define SIGP_CC_BUSY 2
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#define SIGP_CC_NOT_OPERATIONAL 3
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/* SIGP status bits */
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2011-04-15 23:32:47 +08:00
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#define SIGP_STAT_EQUIPMENT_CHECK 0x80000000UL
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2017-09-29 04:36:57 +08:00
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#define SIGP_STAT_NOT_RUNNING 0x00000400UL
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2011-04-15 23:32:47 +08:00
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#define SIGP_STAT_INCORRECT_STATE 0x00000200UL
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#define SIGP_STAT_INVALID_PARAMETER 0x00000100UL
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#define SIGP_STAT_EXT_CALL_PENDING 0x00000080UL
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#define SIGP_STAT_STOPPED 0x00000040UL
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#define SIGP_STAT_OPERATOR_INTERV 0x00000020UL
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#define SIGP_STAT_CHECK_STOP 0x00000010UL
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#define SIGP_STAT_INOPERATIVE 0x00000004UL
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#define SIGP_STAT_INVALID_ORDER 0x00000002UL
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#define SIGP_STAT_RECEIVER_CHECK 0x00000001UL
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2015-02-24 21:15:27 +08:00
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/* SIGP SET ARCHITECTURE modes */
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#define SIGP_MODE_ESA_S390 0
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#define SIGP_MODE_Z_ARCH_TRANS_ALL_PSW 1
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#define SIGP_MODE_Z_ARCH_TRANS_CUR_PSW 2
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2017-05-09 16:27:58 +08:00
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/* SIGP order code mask corresponding to bit positions 56-63 */
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#define SIGP_ORDER_MASK 0x000000ff
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2014-08-28 23:25:33 +08:00
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/* from s390-virtio-ccw */
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#define MEM_SECTION_SIZE 0x10000000UL
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2014-08-28 23:25:35 +08:00
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#define MAX_AVAIL_SLOTS 32
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2014-08-28 23:25:33 +08:00
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2015-10-08 21:05:46 +08:00
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/* machine check interruption code */
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/* subclasses */
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#define MCIC_SC_SD 0x8000000000000000ULL
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#define MCIC_SC_PD 0x4000000000000000ULL
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#define MCIC_SC_SR 0x2000000000000000ULL
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#define MCIC_SC_CD 0x0800000000000000ULL
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#define MCIC_SC_ED 0x0400000000000000ULL
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#define MCIC_SC_DG 0x0100000000000000ULL
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#define MCIC_SC_W 0x0080000000000000ULL
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#define MCIC_SC_CP 0x0040000000000000ULL
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#define MCIC_SC_SP 0x0020000000000000ULL
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#define MCIC_SC_CK 0x0010000000000000ULL
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/* subclass modifiers */
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#define MCIC_SCM_B 0x0002000000000000ULL
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#define MCIC_SCM_DA 0x0000000020000000ULL
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#define MCIC_SCM_AP 0x0000000000080000ULL
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/* storage errors */
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#define MCIC_SE_SE 0x0000800000000000ULL
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#define MCIC_SE_SC 0x0000400000000000ULL
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#define MCIC_SE_KE 0x0000200000000000ULL
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#define MCIC_SE_DS 0x0000100000000000ULL
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#define MCIC_SE_IE 0x0000000080000000ULL
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/* validity bits */
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#define MCIC_VB_WP 0x0000080000000000ULL
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#define MCIC_VB_MS 0x0000040000000000ULL
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#define MCIC_VB_PM 0x0000020000000000ULL
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#define MCIC_VB_IA 0x0000010000000000ULL
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#define MCIC_VB_FA 0x0000008000000000ULL
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#define MCIC_VB_VR 0x0000004000000000ULL
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#define MCIC_VB_EC 0x0000002000000000ULL
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#define MCIC_VB_FP 0x0000001000000000ULL
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#define MCIC_VB_GR 0x0000000800000000ULL
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#define MCIC_VB_CR 0x0000000400000000ULL
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#define MCIC_VB_ST 0x0000000100000000ULL
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#define MCIC_VB_AR 0x0000000040000000ULL
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2017-02-15 11:47:49 +08:00
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#define MCIC_VB_GS 0x0000000008000000ULL
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2015-10-08 21:05:46 +08:00
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#define MCIC_VB_PR 0x0000000000200000ULL
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#define MCIC_VB_FC 0x0000000000100000ULL
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#define MCIC_VB_CT 0x0000000000020000ULL
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#define MCIC_VB_CC 0x0000000000010000ULL
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2017-08-18 19:43:53 +08:00
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/* cpu.c */
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int s390_get_clock(uint8_t *tod_high, uint64_t *tod_low);
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int s390_set_clock(uint8_t *tod_high, uint64_t *tod_low);
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void s390_crypto_reset(void);
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bool s390_get_squash_mcss(void);
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int s390_get_memslot_count(void);
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int s390_set_memory_limit(uint64_t new_limit, uint64_t *hw_limit);
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void s390_cmma_reset(void);
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void s390_enable_css_support(S390CPU *cpu);
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int s390_assign_subch_ioeventfd(EventNotifier *notifier, uint32_t sch_id,
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int vq, bool assign);
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#ifndef CONFIG_USER_ONLY
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unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu);
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#else
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static inline unsigned int s390_cpu_set_state(uint8_t cpu_state, S390CPU *cpu)
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{
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return 0;
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}
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#endif /* CONFIG_USER_ONLY */
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/* cpu_models.c */
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void s390_cpu_list(FILE *f, fprintf_function cpu_fprintf);
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#define cpu_list s390_cpu_list
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/* helper.c */
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2017-08-31 21:19:38 +08:00
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#define cpu_init(cpu_model) cpu_generic_init(TYPE_S390_CPU, cpu_model)
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2017-09-13 21:24:15 +08:00
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S390CPU *s390x_new_cpu(const char *typename, uint32_t core_id, Error **errp);
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2017-09-21 20:59:08 +08:00
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#define S390_CPU_TYPE_SUFFIX "-" TYPE_S390_CPU
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#define S390_CPU_TYPE_NAME(name) (name S390_CPU_TYPE_SUFFIX)
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2017-08-18 19:43:53 +08:00
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/* you can call this signal handler from your SIGBUS and SIGSEGV
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signal handlers to inform the virtual CPU of exceptions. non zero
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is returned if the signal was handled by the virtual CPU. */
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int cpu_s390x_signal_handler(int host_signum, void *pinfo, void *puc);
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#define cpu_signal_handler cpu_s390x_signal_handler
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/* interrupt.c */
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void s390_crw_mchk(void);
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void s390_io_interrupt(uint16_t subchannel_id, uint16_t subchannel_nr,
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uint32_t io_int_parm, uint32_t io_int_word);
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/* automatically detect the instruction length */
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#define ILEN_AUTO 0xff
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void program_interrupt(CPUS390XState *env, uint32_t code, int ilen);
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/* service interrupts are floating therefore we must not pass an cpustate */
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void s390_sclp_extint(uint32_t parm);
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/* mmu_helper.c */
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int s390_cpu_virt_mem_rw(S390CPU *cpu, vaddr laddr, uint8_t ar, void *hostbuf,
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int len, bool is_write);
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#define s390_cpu_virt_mem_read(cpu, laddr, ar, dest, len) \
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s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, false)
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#define s390_cpu_virt_mem_write(cpu, laddr, ar, dest, len) \
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s390_cpu_virt_mem_rw(cpu, laddr, ar, dest, len, true)
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#define s390_cpu_virt_mem_check_write(cpu, laddr, ar, len) \
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s390_cpu_virt_mem_rw(cpu, laddr, ar, NULL, len, true)
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2017-09-29 04:36:54 +08:00
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/* sigp.c */
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int s390_cpu_restart(S390CPU *cpu);
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void s390_init_sigp(void);
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|
2017-08-18 19:43:53 +08:00
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|
/* outside of target/s390x/ */
|
|
|
|
S390CPU *s390_cpu_addr2state(uint16_t cpu_addr);
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|
2009-12-05 19:44:21 +08:00
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|
#endif
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