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Fix Thumb variable shift condition code bug. 

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1748 c046a42c-6fe2-441c-8c8c-71466251a162
This commit is contained in:
pbrook 2006-02-07 03:34:35 +00:00
parent af2f67333f
commit 3aa22b4b53
1 changed files with 4 additions and 0 deletions
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4
target-arm/translate.c
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@ -1930,12 +1930,15 @@ static void disas_thumb_insn(DisasContext *s)
break; break;
case 0x2: /* lsl */ case 0x2: /* lsl */
gen_op_shll_T1_T0_cc(); gen_op_shll_T1_T0_cc();
gen_op_logic_T1_cc();
break; break;
case 0x3: /* lsr */ case 0x3: /* lsr */
gen_op_shrl_T1_T0_cc(); gen_op_shrl_T1_T0_cc();
gen_op_logic_T1_cc();
break; break;
case 0x4: /* asr */ case 0x4: /* asr */
gen_op_sarl_T1_T0_cc(); gen_op_sarl_T1_T0_cc();
gen_op_logic_T1_cc();
break; break;
case 0x5: /* adc */ case 0x5: /* adc */
gen_op_adcl_T0_T1_cc(); gen_op_adcl_T0_T1_cc();
@ -1945,6 +1948,7 @@ static void disas_thumb_insn(DisasContext *s)
break; break;
case 0x7: /* ror */ case 0x7: /* ror */
gen_op_rorl_T1_T0_cc(); gen_op_rorl_T1_T0_cc();
gen_op_logic_T1_cc();
break; break;
case 0x8: /* tst */ case 0x8: /* tst */
gen_op_andl_T0_T1(); gen_op_andl_T0_T1();