Coalesce all standard configuration sections into single
DEFAULT_SECTIONS macro for all cores. This allows to add new features in
a single place: overlay_tool.h
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Test that non-locking prefetch operations don't cause exceptions on
missing TLB and that other 'hit' cache operations do.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Add path to the core configuration directory to test build command and
replace .include asm directive with #include to enable preprocessing.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Some test suites, like MMU, need per-test initialization. Don't make them
redefine test macro, add test_init for that purpose.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Check privilege level for privileged instructions (IHU, III, IIU and IPFL
are privileged), memory accessibility for instructions that reference memory
(IH* and IPFL) and windowed register validity for all instruction cache
instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Check privilege level for privileged instructions (DHI, DHU, DII, DIU, DIWB,
DIWBI, DPFL are privileged), memory accessibility for instructions that
reference memory (all DH* and DPFL) and windowed register validity for all
data cache instructions.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
The following registers control whether MAC can receive frames:
- MODER.RXEN bit that enables/disables receiver;
- TX_BD_NUM register that specifies number of RX descriptors.
Notify QEMU networking core when the MAC is ready to receive frames.
Discard frame and raise BUSY interrupt when the frame arrives but the
current RX descriptor is not empty.
Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Reviewed-by: Paolo Bonzini <pbonzini@redhat.com>
* Fix a bug causing an assertion in the NVIC on ARMv7M models
* More A64 Neon instructions
* Refactor cpreg API to separate out access check functions, as
groundwork for AArch64 system mode
* Fix bug in linux-user A64 store-exclusive of XZR
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABCAAGBQJTBeM5AAoJEDwlJe0UNgzecwwP/1mujaECNj2BPWxGMLTzF4M5
2PCLYbTNPZumb1b6Z1qrCVbrGBS7bKL1lSCKA5Isji1HHyRnNtaJNGMqI7p2AzaE
pPvI+0jhrmdbG2cqgeGbbYMabNdzBTEAhwPo5LQO7wP6CYQDlYH3JVVlcYc6Vl7b
hahAI49AV1HM+Xo9z7DSI2VSA2rI2tgbHpIHrvYwtp2exQnPNZBMyZu42yJdK2Lb
1gsVvnni/mA71KydbM6drhHzk2wd9OrrkFxZG94kOIWUxzarDxIapWUPWr006j7c
wd2jA639OM9wGwyLgmO537smxr+iV7iLAdz6JkI026po3GFxrrmSjVXS93vL9GHP
716kvTKHeG2WRJW1H0uJjUpzw4tFoKv8EQq3rv8McBwe6Cf+nJtfsY5OLa2GpzG5
bro6jeJmogoInfMxGxYPezeWFg0olBa17RgAZk9+Y33vPjQVbgGb9Xna1dndtbrU
e2/T6CAGIGXL3kXLFIiFGB1JBST4UGlGVX2kJLJU+Yv8nzdAZjwQ3gZFJno5DyFU
K9BZQGX932VCf4bgy1MPvZXO3pMN2iF7prDeHVZeGcw/zFTBDQHje32fCLFAGeuz
1qnIGvE/vXZQoaw52qv/kIGLmcBZiXiBNCm+ImttfGu5fjAhODEuAhBBU1Zjv3j7
1qnBhXlVSxOpLMpuJTIJ
=h/1p
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/pmaydell/tags/pull-target-arm-20140220' into staging
target-arm queue:
* Fix a bug causing an assertion in the NVIC on ARMv7M models
* More A64 Neon instructions
* Refactor cpreg API to separate out access check functions, as
groundwork for AArch64 system mode
* Fix bug in linux-user A64 store-exclusive of XZR
# gpg: Signature made Thu 20 Feb 2014 11:12:57 GMT using RSA key ID 14360CDE
# gpg: Good signature from "Peter Maydell <peter.maydell@linaro.org>"
* remotes/pmaydell/tags/pull-target-arm-20140220: (30 commits)
linux-user: AArch64: Fix exclusive store of the zero register
target-arm: A64: Implement unprivileged load/store
target-arm: A64: Implement narrowing three-reg-diff operations
target-arm: A64: Implement the wide 3-reg-different operations
target-arm: A64: Add most remaining three-reg-diff widening ops
target-arm: A64: Add opcode comments to disas_simd_three_reg_diff
target-arm: A64: Implement store-exclusive for system mode
target-arm: Fix incorrect type for value argument to write_raw_cp_reg
target-arm: Remove failure status return from read/write_raw_cp_reg
target-arm: Remove unnecessary code now read/write fns can't fail
target-arm: Drop success/fail return from cpreg read and write functions
target-arm: Convert miscellaneous reginfo structs to accessfn
target-arm: Convert generic timer reginfo to accessfn
target-arm: Convert performance monitor reginfo to accessfn
target-arm: Split cpreg access checks out from read/write functions
target-arm: Stop underdecoding ARM946 PRBS registers
target-arm: Log bad system register accesses with LOG_UNIMP
target-arm: Remove unused ARMCPUState sr substruct
target-arm: Restrict check_ap() use of S and R bits to v6 and earlier
target-arm: Define names for SCTLR bits
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTBMPKAAoJEJykq7OBq3PIYWkIAJsWLbCVaG352bY4bdhssSbX
H7IGS1eLYcJsZu6XLTh1KkesTJNhFzazG5XMagT8/5+Av9kkppnIs0K55G7qP+7R
YZR4lA7fEIS7wQivKbh7mcFJjYYlHZRWBx3fmTxWQtn/S9B2bLAcZDuAkHv7oXHH
ASCyFtbO23MJmAFBNUlqGU+DSGh0jCKyxJI2O3fgLlccgWkIdc0/5gaaLZbWpaKy
HmKKKkp6rISlJRLSUyytjldaZhRuDkUCRa+9fKeHJkGzB1o0zN6MqSloVyhKc73y
VrP1riHNOwecoZhpUs4t51/cogbrmuOWEydOwTLNbvtD5MGHGYblVWtY17OgibE=
=rwDt
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/stefanha/tags/qtest-monitor-process-pull-request' into staging
qtest resource cleanup pull request
# gpg: Signature made Wed 19 Feb 2014 14:46:34 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/qtest-monitor-process-pull-request:
qtest: kill QEMU process on g_assert() failure
qtest: make QEMU our direct child process
qtest: drop unused child_pid field
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1
iQEcBAABAgAGBQJTBNDcAAoJEJykq7OBq3PISEMIAIrJN9RTfpeAaUY4bSj9Q283
ReAgkTbe1yhuvik8E3sN9OOm24EfD9o2mE3Io2Jq1tslgM0yDXcuBoIT6rrmwF3L
MLRtE89JIStv1JbNyeorTgS8N/6kY0evKkmG8kskwHS3QVCKo3+OsPz7D6JNQrdA
KQNJZa19DVIfdgBGCD1HuGOVgCIe3rrGOc16/XvPuK3CXACyvfEO7B/1YStSXBu5
QmtccRMzCo7Xt6PwAvq4RclNa45lnjVvv0lcyApdajn/zFGBzXmK19NrMhDDHQC+
fLS3fmWQCo3dFeVwoyfUhamt3wxD3Mpp5PYEytJ5EOmv+UPuCQ1/8SQJjxxKESo=
=sVTF
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/stefanha/tags/tracing-pull-request' into staging
Tracing pull request
# gpg: Signature made Wed 19 Feb 2014 15:42:20 GMT using RSA key ID 81AB73C8
# gpg: Good signature from "Stefan Hajnoczi <stefanha@redhat.com>"
# gpg: aka "Stefan Hajnoczi <stefanha@gmail.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg: There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 8695 A8BF D3F9 7CDA AC35 775A 9CA4 ABB3 81AB 73C8
* remotes/stefanha/tags/tracing-pull-request:
trace-events: Fix typo in "offset"
Add ust generated files to .gitignore
Update documentation for LTTng ust tracing
Adapt Makefiles to the new LTTng ust interface
Modified the tracetool framework for LTTng 2.x
Fix configure script for LTTng 2.x
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Win32 doesn't have a cpuid.h, and MacOSX may have one but without
the __cpuid() function we use, which means that commit 9d2eec20
broke the build for those platforms. Fix this by tightening up
our configure cpuid.h check to test that the functions we need
are present, and adding some missing #ifdef guards in
tcg/i386/tcg-target.c.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
* remotes/rth/tcg-next:
tcg/i386: Use SHLX/SHRX/SARX instructions
tcg/i386: Use ANDN instruction
tcg/i386: Add tcg_out_vex_modrm
tcg/i386: Move TCG_CT_CONST_* to tcg-target.c
disas/i386: Disassemble ANDN/SHLX/SHRX/SHAX
tcg/optimize: Add more identity simplifications
tcg/optimize: Optmize ANDC X,Y,Y to MOV X,0
tcg/optimize: Simply some logical ops to NOT
tcg/optimize: Handle known-zeros masks for ANDC
tcg/optimize: add known-zero bits compute for load ops
tcg/optimize: improve known-zero bits for 32-bit ops
tcg/optimize: fix known-zero bits optimization
tcg/optimize: fix known-zero bits for right shift ops
tcg-arm: The shift count of op_rotl_i32 is in args[2] not args[1].
TCG: Fix 32-bit host allocation typo
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
* QTest cleanups and test cases for PCI NICs
* NAND fix for "info qtree"
* Cleanup and extension of QOM machine tests
* IndustryPack test cases and conversion to QOM realize
* I2C cleanups
* Cleanups of legacy qdev properties
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJTAooJAAoJEPou0S0+fgE/SuQQALW3zvra4ZLRAQV0e8kFoyj1
vVtmLkDhnCe4cYfxxfOX91NA0rH1ts2EO1+UcnaCHJlptNWfA+8qJW69XgYpHE3c
DKQlKPL/9pV5ywY5uUw/t1UJHg2BfrLBDDM4lP+vrpwiQYq4kp24JffnhfY3l9MA
9qdkXu1HrlWoLRVGnMyGDXI8cb+5bTL+FEc6UuHl3P89/gj5BV+LDWn0QOFbAkxq
4wk+Xh6sHKcfOdq6vMCNGlTjlJnpbY43D1a8+q6hFGG8JBlpne7Oer7bse9k4uTK
q/CzyNzC0lnjjcULpa4ptRlycH0ruD9DPY7Lco9XqYd3l/c9742PmTEqN5TZseKD
XD7+hwT1tk7W8rihm8KETCP6sKlXz4w8tJiWe6IT3zwRzvXIolxxK93heQuaX73Z
HFDmvTPVLUiWF8ftKTyWZM3w+jsbSH0QSrMCIHKJrPTRWTKphx0DUP74lWjNsvGs
FFBjpAgrflLihxiuRrcLmekGn0xCTjhQWIo2GoiWTgLSEHNQQQUNO+15/kcU/vlI
hh3DJpiBKeSnUapHHL0OEK6ryeHoG95akiRjImwWVthNLk4KEuWtlhFPYBtulO5A
PA02trE4Ah769effX0ZYdNl23KbW4VxpZ8VZv+kp7RTrDKxw551HoEFJ5ja0nkvB
O1CfsE7x0GH/Rbi/Hxhu
=KRcc
-----END PGP SIGNATURE-----
Merge remote-tracking branch 'remotes/afaerber/tags/qom-devices-for-peter' into staging
QOM infrastructure fixes and device conversions
* QTest cleanups and test cases for PCI NICs
* NAND fix for "info qtree"
* Cleanup and extension of QOM machine tests
* IndustryPack test cases and conversion to QOM realize
* I2C cleanups
* Cleanups of legacy qdev properties
# gpg: Signature made Mon 17 Feb 2014 22:15:37 GMT using RSA key ID 3E7E013F
# gpg: Good signature from "Andreas Färber <afaerber@suse.de>"
# gpg: aka "Andreas Färber <afaerber@suse.com>"
* remotes/afaerber/tags/qom-devices-for-peter: (49 commits)
qtest: Include system headers before user headers
qapi: Refine human printing of sizes
qdev: Use QAPI type names for properties
qdev: Add enum property types to QAPI schema
block: Handle "rechs" and "large" translation options
qdev: Remove hex8/32/64 property types
qdev: Remove most legacy printers
qdev: Use human mode in "info qtree"
qapi: Add human mode to StringOutputVisitor
qdev: Inline qdev_prop_parse()
qdev: Legacy properties are just strings
qdev: Legacy properties are now read-only
qdev: Remove legacy parsers for hex8/32/64
qdev: Sizes are now parsed by StringInputVisitor
qapi: Add size parser to StringInputVisitor
qtest: Don't segfault with invalid -qtest option
ipack: Move IndustryPack out of hw/char/
ipoctal232: QOM parent field cleanup
ipack: QOM parent field cleanup for IPackDevice
ipack: QOM parent field cleanup for IPackBus
...
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Janne Grunau <j@jannau.net>
Reviewed-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement the unprivileged load and store instructions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the narrowing three-reg-diff operations: ADDHN,
RADDHN, SUBHN and RSUBHN.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the wide three-reg-different operations:
SADDW, UADDW, SSUBW and USUBW.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add the remainder of the 64x64->128 operations in the three-reg-diff
category except for PMULL, PMULL2.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
The opcode switch in disas_simd_three_reg_diff() is missing the
customary comments indicating which cases correspond to which
instructions. Add them.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
System mode store-exclusive use a different code path to usermode ones;
implement this missing code, in a similar way to the 32 bit version.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
The write_raw_cp_reg's value argument should be a uint64_t, since
that's what all its callers hand it and what all the functions it
calls take. A (harmless) typo meant we were accidentally declaring
it as int64_t.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
The read_raw_cp_reg and write_raw_cp_reg functions can now never
fail (in fact they should never have failed previously unless
there was a bug in a reginfo that meant no raw accessor was
provided for a might-trap register). This allows us to clean up
their prototypes so the write function returns void and the
read function returns the value read, which in turn lets us
simplify the callers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Now that cpreg read and write functions can't fail and throw an
exception, we can remove the code from the translator that synchronises
the guest PC in case an exception is thrown.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
All cpreg read and write functions now return 0, so we can clean up
their prototypes:
* write functions return void
* read functions return the value rather than taking a pointer
to write the value to
This is a fairly mechanical change which makes only the bare
minimum set of changes to the callers of read and write functions.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Convert the remaining miscellaneous cases of reginfo read/write
functions returning EXCP_UDEF to use an accessfn instead:
TEEHBR, and the ATS address-translation operations.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Convert the reginfo structs for the generic timer registers
to use access functions rather than returning EXCP_UDEF from
their read handlers. In some cases this allows us to remove
a read handler completely.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Convert the performance monitor reginfo definitions to use
an accessfn rather than returning EXCP_UDEF from read and
write functions. This also allows us to fix a couple of XXX
cases where we weren't imposing the access restrictions on
RAZ/WI or constant registers.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Several of the system registers handled via the ARMCPRegInfo
mechanism have access trap control bits controlling whether the
registers are accessible to lower privilege levels. Replace
the existing mechanism (allowing the read and write functions
to return EXCP_UDEF if access is denied) with a dedicated
"check access rights" function pointer in the ARMCPRegInfo.
This will allow us to simplify some of the register definitions,
which no longer need read/write functions purely to handle
the access checks.
We take the opportunity to define the return value from the
access checking function in a way that allows us to set the
correct exception syndrome information for exceptions taken
to AArch64 (which may need to distinguish access failures due
to a configurable trap or enable from other kinds of access
failure).
This commit defines the new mechanism but does not move any
of the registers across to use it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
The ARM946 has 8 PRBS (protection region base and size) registers.
Currently we implement these with a CP_ANY reginfo; however this
underdecodes (since there are 16 possible values of CRm but only
8 registers) and we catch the invalid values in the read and
write functions. However this causes issues with migration since
we only migrate the first of a wildcard register set, so we only
migrate c6_region[0]. It also makes it awkward to pull reginfo
access checks out into their own function.
Avoid all these problems by just defining separate reginfo structs
for each of the 8 registers; this also lets us avoid having any
read or write functions and will result in more efficient direct
field accesses from generated code.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Log guest attempts to access unimplemented system registers via
the LOG_UNIMP reporting mechanism (for both the 32 bit and 64 bit
instruction sets). This is particularly useful for debugging
problems where the guest is trying to use a system register that
QEMU doesn't implement.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Remove the 'struct sr' from ARMCPUState -- it isn't actually used and is
a hangover from the original separate system register implementation used
by the SuSE linux-user-mode-only AArch64 target.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
The SCTLR bits S and R (8 and 9) only exist in ARMv6 and earlier.
In ARMv7 these bits RAZ, and in ARMv8 they are reassigned. Guard
the use of them in check_ap() so that we don't get incorrect results
for ARMv8 CPUs.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
The SCTLR is full of bits for enabling or disabling various things, and so
there are many places in the code which check if certain bits are set.
Define some named constants for the SCTLR bits so these checks are easier
to read.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Extend the set of CPUs for which we provide a QEMU_KVM_ARM_TARGET_*
constant to include all the ones currently supported by the kernel
headers we are using.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Implement the remaining instructions in the SIMD 3-reg-same
and scalar-3-reg-same groups: FMULX, FRECPS, FRSQRTS, FACGE,
FACGT, FMLA and FMLS.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
The ARMv8 instruction set includes a fused floating point
reciprocal square root step instruction which demands an
"(x * y + z) / 2" fused operation. Support this by adding
a flag to the softfloat muladd operations which requests
that the result is halved before rounding.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Add support for the floating-point pairwise operations
FADDP, FMAXP, FMAXNMP, FMINP and FMINNMP. To do this we use the
code which was previously handling only integer pairwise operations,
and push the integer-specific decode and handling of unallocated
cases up one level in the call tree, so we can also call it from
the floating-point section of the decoder.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
This adds all forms of the SIMD floating point and set instructions:
FCM(GT|GE|EQ|LE|LT)
Most of the heavy lifting is done by either the existing neon helpers or
some new helpers for the 64bit double cases. Most of the code paths are
common although the 2misc versions are a little special as they compare
against zero.
Signed-off-by: Alex Bennée <alex.bennee@linaro.org>
[PMM: fixed some minor bugs, added the 2-misc-scalar encoding]
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the scalar three different instruction group:
it only has three instructions in it.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the SIMD scalar indexed instructions. The encoding
here is nearly identical to the vector indexed grouping, so
we combine the two.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement the 'long' operations in the vector x indexed
element category.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Implement all the SIMD vector x indexed element instructions
in the subcategory which are not 'long' ops.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Commit 40d225009e accidentally changed the behaviour of
gic_acknowledge_irq() for the NVIC. The NVIC doesn't have SGIs,
so this meant we hit an assertion:
gic_acknowledge_irq: Assertion `s->sgi_pending[irq][cpu] != 0' failed.
Return NVIC acknowledge-irq to its previous behaviour, like 11MPCore.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Commit 1b90d56e changed the implementation of in/out imm to not assign
the accessed port number to cpu_T[0] as it appeared unnecessary.
However, currently gen_check_io() makes use of cpu_T[0] to implement the
I/O bitmap checks, so it's in fact still used and the change broke the
check, leading to #GP in legitimate cases (and probably also allowing
access to ports that shouldn't be allowed).
This patch reintroduces the missing assignment for these cases.
Signed-off-by: Kevin Wolf <kwolf@redhat.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
Max Filippov