Kito Cheng 5836c3ecce RISC-V: linux-user support for RVE ABI ... This change checks elf_flags for EF_RISCV_RVE and if present uses the RVE linux syscall ABI which uses t0 for the syscall number instead of a7. Warn and exit if a non-RVE ABI binary is run on a cpu with the RVE extension as it is incompatible. Cc: Palmer Dabbelt <palmer@sifive.com> Cc: Sagar Karandikar <sagark@eecs.berkeley.edu> Cc: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> Cc: Alistair Francis <Alistair.Francis@wdc.com> Co-authored-by: Kito Cheng <kito.cheng@gmail.com> Co-authored-by: Michael Clark <mjc@sifive.com> Signed-off-by: Michael Clark <mjc@sifive.com> Signed-off-by: Alistair Francis <alistair.francis@wdc.com> Signed-off-by: Palmer Dabbelt <palmer@sifive.com>		2019-03-19 05:14:39 -07:00
..
insn_trans	target/riscv: Fix manually parsed 16 bit insn	2019-03-17 22:21:32 -07:00
Makefile.objs	target/riscv: Convert quadrant 0 of RVXC insns to decodetree	2019-03-13 10:34:06 +01:00
cpu.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
cpu.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
cpu_bits.h	RISC-V: Fixes to CSR_* register macros.	2019-03-19 05:13:24 -07:00
cpu_helper.c	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 05:14:39 -07:00
cpu_user.h	RISC-V: linux-user support for RVE ABI	2019-03-19 05:14:39 -07:00
csr.c	RISC-V: Allow interrupt controllers to claim interrupts	2019-03-19 05:14:39 -07:00
fpu_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
gdbstub.c	RISC-V: Add hooks to use the gdb xml files.	2019-03-19 05:13:24 -07:00
helper.h	RISC-V CPU Helpers	2018-03-07 08:30:28 +13:00
insn16.decode	target/riscv: Convert quadrant 2 of RVXC insns to decodetree	2019-03-13 10:40:46 +01:00
insn32-64.decode	target/riscv: Convert RV64D insns to decodetree	2019-03-13 10:34:06 +01:00
insn32.decode	target/riscv: make ADD/SUB/OR/XOR/AND insn use arg lists	2019-03-13 10:40:50 +01:00
instmap.h	RISC-V TCG Code Generation	2018-03-07 08:30:28 +13:00
op_helper.c	RISC-V: Use riscv prefix consistently on cpu helpers	2019-02-11 15:56:21 -08:00
pmp.c	riscv: pmp: Log pmp access errors as guest errors	2019-03-19 05:14:38 -07:00
pmp.h	RISC-V Physical Memory Protection	2018-03-07 08:30:28 +13:00
translate.c	target/riscv: Remove decode_RV32_64G()	2019-03-13 10:40:50 +01:00