aurel32 bbc0d79cb7 MIPS: Fix tlbwi/tlbwr ... In CP0 Index register, bit 31 means 'Probe Failure', while lowest bits contain the TLB index. In tlbwi and tlbwr instructions, this Probe Failure bit must be ignored when reading the TLB index. Attached patch fixes it. (Hervé Poussineau) git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5215 c046a42c-6fe2-441c-8c8c-71466251a162		2008-09-14 17:09:56 +00:00
..
TODO	Clarify some TODO items.	2008-06-24 22:04:41 +00:00
cpu.h	Less hardcoding of TARGET_USER_ONLY.	2008-07-23 16:14:22 +00:00
exec.h	MIPS: remove empty cpu_mips_irqctrl_init()	2008-09-14 16:38:57 +00:00
helper.c	Less hardcoding of TARGET_USER_ONLY.	2008-07-23 16:14:22 +00:00
helper.h	Less hardcoding of TARGET_USER_ONLY.	2008-07-23 16:14:22 +00:00
machine.c	Change MIPS machine default to Malta.	2008-07-05 21:51:47 +00:00
mips-defs.h	Support for VR5432, and some of its special instructions. Original patch	2007-12-25 20:46:56 +00:00
op_helper.c	MIPS: Fix tlbwi/tlbwr	2008-09-14 17:09:56 +00:00
translate.c	TCG fixes for target-mips	2008-09-05 14:19:17 +00:00
translate_init.c	target-mips: fix warning	2008-09-14 16:28:26 +00:00