linux_old1/drivers/pci/host/Kconfig

95 lines
2.5 KiB
Plaintext
Raw Normal View History

menu "PCI host controller drivers"
depends on PCI
config PCI_DRA7XX
bool "TI DRA7xx PCIe controller"
select PCIE_DW
depends on OF && HAS_IOMEM && TI_PIPE3
help
Enables support for the PCIe controller in the DRA7xx SoC. There
are two instances of PCIe controller in DRA7xx. This controller can
act both as EP and RC. This reuses the Designware core.
config PCI_MVEBU
bool "Marvell EBU PCIe controller"
depends on ARCH_MVEBU || ARCH_DOVE
depends on OF
config PCIE_DW
bool
config PCI_EXYNOS
bool "Samsung Exynos PCIe controller"
depends on SOC_EXYNOS5440
select PCIEPORTBUS
select PCIE_DW
config PCI_IMX6
bool "Freescale i.MX6 PCIe controller"
depends on SOC_IMX6Q
select PCIEPORTBUS
select PCIE_DW
config PCI_TEGRA
bool "NVIDIA Tegra PCIe controller"
depends on ARCH_TEGRA
config PCI_RCAR_GEN2
bool "Renesas R-Car Gen2 Internal PCI controller"
depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
help
Say Y here if you want internal PCI support on R-Car Gen2 SoC.
There are 3 internal PCI controllers available with a single
built-in EHCI/OHCI host controller present on each one.
config PCI_RCAR_GEN2_PCIE
bool "Renesas R-Car PCIe controller"
depends on ARCH_SHMOBILE || (ARM && COMPILE_TEST)
help
Say Y here if you want PCIe controller support on R-Car Gen2 SoCs.
config PCI_HOST_GENERIC
bool "Generic PCI host controller"
depends on ARM && OF
help
Say Y here if you want to support a simple generic PCI host
controller, such as the one emulated by kvmtool.
config PCIE_SPEAR13XX
bool "STMicroelectronics SPEAr PCIe controller"
depends on ARCH_SPEAR13XX
select PCIEPORTBUS
select PCIE_DW
help
Say Y here if you want PCIe support on SPEAr13XX SoCs.
config PCI_KEYSTONE
bool "TI Keystone PCIe controller"
depends on ARCH_KEYSTONE
select PCIE_DW
select PCIEPORTBUS
help
Say Y here if you want to enable PCI controller support on Keystone
SoCs. The PCI controller on Keystone is based on Designware hardware
and therefore the driver re-uses the Designware core functions to
implement the driver.
Merge branches 'pci/misc', 'pci/pm', 'pci/host-designware', 'pci/host-imx6', 'pci/host-keystone', 'pci/host-tegra' and 'pci/host-xilinx' into next * pci/misc: PCI/AER: Make <linux/aer.h> standalone includable PCI: Remove unnecessary variable in pci_add_dynid() * pci/pm: PCI/PM: Allow PCI devices to be put into D3cold during system suspend PCI/PM: Drop unused runtime PM support code for PCIe ports * pci/host-designware: PCI: designware: Check private_data validity in single place PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init() PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus() PCI: designware: Parse bus-range property from devicetree PCI: designware: Add support for v3.65 hardware * pci/host-imx6: PCI: imx6: Probe in module_init(), not fs_initcall() PCI: designware: Remove pci_assign_unassigned_resources() from dw_pcie_host_init() PCI: designware: Use pci_create_root_bus() instead of pci_scan_root_bus() PCI: designware: Parse bus-range property from devicetree PCI: imx6: Put LTSSM in "Detect" state before disabling it MAINTAINERS: Add Lucas Stach as co-maintainer for i.MX6 PCI driver PCI: designware: Add support for v3.65 hardware * pci/host-keystone: PCI: keystone: Add TI Keystone PCIe driver PCI: designware: Add support for v3.65 hardware * pci/host-tegra: PCI: tegra: Implement a proper resource hierarchy PCI: tegra: Add missing cleanup in error path and tegra_msi_teardown_irq() resources: Add device-managed request/release_resource() * pci/host-xilinx: PCI: xilinx: Add Xilinx AXI PCIe Host Bridge IP driver Conflicts: drivers/pci/host/Kconfig drivers/pci/host/Makefile
2014-09-06 00:57:20 +08:00
config PCIE_XILINX
bool "Xilinx AXI PCIe host bridge support"
depends on ARCH_ZYNQ
help
Say 'Y' here if you want kernel to support the Xilinx AXI PCIe
Host Bridge driver.
config PCI_XGENE
bool "X-Gene PCIe controller"
depends on ARCH_XGENE
depends on OF
select PCIEPORTBUS
help
Say Y here if you want internal PCI support on APM X-Gene SoC.
There are 5 internal PCIe ports available. Each port is GEN3 capable
and have varied lanes from x1 to x8.
endmenu