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Renesas ARM Based SoC DT Updates for v4.7 

* Configure NMI key as wakeup source in DT of kzm9g board
 * Add SDHI support to DT of gose board
 * Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC
 * Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs
 * Add IIC support to DT of r8a7794 SoC
 * Add CAN support to DT of r8a7793 and r8a7794 SoCs
 * Add SCIF2 support to r8a7790 device tree
 * Use CAN, JPU and USB3.0 fallback compatibility string
   in DT of r8a7791 and r8a7790 SoCs
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Merge tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Merge "Renesas ARM Based SoC DT Updates for v4.7" from Simon Horman:

* Configure NMI key as wakeup source in DT of kzm9g board
* Add SDHI support to DT of gose board
* Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC
* Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs
* Add IIC support to DT of r8a7794 SoC
* Add CAN support to DT of r8a7793 and r8a7794 SoCs
* Add SCIF2 support to r8a7790 device tree
* Use CAN, JPU and USB3.0 fallback compatibility string
  in DT of r8a7791 and r8a7790 SoCs

* tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits)
  ARM: dts: gose: Enable SDHI controllers
  ARM: dts: r8a7793: Add SDHI controllers
  ARM: dts: r8a7790: fix max-frequency for SDHI
  ARM: dts: kzm9g: Configure NMI key as wake-up source
  ARM: dts: r8a7790: lager: Enable UHS-I SDR-50
  ARM: dts: r8a7790: Set maximum frequencies for SDHI clocks
  ARM: dts: r8a7791: Use USB3.0 fallback compatibility string
  ARM: dts: r8a7790: Use USB3.0 fallback compatibility string
  ARM: dts: r8a7779: Correct interrupt type for ARM TWD
  ARM: dts: sh73a0: Correct interrupt type for ARM TWD
  ARM: dts: r8a7794: Add IIC nodes
  ARM: dts: r8a7794: add IIC clocks
  ARM: dts: r8a7793: add CAN nodes to device tree
  ARM: dts: r8a7793: add CAN clocks to device tree
  ARM: dts: r8a7794: add CAN nodes to device tree
  ARM: dts: r8a7794: add CAN clocks to device tree
  ARM: dts: r8a7790: use fallback can compatibility string
  ARM: dts: r8a7791: use fallback can compatibility string
  ARM: dts: r8a7790: Add SCIF2 device node
  ARM: dts: r8a7790: Add SCIF2 clock
  ...
This commit is contained in:
Arnd Bergmann 2016-04-25 23:01:39 +02:00
parent 9b61aefce7 6f92cb2f45
commit 05ad9c3e77
11 changed files with 343 additions and 29 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

2
arch/arm/boot/dts/r8a7779.dtsi
View File

@ -67,7 +67,7 @@ timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>; reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 interrupts = <GIC_PPI 13
(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>; (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&cpg_clocks R8A7779_CLK_ZS>; clocks = <&cpg_clocks R8A7779_CLK_ZS>;
}; };

22
arch/arm/boot/dts/r8a7790-lager.dts
View File

@ -345,11 +345,25 @@ scifa1_pins: serial1 {
sdhi0_pins: sd0 { sdhi0_pins: sd0 {
groups = "sdhi0_data4", "sdhi0_ctrl"; groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0"; function = "sdhi0";
power-source = <3300>;
};
sdhi0_pins_uhs: sd0_uhs {
groups = "sdhi0_data4", "sdhi0_ctrl";
function = "sdhi0";
power-source = <1800>;
}; };
sdhi2_pins: sd2 { sdhi2_pins: sd2 {
groups = "sdhi2_data4", "sdhi2_ctrl"; groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2"; function = "sdhi2";
power-source = <3300>;
};
sdhi2_pins_uhs: sd2_uhs {
groups = "sdhi2_data4", "sdhi2_ctrl";
function = "sdhi2";
power-source = <1800>;
}; };
mmc1_pins: mmc1 { mmc1_pins: mmc1 {
@ -538,21 +552,25 @@ pmic: pmic@0 {
&sdhi0 { &sdhi0 {
pinctrl-0 = <&sdhi0_pins>; pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default"; pinctrl-1 = <&sdhi0_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi0>; vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>; vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
status = "okay"; status = "okay";
}; };
&sdhi2 { &sdhi2 {
pinctrl-0 = <&sdhi2_pins>; pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default"; pinctrl-1 = <&sdhi2_pins_uhs>;
pinctrl-names = "default", "state_uhs";
vmmc-supply = <&vcc_sdhi2>; vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>; vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>; cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
sd-uhs-sdr50;
status = "okay"; status = "okay";
}; };

32
arch/arm/boot/dts/r8a7790.dtsi
View File

@ -589,6 +589,7 @@ sdhi0: sd@ee100000 {
clocks = <&mstp3_clks R8A7790_CLK_SDHI0>; clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
dmas = <&dmac1 0xcd>, <&dmac1 0xce>; dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
max-frequency = <195000000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -600,6 +601,7 @@ sdhi1: sd@ee120000 {
clocks = <&mstp3_clks R8A7790_CLK_SDHI1>; clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
dmas = <&dmac1 0xc9>, <&dmac1 0xca>; dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
max-frequency = <195000000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -611,6 +613,7 @@ sdhi2: sd@ee140000 {
clocks = <&mstp3_clks R8A7790_CLK_SDHI2>; clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
dmas = <&dmac1 0xc1>, <&dmac1 0xc2>; dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
max-frequency = <97500000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -622,6 +625,7 @@ sdhi3: sd@ee160000 {
clocks = <&mstp3_clks R8A7790_CLK_SDHI3>; clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
dmas = <&dmac1 0xd3>, <&dmac1 0xd4>; dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
dma-names = "tx", "rx"; dma-names = "tx", "rx";
max-frequency = <97500000>;
power-domains = <&cpg_clocks>; power-domains = <&cpg_clocks>;
status = "disabled"; status = "disabled";
}; };
@ -732,6 +736,20 @@ scif1: serial@e6e68000 {
status = "disabled"; status = "disabled";
}; };
scif2: serial@e6e56000 {
compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
"renesas,scif";
reg = <0 0xe6e56000 0 64>;
interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
<&scif_clk>;
clock-names = "fck", "brg_int", "scif_clk";
dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
status = "disabled";
};
hscif0: serial@e62c0000 { hscif0: serial@e62c0000 {
compatible = "renesas,hscif-r8a7790", compatible = "renesas,hscif-r8a7790",
"renesas,rcar-gen2-hscif", "renesas,hscif"; "renesas,rcar-gen2-hscif", "renesas,hscif";
@ -968,7 +986,7 @@ du_out_lvds1: endpoint {
}; };
can0: can@e6e80000 { can0: can@e6e80000 {
compatible = "renesas,can-r8a7790"; compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>; reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_RCAN0>, clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
@ -979,7 +997,7 @@ can0: can@e6e80000 {
}; };
can1: can@e6e88000 { can1: can@e6e88000 {
compatible = "renesas,can-r8a7790"; compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>; reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7790_CLK_RCAN1>, clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
@ -990,7 +1008,7 @@ can1: can@e6e88000 {
}; };
jpu: jpeg-codec@fe980000 { jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7790"; compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>; reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7790_CLK_JPU>; clocks = <&mstp1_clks R8A7790_CLK_JPU>;
@ -1302,19 +1320,19 @@ R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
mstp3_clks: mstp3_clks@e615013c { mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>, clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
<&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>, <&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>, <&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
<&hp_clk>, <&hp_clk>; <&hp_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3 R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0 R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1 R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1 R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
>; >;
clock-output-names = clock-output-names =
"iic2", "tpu0", "mmcif1", "sdhi3", "iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
"sdhi2", "sdhi1", "sdhi0", "mmcif0", "sdhi2", "sdhi1", "sdhi0", "mmcif0",
"iic0", "pciec", "iic1", "ssusb", "cmt1", "iic0", "pciec", "iic1", "ssusb", "cmt1",
"usbdmac0", "usbdmac1"; "usbdmac0", "usbdmac1";
@ -1499,7 +1517,7 @@ msiof3: spi@e6c90000 {
}; };
xhci: usb@ee000000 { xhci: usb@ee000000 {
compatible = "renesas,xhci-r8a7790"; compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
reg = <0 0xee000000 0 0xc00>; reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7790_CLK_SSUSB>; clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;

8
arch/arm/boot/dts/r8a7791.dtsi
View File

@ -1013,7 +1013,7 @@ du_out_lvds0: endpoint {
}; };
can0: can@e6e80000 { can0: can@e6e80000 {
compatible = "renesas,can-r8a7791"; compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>; reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_RCAN0>, clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
@ -1024,7 +1024,7 @@ can0: can@e6e80000 {
}; };
can1: can@e6e88000 { can1: can@e6e88000 {
compatible = "renesas,can-r8a7791"; compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>; reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7791_CLK_RCAN1>, clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
@ -1035,7 +1035,7 @@ can1: can@e6e88000 {
}; };
jpu: jpeg-codec@fe980000 { jpu: jpeg-codec@fe980000 {
compatible = "renesas,jpu-r8a7791"; compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
reg = <0 0xfe980000 0 0x10300>; reg = <0 0xfe980000 0 0x10300>;
interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp1_clks R8A7791_CLK_JPU>; clocks = <&mstp1_clks R8A7791_CLK_JPU>;
@ -1520,7 +1520,7 @@ msiof2: spi@e6e00000 {
}; };
xhci: usb@ee000000 { xhci: usb@ee000000 {
compatible = "renesas,xhci-r8a7791"; compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
reg = <0 0xee000000 0 0xc00>; reg = <0 0xee000000 0 0xc00>;
interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>; interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7791_CLK_SSUSB>; clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;

119
arch/arm/boot/dts/r8a7793-gose.dts
View File

@ -158,6 +158,78 @@ led8 {
}; };
}; };
vcc_sdhi0: regulator@0 {
compatible = "regulator-fixed";
regulator-name = "SDHI0 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi0: regulator@1 {
compatible = "regulator-gpio";
regulator-name = "SDHI0 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi1: regulator@2 {
compatible = "regulator-fixed";
regulator-name = "SDHI1 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi1: regulator@3 {
compatible = "regulator-gpio";
regulator-name = "SDHI1 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
vcc_sdhi2: regulator@4 {
compatible = "regulator-fixed";
regulator-name = "SDHI2 Vcc";
regulator-min-microvolt = <3300000>;
regulator-max-microvolt = <3300000>;
gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
enable-active-high;
};
vccq_sdhi2: regulator@5 {
compatible = "regulator-gpio";
regulator-name = "SDHI2 VccQ";
regulator-min-microvolt = <1800000>;
regulator-max-microvolt = <3300000>;
gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
gpios-states = <1>;
states = <3300000 1
1800000 0>;
};
audio_clock: audio_clock { audio_clock: audio_clock {
compatible = "fixed-clock"; compatible = "fixed-clock";
#clock-cells = <0>; #clock-cells = <0>;
@ -273,6 +345,21 @@ phy1_pins: phy1 {
function = "intc"; function = "intc";
}; };
sdhi0_pins: sd0 {
renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
renesas,function = "sdhi0";
};
sdhi1_pins: sd1 {
renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
renesas,function = "sdhi1";
};
sdhi2_pins: sd2 {
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
renesas,function = "sdhi2";
};
qspi_pins: spi0 { qspi_pins: spi0 {
groups = "qspi_ctrl", "qspi_data4"; groups = "qspi_ctrl", "qspi_data4";
function = "qspi"; function = "qspi";
@ -328,6 +415,38 @@ &scif_clk {
status = "okay"; status = "okay";
}; };
&sdhi0 {
pinctrl-0 = <&sdhi0_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi0>;
vqmmc-supply = <&vccq_sdhi0>;
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sdhi1 {
pinctrl-0 = <&sdhi1_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi1>;
vqmmc-supply = <&vccq_sdhi1>;
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
status = "okay";
};
&sdhi2 {
pinctrl-0 = <&sdhi2_pins>;
pinctrl-names = "default";
vmmc-supply = <&vcc_sdhi2>;
vqmmc-supply = <&vccq_sdhi2>;
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
status = "okay";
};
&qspi { &qspi {
pinctrl-0 = <&qspi_pins>; pinctrl-0 = <&qspi_pins>;
pinctrl-names = "default"; pinctrl-names = "default";

82
arch/arm/boot/dts/r8a7793.dtsi
View File

@ -507,6 +507,39 @@ pfc: pfc@e6060000 {
reg = <0 0xe6060000 0 0x250>; reg = <0 0xe6060000 0 0x250>;
}; };
sdhi0: sd@ee100000 {
compatible = "renesas,sdhi-r8a7793";
reg = <0 0xee100000 0 0x328>;
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
status = "disabled";
};
sdhi1: sd@ee140000 {
compatible = "renesas,sdhi-r8a7793";
reg = <0 0xee140000 0 0x100>;
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
status = "disabled";
};
sdhi2: sd@ee160000 {
compatible = "renesas,sdhi-r8a7793";
reg = <0 0xee160000 0 0x100>;
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
status = "disabled";
};
scifa0: serial@e6c40000 { scifa0: serial@e6c40000 {
compatible = "renesas,scifa-r8a7793", compatible = "renesas,scifa-r8a7793",
"renesas,rcar-gen2-scifa", "renesas,scifa"; "renesas,rcar-gen2-scifa", "renesas,scifa";
@ -806,6 +839,28 @@ du_out_lvds0: endpoint {
}; };
}; };
can0: can@e6e80000 {
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
can1: can@e6e88000 {
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
clocks { clocks {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@ -839,6 +894,22 @@ audio_clk_c: audio_clk_c {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
status = "disabled";
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -853,7 +924,7 @@ cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7793-cpg-clocks", compatible = "renesas,r8a7793-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks"; "renesas,rcar-gen2-cpg-clocks";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>; clocks = <&extal_clk &usb_extal_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3", clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z", "lb", "qspi", "sdh", "sd0", "z",
@ -1081,6 +1152,7 @@ mstp9_clks: mstp9_clks@e6150994 {
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&p_clk>, <&p_clk>,
<&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>, <&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>, <&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>; <&hp_clk>, <&hp_clk>;
@ -1090,7 +1162,8 @@ R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4 R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2 R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0 R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5 R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4 R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
R8A7793_CLK_I2C3 R8A7793_CLK_I2C2 R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
R8A7793_CLK_I2C1 R8A7793_CLK_I2C0 R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
@ -1098,8 +1171,9 @@ R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
clock-output-names = clock-output-names =
"gpio7", "gpio6", "gpio5", "gpio4", "gpio7", "gpio6", "gpio5", "gpio4",
"gpio3", "gpio2", "gpio1", "gpio0", "gpio3", "gpio2", "gpio1", "gpio0",
"qspi_mod", "i2c5", "i2c6", "i2c4", "rcan1", "rcan0", "qspi_mod", "i2c5",
"i2c3", "i2c2", "i2c1", "i2c0"; "i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
"i2c0";
}; };
mstp10_clks: mstp10_clks@e6150998 { mstp10_clks: mstp10_clks@e6150998 {
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";

92
arch/arm/boot/dts/r8a7794.dtsi
View File

@ -26,6 +26,8 @@ aliases {
i2c3 = &i2c3; i2c3 = &i2c3;
i2c4 = &i2c4; i2c4 = &i2c4;
i2c5 = &i2c5; i2c5 = &i2c5;
i2c6 = &i2c6;
i2c7 = &i2c7;
spi0 = &qspi; spi0 = &qspi;
vin0 = &vin0; vin0 = &vin0;
vin1 = &vin1; vin1 = &vin1;
@ -629,6 +631,32 @@ i2c5: i2c@e6528000 {
status = "disabled"; status = "disabled";
}; };
i2c6: i2c@e6500000 {
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
reg = <0 0xe6500000 0 0x425>;
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
i2c7: i2c@e6510000 {
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
reg = <0 0xe6510000 0 0x425>;
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
dma-names = "tx", "rx";
power-domains = <&cpg_clocks>;
#address-cells = <1>;
#size-cells = <0>;
status = "disabled";
};
mmcif0: mmc@ee200000 { mmcif0: mmc@ee200000 {
compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif"; compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
reg = <0 0xee200000 0 0x80>; reg = <0 0xee200000 0 0x80>;
@ -830,6 +858,28 @@ du_out_rgb1: endpoint {
}; };
}; };
can0: can@e6e80000 {
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
reg = <0 0xe6e80000 0 0x1000>;
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
can1: can@e6e88000 {
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
reg = <0 0xe6e88000 0 0x1000>;
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
clock-names = "clkp1", "clkp2", "can_clk";
power-domains = <&cpg_clocks>;
status = "disabled";
};
clocks { clocks {
#address-cells = <2>; #address-cells = <2>;
#size-cells = <2>; #size-cells = <2>;
@ -843,6 +893,22 @@ extal_clk: extal {
clock-frequency = <0>; clock-frequency = <0>;
}; };
/* External USB clock - can be overridden by the board */
usb_extal_clk: usb_extal {
compatible = "fixed-clock";
#clock-cells = <0>;
clock-frequency = <48000000>;
};
/* External CAN clock */
can_clk: can {
compatible = "fixed-clock";
#clock-cells = <0>;
/* This value must be overridden by the board. */
clock-frequency = <0>;
status = "disabled";
};
/* External SCIF clock */ /* External SCIF clock */
scif_clk: scif { scif_clk: scif {
compatible = "fixed-clock"; compatible = "fixed-clock";
@ -857,10 +923,11 @@ cpg_clocks: cpg_clocks@e6150000 {
compatible = "renesas,r8a7794-cpg-clocks", compatible = "renesas,r8a7794-cpg-clocks",
"renesas,rcar-gen2-cpg-clocks"; "renesas,rcar-gen2-cpg-clocks";
reg = <0 0xe6150000 0 0x1000>; reg = <0 0xe6150000 0 0x1000>;
clocks = <&extal_clk>; clocks = <&extal_clk &usb_extal_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-output-names = "main", "pll0", "pll1", "pll3", clock-output-names = "main", "pll0", "pll1", "pll3",
"lb", "qspi", "sdh", "sd0", "z"; "lb", "qspi", "sdh", "sd0", "z",
"rcan";
#power-domain-cells = <0>; #power-domain-cells = <0>;
}; };
/* Variable factor clocks */ /* Variable factor clocks */
@ -1060,16 +1127,19 @@ mstp3_clks: mstp3_clks@e615013c {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>; reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>, clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>; <&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = < clock-indices = <
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0 R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1 R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1 R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
>; >;
clock-output-names = clock-output-names =
"sdhi2", "sdhi1", "sdhi0", "sdhi2", "sdhi1", "sdhi0",
"mmcif0", "cmt1", "usbdmac0", "usbdmac1"; "mmcif0", "i2c6", "i2c7",
"cmt1", "usbdmac0", "usbdmac1";
}; };
mstp4_clks: mstp4_clks@e6150140 { mstp4_clks: mstp4_clks@e6150140 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
@ -1115,20 +1185,22 @@ mstp9_clks: mstp9_clks@e6150994 {
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks"; compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>; reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
<&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>, <&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>; <&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
<&hp_clk>, <&hp_clk>;
#clock-cells = <1>; #clock-cells = <1>;
clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5 clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3 R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1 R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
R8A7794_CLK_I2C5 R8A7794_CLK_I2C4 R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2 R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>; R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
clock-output-names = clock-output-names =
"gpio6", "gpio5", "gpio4", "gpio3", "gpio2", "gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
"gpio1", "gpio0", "qspi_mod", "gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0"; "i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
}; };
mstp11_clks: mstp11_clks@e615099c { mstp11_clks: mstp11_clks@e615099c {

7
arch/arm/boot/dts/sh73a0-kzm9g.dts
View File

@ -149,6 +149,13 @@ home-key {
label = "SW1"; label = "SW1";
wakeup-source; wakeup-source;
}; };
wakeup-key {
gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
linux,code = <KEY_WAKEUP>;
label = "NMI";
wakeup-source;
};
}; };
sound { sound {

2
arch/arm/boot/dts/sh73a0.dtsi
View File

@ -43,7 +43,7 @@ cpu@1 {
timer@f0000600 { timer@f0000600 {
compatible = "arm,cortex-a9-twd-timer"; compatible = "arm,cortex-a9-twd-timer";
reg = <0xf0000600 0x20>; reg = <0xf0000600 0x20>;
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>; interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
clocks = <&twd_clk>; clocks = <&twd_clk>;
}; };

1
include/dt-bindings/clock/r8a7790-clock.h
View File

@ -66,6 +66,7 @@
#define R8A7790_CLK_IIC2 0 #define R8A7790_CLK_IIC2 0
#define R8A7790_CLK_TPU0 4 #define R8A7790_CLK_TPU0 4
#define R8A7790_CLK_MMCIF1 5 #define R8A7790_CLK_MMCIF1 5
#define R8A7790_CLK_SCIF2 10
#define R8A7790_CLK_SDHI3 11 #define R8A7790_CLK_SDHI3 11
#define R8A7790_CLK_SDHI2 12 #define R8A7790_CLK_SDHI2 12
#define R8A7790_CLK_SDHI1 13 #define R8A7790_CLK_SDHI1 13

5
include/dt-bindings/clock/r8a7794-clock.h
View File

@ -21,6 +21,7 @@
#define R8A7794_CLK_SDH 6 #define R8A7794_CLK_SDH 6
#define R8A7794_CLK_SD0 7 #define R8A7794_CLK_SD0 7
#define R8A7794_CLK_Z 8 #define R8A7794_CLK_Z 8
#define R8A7794_CLK_RCAN 9
/* MSTP0 */ /* MSTP0 */
#define R8A7794_CLK_MSIOF0 0 #define R8A7794_CLK_MSIOF0 0
@ -56,6 +57,8 @@
#define R8A7794_CLK_SDHI1 12 #define R8A7794_CLK_SDHI1 12
#define R8A7794_CLK_SDHI0 14 #define R8A7794_CLK_SDHI0 14
#define R8A7794_CLK_MMCIF0 15 #define R8A7794_CLK_MMCIF0 15
#define R8A7794_CLK_IIC0 18
#define R8A7794_CLK_IIC1 23
#define R8A7794_CLK_CMT1 29 #define R8A7794_CLK_CMT1 29
#define R8A7794_CLK_USBDMAC0 30 #define R8A7794_CLK_USBDMAC0 30
#define R8A7794_CLK_USBDMAC1 31 #define R8A7794_CLK_USBDMAC1 31
@ -95,6 +98,8 @@
#define R8A7794_CLK_GPIO2 10 #define R8A7794_CLK_GPIO2 10
#define R8A7794_CLK_GPIO1 11 #define R8A7794_CLK_GPIO1 11
#define R8A7794_CLK_GPIO0 12 #define R8A7794_CLK_GPIO0 12
#define R8A7794_CLK_RCAN1 15
#define R8A7794_CLK_RCAN0 16
#define R8A7794_CLK_QSPI_MOD 17 #define R8A7794_CLK_QSPI_MOD 17
#define R8A7794_CLK_I2C5 25 #define R8A7794_CLK_I2C5 25
#define R8A7794_CLK_I2C4 27 #define R8A7794_CLK_I2C4 27