Renesas ARM Based SoC DT Updates for v4.7
* Configure NMI key as wakeup source in DT of kzm9g board * Add SDHI support to DT of gose board * Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC * Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs * Add IIC support to DT of r8a7794 SoC * Add CAN support to DT of r8a7793 and r8a7794 SoCs * Add SCIF2 support to r8a7790 device tree * Use CAN, JPU and USB3.0 fallback compatibility string in DT of r8a7791 and r8a7790 SoCs -----BEGIN PGP SIGNATURE----- Version: GnuPG v1 iQIcBAABAgAGBQJXHZwbAAoJENfPZGlqN0++3nUP/3sPtsfjE9v40DBnhiuO6nDA W3IW1mwlisw+R/HN8mkFun7OYDWjiY9dAjR7tHhKCxapztIxbWMG2pWgKmTKevIR m7RY8VCOWQIKDhpBEAalqxhpu5WAq5/Dfeyf2CF+CnPCnZA+CUsVS+gLdJRz5R0e yP5c9n9EaLMs/1IODQlgySQcdYrfal/SaRcsNDwnZZIH4L98DewhYAcXb7wYVL3Y n1bd4CAcHmKXk+rjauFnynXSCU/BIOEf+FiUlyHPgDAk3VrIAB9aos7C0S+lSCtr 4v7q0G0fizaeImtiDW2XrNIvBinbVb8vRWN4Q7hgPqDqJAxaPIa9Uy8QFf8Y2vZ7 Ki0VAtq0JFoH78CdzNMD7tHzOUMOgTio7mnvK66JAG/KtWVthBdGDMRd3sCl5wnQ Eepe8hEWBPMZF8XibIJ7HUpVFGDmBwrQ5hawsO3vYG6qiR/Cakc+8NLjMbx+y3AN j1LZL3uHWfNC/798MovmpMswhVFuP6MTdF2HTICwlC8rHCPW2J20w4F0HBiMZcSE KUsid/YhFMuILkMEDBLfnqtmrGgF4ugrVusxFqzl6nn7F3eiguYv4cq3CmBosK5d Lp2frlfUjSWjGcpr4J0+qXOwjZljCu+1tDeTlRAEHSuPyQXm3vNUYzuxGGgQKWOg Fs29CVOaPN5+QoFRv+O9 =vStA -----END PGP SIGNATURE----- Merge tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt Merge "Renesas ARM Based SoC DT Updates for v4.7" from Simon Horman: * Configure NMI key as wakeup source in DT of kzm9g board * Add SDHI support to DT of gose board * Add support of UHS-I SDR-50 for SDHI to DT of r8a7790 SoC * Correct interrupt type for ARM TWD in DT of r8a7779 and sh73a0 SoCs * Add IIC support to DT of r8a7794 SoC * Add CAN support to DT of r8a7793 and r8a7794 SoCs * Add SCIF2 support to r8a7790 device tree * Use CAN, JPU and USB3.0 fallback compatibility string in DT of r8a7791 and r8a7790 SoCs * tag 'renesas-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (22 commits) ARM: dts: gose: Enable SDHI controllers ARM: dts: r8a7793: Add SDHI controllers ARM: dts: r8a7790: fix max-frequency for SDHI ARM: dts: kzm9g: Configure NMI key as wake-up source ARM: dts: r8a7790: lager: Enable UHS-I SDR-50 ARM: dts: r8a7790: Set maximum frequencies for SDHI clocks ARM: dts: r8a7791: Use USB3.0 fallback compatibility string ARM: dts: r8a7790: Use USB3.0 fallback compatibility string ARM: dts: r8a7779: Correct interrupt type for ARM TWD ARM: dts: sh73a0: Correct interrupt type for ARM TWD ARM: dts: r8a7794: Add IIC nodes ARM: dts: r8a7794: add IIC clocks ARM: dts: r8a7793: add CAN nodes to device tree ARM: dts: r8a7793: add CAN clocks to device tree ARM: dts: r8a7794: add CAN nodes to device tree ARM: dts: r8a7794: add CAN clocks to device tree ARM: dts: r8a7790: use fallback can compatibility string ARM: dts: r8a7791: use fallback can compatibility string ARM: dts: r8a7790: Add SCIF2 device node ARM: dts: r8a7790: Add SCIF2 clock ...
This commit is contained in:
Arnd Bergmann
commit
05ad9c3e77
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@ -67,7 +67,7 @@ timer@f0000600 {
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compatible = "arm,cortex-a9-twd-timer";
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reg = <0xf0000600 0x20>;
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interrupts = <GIC_PPI 13
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_HIGH)>;
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(GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_EDGE_RISING)>;
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clocks = <&cpg_clocks R8A7779_CLK_ZS>;
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};
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@ -345,11 +345,25 @@ scifa1_pins: serial1 {
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sdhi0_pins: sd0 {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <3300>;
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};
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sdhi0_pins_uhs: sd0_uhs {
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groups = "sdhi0_data4", "sdhi0_ctrl";
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function = "sdhi0";
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power-source = <1800>;
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};
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sdhi2_pins: sd2 {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <3300>;
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};
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sdhi2_pins_uhs: sd2_uhs {
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groups = "sdhi2_data4", "sdhi2_ctrl";
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function = "sdhi2";
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power-source = <1800>;
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};
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mmc1_pins: mmc1 {
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@ -538,21 +552,25 @@ pmic: pmic@0 {
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&sdhi0 {
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pinctrl-0 = <&sdhi0_pins>;
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pinctrl-names = "default";
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pinctrl-1 = <&sdhi0_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi0>;
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vqmmc-supply = <&vccq_sdhi0>;
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cd-gpios = <&gpio3 6 GPIO_ACTIVE_LOW>;
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sd-uhs-sdr50;
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status = "okay";
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};
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&sdhi2 {
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pinctrl-0 = <&sdhi2_pins>;
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pinctrl-names = "default";
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pinctrl-1 = <&sdhi2_pins_uhs>;
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pinctrl-names = "default", "state_uhs";
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vmmc-supply = <&vcc_sdhi2>;
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vqmmc-supply = <&vccq_sdhi2>;
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cd-gpios = <&gpio3 22 GPIO_ACTIVE_LOW>;
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sd-uhs-sdr50;
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status = "okay";
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};
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@ -589,6 +589,7 @@ sdhi0: sd@ee100000 {
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clocks = <&mstp3_clks R8A7790_CLK_SDHI0>;
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dmas = <&dmac1 0xcd>, <&dmac1 0xce>;
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dma-names = "tx", "rx";
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max-frequency = <195000000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -600,6 +601,7 @@ sdhi1: sd@ee120000 {
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clocks = <&mstp3_clks R8A7790_CLK_SDHI1>;
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dmas = <&dmac1 0xc9>, <&dmac1 0xca>;
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dma-names = "tx", "rx";
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max-frequency = <195000000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -611,6 +613,7 @@ sdhi2: sd@ee140000 {
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clocks = <&mstp3_clks R8A7790_CLK_SDHI2>;
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dmas = <&dmac1 0xc1>, <&dmac1 0xc2>;
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dma-names = "tx", "rx";
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max-frequency = <97500000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -622,6 +625,7 @@ sdhi3: sd@ee160000 {
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clocks = <&mstp3_clks R8A7790_CLK_SDHI3>;
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dmas = <&dmac1 0xd3>, <&dmac1 0xd4>;
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dma-names = "tx", "rx";
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max-frequency = <97500000>;
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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@ -732,6 +736,20 @@ scif1: serial@e6e68000 {
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status = "disabled";
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};
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scif2: serial@e6e56000 {
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compatible = "renesas,scif-r8a7790", "renesas,rcar-gen2-scif",
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"renesas,scif";
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reg = <0 0xe6e56000 0 64>;
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interrupts = <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7790_CLK_SCIF2>, <&zs_clk>,
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<&scif_clk>;
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clock-names = "fck", "brg_int", "scif_clk";
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dmas = <&dmac0 0x2b>, <&dmac0 0x2c>;
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dma-names = "tx", "rx";
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power-domains = <&cpg_clocks>;
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status = "disabled";
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};
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hscif0: serial@e62c0000 {
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compatible = "renesas,hscif-r8a7790",
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"renesas,rcar-gen2-hscif", "renesas,hscif";
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@ -968,7 +986,7 @@ du_out_lvds1: endpoint {
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};
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7790";
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compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7790_CLK_RCAN0>,
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@ -979,7 +997,7 @@ can0: can@e6e80000 {
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};
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can1: can@e6e88000 {
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compatible = "renesas,can-r8a7790";
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compatible = "renesas,can-r8a7790", "renesas,rcar-gen2-can";
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reg = <0 0xe6e88000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7790_CLK_RCAN1>,
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@ -990,7 +1008,7 @@ can1: can@e6e88000 {
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};
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jpu: jpeg-codec@fe980000 {
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compatible = "renesas,jpu-r8a7790";
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compatible = "renesas,jpu-r8a7790", "renesas,rcar-gen2-jpu";
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reg = <0 0xfe980000 0 0x10300>;
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7790_CLK_JPU>;
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@ -1302,19 +1320,19 @@ R8A7790_CLK_SYS_DMAC1 R8A7790_CLK_SYS_DMAC0
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mstp3_clks: mstp3_clks@e615013c {
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compatible = "renesas,r8a7790-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
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clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&sd3_clk>,
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clocks = <&hp_clk>, <&cp_clk>, <&mmc1_clk>, <&p_clk>, <&sd3_clk>,
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<&sd2_clk>, <&cpg_clocks R8A7790_CLK_SD1>, <&cpg_clocks R8A7790_CLK_SD0>, <&mmc0_clk>,
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<&hp_clk>, <&mp_clk>, <&hp_clk>, <&mp_clk>, <&rclk_clk>,
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<&hp_clk>, <&hp_clk>;
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#clock-cells = <1>;
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clock-indices = <
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R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SDHI3
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R8A7790_CLK_IIC2 R8A7790_CLK_TPU0 R8A7790_CLK_MMCIF1 R8A7790_CLK_SCIF2 R8A7790_CLK_SDHI3
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R8A7790_CLK_SDHI2 R8A7790_CLK_SDHI1 R8A7790_CLK_SDHI0 R8A7790_CLK_MMCIF0
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R8A7790_CLK_IIC0 R8A7790_CLK_PCIEC R8A7790_CLK_IIC1 R8A7790_CLK_SSUSB R8A7790_CLK_CMT1
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R8A7790_CLK_USBDMAC0 R8A7790_CLK_USBDMAC1
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>;
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clock-output-names =
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"iic2", "tpu0", "mmcif1", "sdhi3",
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"iic2", "tpu0", "mmcif1", "scif2", "sdhi3",
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"sdhi2", "sdhi1", "sdhi0", "mmcif0",
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"iic0", "pciec", "iic1", "ssusb", "cmt1",
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"usbdmac0", "usbdmac1";
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@ -1499,7 +1517,7 @@ msiof3: spi@e6c90000 {
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};
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xhci: usb@ee000000 {
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compatible = "renesas,xhci-r8a7790";
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compatible = "renesas,xhci-r8a7790", "renesas,rcar-gen2-xhci";
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reg = <0 0xee000000 0 0xc00>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7790_CLK_SSUSB>;
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@ -1013,7 +1013,7 @@ du_out_lvds0: endpoint {
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};
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can0: can@e6e80000 {
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compatible = "renesas,can-r8a7791";
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compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
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reg = <0 0xe6e80000 0 0x1000>;
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interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_RCAN0>,
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@ -1024,7 +1024,7 @@ can0: can@e6e80000 {
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};
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can1: can@e6e88000 {
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compatible = "renesas,can-r8a7791";
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compatible = "renesas,can-r8a7791", "renesas,rcar-gen2-can";
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reg = <0 0xe6e88000 0 0x1000>;
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interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp9_clks R8A7791_CLK_RCAN1>,
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@ -1035,7 +1035,7 @@ can1: can@e6e88000 {
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};
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jpu: jpeg-codec@fe980000 {
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compatible = "renesas,jpu-r8a7791";
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compatible = "renesas,jpu-r8a7791", "renesas,rcar-gen2-jpu";
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reg = <0 0xfe980000 0 0x10300>;
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interrupts = <GIC_SPI 272 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp1_clks R8A7791_CLK_JPU>;
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@ -1520,7 +1520,7 @@ msiof2: spi@e6e00000 {
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};
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xhci: usb@ee000000 {
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compatible = "renesas,xhci-r8a7791";
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compatible = "renesas,xhci-r8a7791", "renesas,rcar-gen2-xhci";
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reg = <0 0xee000000 0 0xc00>;
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interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&mstp3_clks R8A7791_CLK_SSUSB>;
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@ -158,6 +158,78 @@ led8 {
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};
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};
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vcc_sdhi0: regulator@0 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI0 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio7 17 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi0: regulator@1 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI0 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 12 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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vcc_sdhi1: regulator@2 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI1 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio7 18 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi1: regulator@3 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI1 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 13 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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vcc_sdhi2: regulator@4 {
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compatible = "regulator-fixed";
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regulator-name = "SDHI2 Vcc";
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regulator-min-microvolt = <3300000>;
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regulator-max-microvolt = <3300000>;
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gpio = <&gpio7 19 GPIO_ACTIVE_HIGH>;
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enable-active-high;
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};
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vccq_sdhi2: regulator@5 {
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compatible = "regulator-gpio";
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regulator-name = "SDHI2 VccQ";
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regulator-min-microvolt = <1800000>;
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regulator-max-microvolt = <3300000>;
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gpios = <&gpio2 26 GPIO_ACTIVE_HIGH>;
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gpios-states = <1>;
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states = <3300000 1
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1800000 0>;
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};
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audio_clock: audio_clock {
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compatible = "fixed-clock";
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#clock-cells = <0>;
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||||
|
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@ -273,6 +345,21 @@ phy1_pins: phy1 {
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function = "intc";
|
||||
};
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|
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sdhi0_pins: sd0 {
|
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renesas,groups = "sdhi0_data4", "sdhi0_ctrl";
|
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renesas,function = "sdhi0";
|
||||
};
|
||||
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sdhi1_pins: sd1 {
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renesas,groups = "sdhi1_data4", "sdhi1_ctrl";
|
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renesas,function = "sdhi1";
|
||||
};
|
||||
|
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sdhi2_pins: sd2 {
|
||||
renesas,groups = "sdhi2_data4", "sdhi2_ctrl";
|
||||
renesas,function = "sdhi2";
|
||||
};
|
||||
|
||||
qspi_pins: spi0 {
|
||||
groups = "qspi_ctrl", "qspi_data4";
|
||||
function = "qspi";
|
||||
|
|
@ -328,6 +415,38 @@ &scif_clk {
|
|||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi0 {
|
||||
pinctrl-0 = <&sdhi0_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi0>;
|
||||
vqmmc-supply = <&vccq_sdhi0>;
|
||||
cd-gpios = <&gpio6 6 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 7 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi1 {
|
||||
pinctrl-0 = <&sdhi1_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi1>;
|
||||
vqmmc-supply = <&vccq_sdhi1>;
|
||||
cd-gpios = <&gpio6 14 GPIO_ACTIVE_LOW>;
|
||||
wp-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&sdhi2 {
|
||||
pinctrl-0 = <&sdhi2_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
||||
vmmc-supply = <&vcc_sdhi2>;
|
||||
vqmmc-supply = <&vccq_sdhi2>;
|
||||
cd-gpios = <&gpio6 22 GPIO_ACTIVE_LOW>;
|
||||
status = "okay";
|
||||
};
|
||||
|
||||
&qspi {
|
||||
pinctrl-0 = <&qspi_pins>;
|
||||
pinctrl-names = "default";
|
||||
|
|
|
|||
|
|
@ -507,6 +507,39 @@ pfc: pfc@e6060000 {
|
|||
reg = <0 0xe6060000 0 0x250>;
|
||||
};
|
||||
|
||||
sdhi0: sd@ee100000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee100000 0 0x328>;
|
||||
interrupts = <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI0>;
|
||||
dmas = <&dmac0 0xcd>, <&dmac0 0xce>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi1: sd@ee140000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee140000 0 0x100>;
|
||||
interrupts = <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI1>;
|
||||
dmas = <&dmac0 0xc1>, <&dmac0 0xc2>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
sdhi2: sd@ee160000 {
|
||||
compatible = "renesas,sdhi-r8a7793";
|
||||
reg = <0 0xee160000 0 0x100>;
|
||||
interrupts = <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7793_CLK_SDHI2>;
|
||||
dmas = <&dmac0 0xd3>, <&dmac0 0xd4>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
scifa0: serial@e6c40000 {
|
||||
compatible = "renesas,scifa-r8a7793",
|
||||
"renesas,rcar-gen2-scifa", "renesas,scifa";
|
||||
|
|
@ -806,6 +839,28 @@ du_out_lvds0: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7793", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7793_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7793_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -839,6 +894,22 @@ audio_clk_c: audio_clk_c {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -853,7 +924,7 @@ cpg_clocks: cpg_clocks@e6150000 {
|
|||
compatible = "renesas,r8a7793-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
|
|
@ -1081,6 +1152,7 @@ mstp9_clks: mstp9_clks@e6150994 {
|
|||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&p_clk>, <&p_clk>,
|
||||
<&cpg_clocks R8A7793_CLK_QSPI>, <&hp_clk>,
|
||||
<&cp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
|
|
@ -1090,7 +1162,8 @@ R8A7793_CLK_GPIO7 R8A7793_CLK_GPIO6
|
|||
R8A7793_CLK_GPIO5 R8A7793_CLK_GPIO4
|
||||
R8A7793_CLK_GPIO3 R8A7793_CLK_GPIO2
|
||||
R8A7793_CLK_GPIO1 R8A7793_CLK_GPIO0
|
||||
R8A7793_CLK_QSPI_MOD R8A7793_CLK_I2C5
|
||||
R8A7793_CLK_QSPI_MOD R8A7793_CLK_RCAN1
|
||||
R8A7793_CLK_RCAN0 R8A7793_CLK_I2C5
|
||||
R8A7793_CLK_IICDVFS R8A7793_CLK_I2C4
|
||||
R8A7793_CLK_I2C3 R8A7793_CLK_I2C2
|
||||
R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
|
||||
|
|
@ -1098,8 +1171,9 @@ R8A7793_CLK_I2C1 R8A7793_CLK_I2C0
|
|||
clock-output-names =
|
||||
"gpio7", "gpio6", "gpio5", "gpio4",
|
||||
"gpio3", "gpio2", "gpio1", "gpio0",
|
||||
"qspi_mod", "i2c5", "i2c6", "i2c4",
|
||||
"i2c3", "i2c2", "i2c1", "i2c0";
|
||||
"rcan1", "rcan0", "qspi_mod", "i2c5",
|
||||
"i2c6", "i2c4", "i2c3", "i2c2", "i2c1",
|
||||
"i2c0";
|
||||
};
|
||||
mstp10_clks: mstp10_clks@e6150998 {
|
||||
compatible = "renesas,r8a7793-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
|
|||
|
|
@ -26,6 +26,8 @@ aliases {
|
|||
i2c3 = &i2c3;
|
||||
i2c4 = &i2c4;
|
||||
i2c5 = &i2c5;
|
||||
i2c6 = &i2c6;
|
||||
i2c7 = &i2c7;
|
||||
spi0 = &qspi;
|
||||
vin0 = &vin0;
|
||||
vin1 = &vin1;
|
||||
|
|
@ -629,6 +631,32 @@ i2c5: i2c@e6528000 {
|
|||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c6: i2c@e6500000 {
|
||||
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6500000 0 0x425>;
|
||||
interrupts = <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC0>;
|
||||
dmas = <&dmac0 0x61>, <&dmac0 0x62>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
i2c7: i2c@e6510000 {
|
||||
compatible = "renesas,iic-r8a7794", "renesas,rmobile-iic";
|
||||
reg = <0 0xe6510000 0 0x425>;
|
||||
interrupts = <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp3_clks R8A7794_CLK_IIC1>;
|
||||
dmas = <&dmac0 0x65>, <&dmac0 0x66>;
|
||||
dma-names = "tx", "rx";
|
||||
power-domains = <&cpg_clocks>;
|
||||
#address-cells = <1>;
|
||||
#size-cells = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
mmcif0: mmc@ee200000 {
|
||||
compatible = "renesas,mmcif-r8a7794", "renesas,sh-mmcif";
|
||||
reg = <0 0xee200000 0 0x80>;
|
||||
|
|
@ -830,6 +858,28 @@ du_out_rgb1: endpoint {
|
|||
};
|
||||
};
|
||||
|
||||
can0: can@e6e80000 {
|
||||
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e80000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN0>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
can1: can@e6e88000 {
|
||||
compatible = "renesas,can-r8a7794", "renesas,rcar-gen2-can";
|
||||
reg = <0 0xe6e88000 0 0x1000>;
|
||||
interrupts = <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>;
|
||||
clocks = <&mstp9_clks R8A7794_CLK_RCAN1>,
|
||||
<&cpg_clocks R8A7794_CLK_RCAN>, <&can_clk>;
|
||||
clock-names = "clkp1", "clkp2", "can_clk";
|
||||
power-domains = <&cpg_clocks>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
clocks {
|
||||
#address-cells = <2>;
|
||||
#size-cells = <2>;
|
||||
|
|
@ -843,6 +893,22 @@ extal_clk: extal {
|
|||
clock-frequency = <0>;
|
||||
};
|
||||
|
||||
/* External USB clock - can be overridden by the board */
|
||||
usb_extal_clk: usb_extal {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
clock-frequency = <48000000>;
|
||||
};
|
||||
|
||||
/* External CAN clock */
|
||||
can_clk: can {
|
||||
compatible = "fixed-clock";
|
||||
#clock-cells = <0>;
|
||||
/* This value must be overridden by the board. */
|
||||
clock-frequency = <0>;
|
||||
status = "disabled";
|
||||
};
|
||||
|
||||
/* External SCIF clock */
|
||||
scif_clk: scif {
|
||||
compatible = "fixed-clock";
|
||||
|
|
@ -857,10 +923,11 @@ cpg_clocks: cpg_clocks@e6150000 {
|
|||
compatible = "renesas,r8a7794-cpg-clocks",
|
||||
"renesas,rcar-gen2-cpg-clocks";
|
||||
reg = <0 0xe6150000 0 0x1000>;
|
||||
clocks = <&extal_clk>;
|
||||
clocks = <&extal_clk &usb_extal_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-output-names = "main", "pll0", "pll1", "pll3",
|
||||
"lb", "qspi", "sdh", "sd0", "z";
|
||||
"lb", "qspi", "sdh", "sd0", "z",
|
||||
"rcan";
|
||||
#power-domain-cells = <0>;
|
||||
};
|
||||
/* Variable factor clocks */
|
||||
|
|
@ -1060,16 +1127,19 @@ mstp3_clks: mstp3_clks@e615013c {
|
|||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe615013c 0 4>, <0 0xe6150048 0 4>;
|
||||
clocks = <&sd3_clk>, <&sd2_clk>, <&cpg_clocks R8A7794_CLK_SD0>,
|
||||
<&mmc0_clk>, <&rclk_clk>, <&hp_clk>, <&hp_clk>;
|
||||
<&mmc0_clk>, <&hp_clk>, <&hp_clk>, <&rclk_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <
|
||||
R8A7794_CLK_SDHI2 R8A7794_CLK_SDHI1 R8A7794_CLK_SDHI0
|
||||
R8A7794_CLK_MMCIF0 R8A7794_CLK_CMT1
|
||||
R8A7794_CLK_MMCIF0 R8A7794_CLK_IIC0
|
||||
R8A7794_CLK_IIC1 R8A7794_CLK_CMT1
|
||||
R8A7794_CLK_USBDMAC0 R8A7794_CLK_USBDMAC1
|
||||
>;
|
||||
clock-output-names =
|
||||
"sdhi2", "sdhi1", "sdhi0",
|
||||
"mmcif0", "cmt1", "usbdmac0", "usbdmac1";
|
||||
"mmcif0", "i2c6", "i2c7",
|
||||
"cmt1", "usbdmac0", "usbdmac1";
|
||||
};
|
||||
mstp4_clks: mstp4_clks@e6150140 {
|
||||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
|
|
@ -1115,20 +1185,22 @@ mstp9_clks: mstp9_clks@e6150994 {
|
|||
compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
|
||||
reg = <0 0xe6150994 0 4>, <0 0xe61509a4 0 4>;
|
||||
clocks = <&cp_clk>, <&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>,
|
||||
<&cpg_clocks R8A7794_CLK_QSPI>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>;
|
||||
<&cp_clk>, <&cp_clk>, <&cp_clk>, <&p_clk>,
|
||||
<&p_clk>, <&cpg_clocks R8A7794_CLK_QSPI>,
|
||||
<&hp_clk>, <&hp_clk>, <&hp_clk>, <&hp_clk>,
|
||||
<&hp_clk>, <&hp_clk>;
|
||||
#clock-cells = <1>;
|
||||
clock-indices = <R8A7794_CLK_GPIO6 R8A7794_CLK_GPIO5
|
||||
R8A7794_CLK_GPIO4 R8A7794_CLK_GPIO3
|
||||
R8A7794_CLK_GPIO2 R8A7794_CLK_GPIO1
|
||||
R8A7794_CLK_GPIO0 R8A7794_CLK_QSPI_MOD
|
||||
R8A7794_CLK_GPIO0 R8A7794_CLK_RCAN1
|
||||
R8A7794_CLK_RCAN0 R8A7794_CLK_QSPI_MOD
|
||||
R8A7794_CLK_I2C5 R8A7794_CLK_I2C4
|
||||
R8A7794_CLK_I2C3 R8A7794_CLK_I2C2
|
||||
R8A7794_CLK_I2C1 R8A7794_CLK_I2C0>;
|
||||
clock-output-names =
|
||||
"gpio6", "gpio5", "gpio4", "gpio3", "gpio2",
|
||||
"gpio1", "gpio0", "qspi_mod",
|
||||
"gpio1", "gpio0", "rcan1", "rcan0", "qspi_mod",
|
||||
"i2c5", "i2c4", "i2c3", "i2c2", "i2c1", "i2c0";
|
||||
};
|
||||
mstp11_clks: mstp11_clks@e615099c {
|
||||
|
|
|
|||
|
|
@ -149,6 +149,13 @@ home-key {
|
|||
label = "SW1";
|
||||
wakeup-source;
|
||||
};
|
||||
|
||||
wakeup-key {
|
||||
gpios = <&pfc 159 GPIO_ACTIVE_LOW>;
|
||||
linux,code = <KEY_WAKEUP>;
|
||||
label = "NMI";
|
||||
wakeup-source;
|
||||
};
|
||||
};
|
||||
|
||||
sound {
|
||||
|
|
|
|||
|
|
@ -43,7 +43,7 @@ cpu@1 {
|
|||
timer@f0000600 {
|
||||
compatible = "arm,cortex-a9-twd-timer";
|
||||
reg = <0xf0000600 0x20>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_HIGH)>;
|
||||
interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_EDGE_RISING)>;
|
||||
clocks = <&twd_clk>;
|
||||
};
|
||||
|
||||
|
|
|
|||
|
|
@ -66,6 +66,7 @@
|
|||
#define R8A7790_CLK_IIC2 0
|
||||
#define R8A7790_CLK_TPU0 4
|
||||
#define R8A7790_CLK_MMCIF1 5
|
||||
#define R8A7790_CLK_SCIF2 10
|
||||
#define R8A7790_CLK_SDHI3 11
|
||||
#define R8A7790_CLK_SDHI2 12
|
||||
#define R8A7790_CLK_SDHI1 13
|
||||
|
|
|
|||
|
|
@ -21,6 +21,7 @@
|
|||
#define R8A7794_CLK_SDH 6
|
||||
#define R8A7794_CLK_SD0 7
|
||||
#define R8A7794_CLK_Z 8
|
||||
#define R8A7794_CLK_RCAN 9
|
||||
|
||||
/* MSTP0 */
|
||||
#define R8A7794_CLK_MSIOF0 0
|
||||
|
|
@ -56,6 +57,8 @@
|
|||
#define R8A7794_CLK_SDHI1 12
|
||||
#define R8A7794_CLK_SDHI0 14
|
||||
#define R8A7794_CLK_MMCIF0 15
|
||||
#define R8A7794_CLK_IIC0 18
|
||||
#define R8A7794_CLK_IIC1 23
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||||
#define R8A7794_CLK_CMT1 29
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#define R8A7794_CLK_USBDMAC0 30
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#define R8A7794_CLK_USBDMAC1 31
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@ -95,6 +98,8 @@
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#define R8A7794_CLK_GPIO2 10
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#define R8A7794_CLK_GPIO1 11
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#define R8A7794_CLK_GPIO0 12
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#define R8A7794_CLK_RCAN1 15
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#define R8A7794_CLK_RCAN0 16
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#define R8A7794_CLK_QSPI_MOD 17
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#define R8A7794_CLK_I2C5 25
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#define R8A7794_CLK_I2C4 27
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||||
|
|
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|||
Loading…
Reference in New Issue