drivers/iommu/amd: Clean up iommu_pc_get_set_reg()
Clean up coding style and fix a bug in the 64-bit register read logic since it overwrites the upper 32-bit when reading the lower 32-bit. Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com> Signed-off-by: Borislav Petkov <bp@suse.de> Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org> Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com> Cc: Arnaldo Carvalho de Melo <acme@redhat.com> Cc: Jiri Olsa <jolsa@redhat.com> Cc: Jörg Rödel <joro@8bytes.org> Cc: Linus Torvalds <torvalds@linux-foundation.org> Cc: Peter Zijlstra <peterz@infradead.org> Cc: Stephane Eranian <eranian@google.com> Cc: Thomas Gleixner <tglx@linutronix.de> Cc: Vince Weaver <vincent.weaver@maine.edu> Cc: iommu@lists.linux-foundation.org Link: http://lkml.kernel.org/r/1487926102-13073-5-git-send-email-Suravee.Suthikulpanit@amd.com Signed-off-by: Ingo Molnar <mingo@kernel.org>
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@ -2773,12 +2773,15 @@ static int iommu_pc_get_set_reg_val(struct amd_iommu *iommu,
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return -EINVAL;
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if (is_write) {
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writel((u32)*value, iommu->mmio_base + offset);
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writel((*value >> 32), iommu->mmio_base + offset + 4);
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u64 val = *value & GENMASK_ULL(47, 0);
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writel((u32)val, iommu->mmio_base + offset);
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writel((val >> 32), iommu->mmio_base + offset + 4);
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} else {
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*value = readl(iommu->mmio_base + offset + 4);
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*value <<= 32;
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*value = readl(iommu->mmio_base + offset);
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*value |= readl(iommu->mmio_base + offset);
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*value &= GENMASK_ULL(47, 0);
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}
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return 0;
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