cxgb4: collect MPS-TCAM dump
Signed-off-by: Rahul Lakkireddy <rahul.lakkireddy@chelsio.com> Signed-off-by: Ganesh Goudar <ganeshgr@chelsio.com> Signed-off-by: David S. Miller <davem@davemloft.net>
This commit is contained in:
Rahul Lakkireddy
David S. Miller
parent
9030e49897
commit
b289593e13
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@ -114,6 +114,27 @@ struct cudbg_tid_info_region_rev1 {
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u32 reserved[16];
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};
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#define CUDBG_MAX_RPLC_SIZE 128
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struct cudbg_mps_tcam {
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u64 mask;
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u32 rplc[8];
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u32 idx;
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u32 cls_lo;
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u32 cls_hi;
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u32 rplc_size;
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u32 vniy;
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u32 vnix;
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u32 dip_hit;
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u32 vlan_vld;
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u32 repli;
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u16 ivlan;
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u8 addr[ETH_ALEN];
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u8 lookup_type;
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u8 port_num;
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u8 reserved[2];
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};
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#define CUDBG_NUM_ULPTX 11
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#define CUDBG_NUM_ULPTX_READ 512
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@ -58,6 +58,7 @@ enum cudbg_dbg_entity_type {
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CUDBG_PCIE_INDIRECT = 50,
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CUDBG_PM_INDIRECT = 51,
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CUDBG_TID_INFO = 54,
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CUDBG_MPS_TCAM = 57,
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CUDBG_MA_INDIRECT = 61,
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CUDBG_ULPTX_LA = 62,
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CUDBG_UP_CIM_INDIRECT = 64,
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@ -987,6 +987,190 @@ int cudbg_collect_tid(struct cudbg_init *pdbg_init,
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return rc;
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}
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static inline void cudbg_tcamxy2valmask(u64 x, u64 y, u8 *addr, u64 *mask)
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{
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*mask = x | y;
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y = (__force u64)cpu_to_be64(y);
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memcpy(addr, (char *)&y + 2, ETH_ALEN);
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}
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static void cudbg_mps_rpl_backdoor(struct adapter *padap,
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struct fw_ldst_mps_rplc *mps_rplc)
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{
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if (is_t5(padap->params.chip)) {
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mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP3_A));
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mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP2_A));
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mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP1_A));
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mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP0_A));
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} else {
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mps_rplc->rplc255_224 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP7_A));
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mps_rplc->rplc223_192 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP6_A));
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mps_rplc->rplc191_160 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP5_A));
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mps_rplc->rplc159_128 = htonl(t4_read_reg(padap,
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MPS_VF_RPLCT_MAP4_A));
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}
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mps_rplc->rplc127_96 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP3_A));
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mps_rplc->rplc95_64 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP2_A));
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mps_rplc->rplc63_32 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP1_A));
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mps_rplc->rplc31_0 = htonl(t4_read_reg(padap, MPS_VF_RPLCT_MAP0_A));
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}
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static int cudbg_collect_tcam_index(struct adapter *padap,
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struct cudbg_mps_tcam *tcam, u32 idx)
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{
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u64 tcamy, tcamx, val;
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u32 ctl, data2;
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int rc = 0;
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if (CHELSIO_CHIP_VERSION(padap->params.chip) >= CHELSIO_T6) {
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/* CtlReqID - 1: use Host Driver Requester ID
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* CtlCmdType - 0: Read, 1: Write
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* CtlTcamSel - 0: TCAM0, 1: TCAM1
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* CtlXYBitSel- 0: Y bit, 1: X bit
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*/
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/* Read tcamy */
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ctl = CTLREQID_V(1) | CTLCMDTYPE_V(0) | CTLXYBITSEL_V(0);
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if (idx < 256)
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ctl |= CTLTCAMINDEX_V(idx) | CTLTCAMSEL_V(0);
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else
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ctl |= CTLTCAMINDEX_V(idx - 256) | CTLTCAMSEL_V(1);
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t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
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val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
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tcamy = DMACH_G(val) << 32;
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tcamy |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
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data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
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tcam->lookup_type = DATALKPTYPE_G(data2);
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/* 0 - Outer header, 1 - Inner header
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* [71:48] bit locations are overloaded for
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* outer vs. inner lookup types.
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*/
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if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
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/* Inner header VNI */
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tcam->vniy = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
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tcam->vniy = (tcam->vniy << 16) | VIDL_G(val);
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tcam->dip_hit = data2 & DATADIPHIT_F;
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} else {
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tcam->vlan_vld = data2 & DATAVIDH2_F;
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tcam->ivlan = VIDL_G(val);
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}
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tcam->port_num = DATAPORTNUM_G(data2);
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/* Read tcamx. Change the control param */
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ctl |= CTLXYBITSEL_V(1);
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t4_write_reg(padap, MPS_CLS_TCAM_DATA2_CTL_A, ctl);
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val = t4_read_reg(padap, MPS_CLS_TCAM_RDATA1_REQ_ID1_A);
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tcamx = DMACH_G(val) << 32;
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tcamx |= t4_read_reg(padap, MPS_CLS_TCAM_RDATA0_REQ_ID1_A);
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data2 = t4_read_reg(padap, MPS_CLS_TCAM_RDATA2_REQ_ID1_A);
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if (tcam->lookup_type && tcam->lookup_type != DATALKPTYPE_M) {
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/* Inner header VNI mask */
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tcam->vnix = (data2 & DATAVIDH2_F) | DATAVIDH1_G(data2);
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tcam->vnix = (tcam->vnix << 16) | VIDL_G(val);
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}
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} else {
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tcamy = t4_read_reg64(padap, MPS_CLS_TCAM_Y_L(idx));
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tcamx = t4_read_reg64(padap, MPS_CLS_TCAM_X_L(idx));
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}
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/* If no entry, return */
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if (tcamx & tcamy)
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return rc;
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tcam->cls_lo = t4_read_reg(padap, MPS_CLS_SRAM_L(idx));
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tcam->cls_hi = t4_read_reg(padap, MPS_CLS_SRAM_H(idx));
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if (is_t5(padap->params.chip))
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tcam->repli = (tcam->cls_lo & REPLICATE_F);
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else if (is_t6(padap->params.chip))
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tcam->repli = (tcam->cls_lo & T6_REPLICATE_F);
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if (tcam->repli) {
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struct fw_ldst_cmd ldst_cmd;
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struct fw_ldst_mps_rplc mps_rplc;
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memset(&ldst_cmd, 0, sizeof(ldst_cmd));
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ldst_cmd.op_to_addrspace =
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htonl(FW_CMD_OP_V(FW_LDST_CMD) |
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FW_CMD_REQUEST_F | FW_CMD_READ_F |
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FW_LDST_CMD_ADDRSPACE_V(FW_LDST_ADDRSPC_MPS));
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ldst_cmd.cycles_to_len16 = htonl(FW_LEN16(ldst_cmd));
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ldst_cmd.u.mps.rplc.fid_idx =
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htons(FW_LDST_CMD_FID_V(FW_LDST_MPS_RPLC) |
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FW_LDST_CMD_IDX_V(idx));
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rc = t4_wr_mbox(padap, padap->mbox, &ldst_cmd, sizeof(ldst_cmd),
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&ldst_cmd);
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if (rc)
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cudbg_mps_rpl_backdoor(padap, &mps_rplc);
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else
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mps_rplc = ldst_cmd.u.mps.rplc;
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tcam->rplc[0] = ntohl(mps_rplc.rplc31_0);
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tcam->rplc[1] = ntohl(mps_rplc.rplc63_32);
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tcam->rplc[2] = ntohl(mps_rplc.rplc95_64);
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tcam->rplc[3] = ntohl(mps_rplc.rplc127_96);
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if (padap->params.arch.mps_rplc_size > CUDBG_MAX_RPLC_SIZE) {
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tcam->rplc[4] = ntohl(mps_rplc.rplc159_128);
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tcam->rplc[5] = ntohl(mps_rplc.rplc191_160);
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tcam->rplc[6] = ntohl(mps_rplc.rplc223_192);
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tcam->rplc[7] = ntohl(mps_rplc.rplc255_224);
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}
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}
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cudbg_tcamxy2valmask(tcamx, tcamy, tcam->addr, &tcam->mask);
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tcam->idx = idx;
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tcam->rplc_size = padap->params.arch.mps_rplc_size;
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return rc;
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}
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int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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{
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struct adapter *padap = pdbg_init->adap;
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struct cudbg_buffer temp_buff = { 0 };
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u32 size = 0, i, n, total_size = 0;
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struct cudbg_mps_tcam *tcam;
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int rc;
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n = padap->params.arch.mps_tcam_size;
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size = sizeof(struct cudbg_mps_tcam) * n;
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rc = cudbg_get_buff(dbg_buff, size, &temp_buff);
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if (rc)
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return rc;
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tcam = (struct cudbg_mps_tcam *)temp_buff.data;
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for (i = 0; i < n; i++) {
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rc = cudbg_collect_tcam_index(padap, tcam, i);
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if (rc) {
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cudbg_err->sys_err = rc;
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cudbg_put_buff(&temp_buff, dbg_buff);
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return rc;
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}
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total_size += sizeof(struct cudbg_mps_tcam);
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tcam++;
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}
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if (!total_size) {
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rc = CUDBG_SYSTEM_ERROR;
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cudbg_err->sys_err = rc;
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cudbg_put_buff(&temp_buff, dbg_buff);
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return rc;
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}
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cudbg_write_and_release_buff(&temp_buff, dbg_buff);
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return rc;
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}
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int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err)
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@ -111,6 +111,9 @@ int cudbg_collect_pm_indirect(struct cudbg_init *pdbg_init,
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int cudbg_collect_tid(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_mps_tcam(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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int cudbg_collect_ma_indirect(struct cudbg_init *pdbg_init,
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struct cudbg_buffer *dbg_buff,
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struct cudbg_error *cudbg_err);
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@ -56,6 +56,7 @@ static const struct cxgb4_collect_entity cxgb4_collect_hw_dump[] = {
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{ CUDBG_PCIE_INDIRECT, cudbg_collect_pcie_indirect },
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{ CUDBG_PM_INDIRECT, cudbg_collect_pm_indirect },
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{ CUDBG_TID_INFO, cudbg_collect_tid },
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{ CUDBG_MPS_TCAM, cudbg_collect_mps_tcam },
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{ CUDBG_MA_INDIRECT, cudbg_collect_ma_indirect },
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{ CUDBG_ULPTX_LA, cudbg_collect_ulptx_la },
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{ CUDBG_UP_CIM_INDIRECT, cudbg_collect_up_cim_indirect },
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@ -196,6 +197,10 @@ static u32 cxgb4_get_entity_length(struct adapter *adap, u32 entity)
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case CUDBG_TID_INFO:
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len = sizeof(struct cudbg_tid_info_region_rev1);
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break;
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case CUDBG_MPS_TCAM:
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len = sizeof(struct cudbg_mps_tcam) *
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adap->params.arch.mps_tcam_size;
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break;
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case CUDBG_MA_INDIRECT:
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if (CHELSIO_CHIP_VERSION(adap->params.chip) > CHELSIO_T5) {
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n = sizeof(t6_ma_ireg_array) /
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@ -2439,6 +2439,18 @@
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#define MPS_CLS_TCAM_DATA0_A 0xf000
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#define MPS_CLS_TCAM_DATA1_A 0xf004
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#define CTLREQID_S 30
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#define CTLREQID_V(x) ((x) << CTLREQID_S)
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#define MPS_VF_RPLCT_MAP0_A 0x1111c
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#define MPS_VF_RPLCT_MAP1_A 0x11120
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#define MPS_VF_RPLCT_MAP2_A 0x11124
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#define MPS_VF_RPLCT_MAP3_A 0x11128
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#define MPS_VF_RPLCT_MAP4_A 0x11300
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#define MPS_VF_RPLCT_MAP5_A 0x11304
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#define MPS_VF_RPLCT_MAP6_A 0x11308
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#define MPS_VF_RPLCT_MAP7_A 0x1130c
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#define VIDL_S 16
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#define VIDL_M 0xffffU
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#define VIDL_G(x) (((x) >> VIDL_S) & VIDL_M)
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@ -2463,6 +2475,10 @@
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#define DATAVIDH1_M 0x7fU
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#define DATAVIDH1_G(x) (((x) >> DATAVIDH1_S) & DATAVIDH1_M)
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#define MPS_CLS_TCAM_RDATA0_REQ_ID1_A 0xf020
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#define MPS_CLS_TCAM_RDATA1_REQ_ID1_A 0xf024
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#define MPS_CLS_TCAM_RDATA2_REQ_ID1_A 0xf028
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#define USED_S 16
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#define USED_M 0x7ffU
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#define USED_G(x) (((x) >> USED_S) & USED_M)
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