p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity

powerpc/mm: Delete booke bits from book3s 

We also move __ASSEMBLY__ towards the end of header. This avoid
having #ifndef __ASSEMBLY___ all over the header

Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Aneesh Kumar K.V <aneesh.kumar@linux.vnet.ibm.com>
Signed-off-by: Michael Ellerman <mpe@ellerman.id.au>
This commit is contained in:
Aneesh Kumar K.V 2015-12-01 09:06:31 +05:30 committed by Michael Ellerman
parent ab537dca2f
commit cbbb8683fb
3 changed files with 47 additions and 129 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

89
arch/powerpc/include/asm/book3s/32/pgtable.h
View File

@ -3,18 +3,10 @@
#include <asm-generic/pgtable-nopmd.h> #include <asm-generic/pgtable-nopmd.h>
#ifndef __ASSEMBLY__ #include <asm/book3s/32/hash.h>
#include <linux/sched.h>
#include <linux/threads.h>
#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
extern unsigned long ioremap_bot; /* And here we include common definitions */
#include <asm/pte-common.h>
#ifdef CONFIG_44x
extern int icache_44x_need_flush;
#endif
#endif /* __ASSEMBLY__ */
/* /*
* The normal case is that PTEs are 32-bits and we have a 1-page * The normal case is that PTEs are 32-bits and we have a 1-page
@ -31,28 +23,11 @@ extern int icache_44x_need_flush;
#define PGDIR_SIZE (1UL << PGDIR_SHIFT) #define PGDIR_SIZE (1UL << PGDIR_SHIFT)
#define PGDIR_MASK (~(PGDIR_SIZE-1)) #define PGDIR_MASK (~(PGDIR_SIZE-1))
/*
* entries per page directory level: our page-table tree is two-level, so
* we don't really have any PMD directory.
*/
#ifndef __ASSEMBLY__
#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
#endif /* __ASSEMBLY__ */
#define PTRS_PER_PTE (1 << PTE_SHIFT) #define PTRS_PER_PTE (1 << PTE_SHIFT)
#define PTRS_PER_PMD 1 #define PTRS_PER_PMD 1
#define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT)) #define PTRS_PER_PGD (1 << (32 - PGDIR_SHIFT))
#define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE) #define USER_PTRS_PER_PGD (TASK_SIZE / PGDIR_SIZE)
#define FIRST_USER_ADDRESS 0UL
#define pte_ERROR(e) \
pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
(unsigned long long)pte_val(e))
#define pgd_ERROR(e) \
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
/* /*
* This is the bottom of the PKMAP area with HIGHMEM or an arbitrary * This is the bottom of the PKMAP area with HIGHMEM or an arbitrary
* value (for now) on others, from where we can start layout kernel * value (for now) on others, from where we can start layout kernel
@ -100,30 +75,30 @@ extern int icache_44x_need_flush;
#endif #endif
#define VMALLOC_END ioremap_bot #define VMALLOC_END ioremap_bot
#ifndef __ASSEMBLY__
#include <linux/sched.h>
#include <linux/threads.h>
#include <asm/io.h> /* For sub-arch specific PPC_PIN_SIZE */
extern unsigned long ioremap_bot;
/*
* entries per page directory level: our page-table tree is two-level, so
* we don't really have any PMD directory.
*/
#define PTE_TABLE_SIZE (sizeof(pte_t) << PTE_SHIFT)
#define PGD_TABLE_SIZE (sizeof(pgd_t) << (32 - PGDIR_SHIFT))
#define pte_ERROR(e) \
pr_err("%s:%d: bad pte %llx.\n", __FILE__, __LINE__, \
(unsigned long long)pte_val(e))
#define pgd_ERROR(e) \
pr_err("%s:%d: bad pgd %08lx.\n", __FILE__, __LINE__, pgd_val(e))
/* /*
* Bits in a linux-style PTE. These match the bits in the * Bits in a linux-style PTE. These match the bits in the
* (hardware-defined) PowerPC PTE as closely as possible. * (hardware-defined) PowerPC PTE as closely as possible.
*/ */
#if defined(CONFIG_40x)
#include <asm/pte-40x.h>
#elif defined(CONFIG_44x)
#include <asm/pte-44x.h>
#elif defined(CONFIG_FSL_BOOKE) && defined(CONFIG_PTE_64BIT)
#include <asm/pte-book3e.h>
#elif defined(CONFIG_FSL_BOOKE)
#include <asm/pte-fsl-booke.h>
#elif defined(CONFIG_8xx)
#include <asm/pte-8xx.h>
#else /* CONFIG_6xx */
#include <asm/book3s/32/hash.h>
#endif
/* And here we include common definitions */
#include <asm/pte-common.h>
#ifndef __ASSEMBLY__
#define pte_clear(mm, addr, ptep) \ #define pte_clear(mm, addr, ptep) \
do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0) do { pte_update(ptep, ~_PAGE_HASHPTE, 0); } while (0)
@ -167,7 +142,6 @@ static inline unsigned long pte_update(pte_t *p,
unsigned long clr, unsigned long clr,
unsigned long set) unsigned long set)
{ {
#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp; unsigned long old, tmp;
__asm__ __volatile__("\ __asm__ __volatile__("\
@ -180,15 +154,7 @@ static inline unsigned long pte_update(pte_t *p,
: "=&r" (old), "=&r" (tmp), "=m" (*p) : "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" (clr), "r" (set), "m" (*p) : "r" (p), "r" (clr), "r" (set), "m" (*p)
: "cc" ); : "cc" );
#else /* PTE_ATOMIC_UPDATES */
unsigned long old = pte_val(*p);
*p = __pte((old & ~clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
icache_44x_need_flush = 1;
#endif
return old; return old;
} }
#else /* CONFIG_PTE_64BIT */ #else /* CONFIG_PTE_64BIT */
@ -196,7 +162,6 @@ static inline unsigned long long pte_update(pte_t *p,
unsigned long clr, unsigned long clr,
unsigned long set) unsigned long set)
{ {
#ifdef PTE_ATOMIC_UPDATES
unsigned long long old; unsigned long long old;
unsigned long tmp; unsigned long tmp;
@ -211,15 +176,7 @@ static inline unsigned long long pte_update(pte_t *p,
: "=&r" (old), "=&r" (tmp), "=m" (*p) : "=&r" (old), "=&r" (tmp), "=m" (*p)
: "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p) : "r" (p), "r" ((unsigned long)(p) + 4), "r" (clr), "r" (set), "m" (*p)
: "cc" ); : "cc" );
#else /* PTE_ATOMIC_UPDATES */
unsigned long long old = pte_val(*p);
*p = __pte((old & ~(unsigned long long)clr) | set);
#endif /* !PTE_ATOMIC_UPDATES */
#ifdef CONFIG_44x
if ((old & _PAGE_USER) && (old & _PAGE_EXEC))
icache_44x_need_flush = 1;
#endif
return old; return old;
} }
#endif /* CONFIG_PTE_64BIT */ #endif /* CONFIG_PTE_64BIT */
@ -233,12 +190,10 @@ static inline int __ptep_test_and_clear_young(unsigned int context, unsigned lon
{ {
unsigned long old; unsigned long old;
old = pte_update(ptep, _PAGE_ACCESSED, 0); old = pte_update(ptep, _PAGE_ACCESSED, 0);
#if _PAGE_HASHPTE != 0
if (old & _PAGE_HASHPTE) { if (old & _PAGE_HASHPTE) {
unsigned long ptephys = __pa(ptep) & PAGE_MASK; unsigned long ptephys = __pa(ptep) & PAGE_MASK;
flush_hash_pages(context, addr, ptephys, 1); flush_hash_pages(context, addr, ptephys, 1);
} }
#endif
return (old & _PAGE_ACCESSED) != 0; return (old & _PAGE_ACCESSED) != 0;
} }
#define ptep_test_and_clear_young(__vma, __addr, __ptep) \ #define ptep_test_and_clear_young(__vma, __addr, __ptep) \

84
arch/powerpc/include/asm/book3s/64/pgtable.h
View File

@ -8,7 +8,6 @@
#include <asm/book3s/64/hash.h> #include <asm/book3s/64/hash.h>
#include <asm/barrier.h> #include <asm/barrier.h>
#define FIRST_USER_ADDRESS 0UL
/* /*
* Size of EA range mapped by our pagetables. * Size of EA range mapped by our pagetables.
@ -25,27 +24,16 @@
/* /*
* Define the address range of the kernel non-linear virtual area * Define the address range of the kernel non-linear virtual area
*/ */
#ifdef CONFIG_PPC_BOOK3E
#define KERN_VIRT_START ASM_CONST(0x8000000000000000)
#else
#define KERN_VIRT_START ASM_CONST(0xD000000000000000) #define KERN_VIRT_START ASM_CONST(0xD000000000000000)
#endif
#define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000) #define KERN_VIRT_SIZE ASM_CONST(0x0000100000000000)
/* /*
* The vmalloc space starts at the beginning of that region, and * The vmalloc space starts at the beginning of that region, and
* occupies half of it on hash CPUs and a quarter of it on Book3E * occupies half of it on hash CPUs and a quarter of it on Book3E
* (we keep a quarter for the virtual memmap) * (we keep a quarter for the virtual memmap)
*/ */
#define VMALLOC_START KERN_VIRT_START #define VMALLOC_START KERN_VIRT_START
#ifdef CONFIG_PPC_BOOK3E
#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 2)
#else
#define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1) #define VMALLOC_SIZE (KERN_VIRT_SIZE >> 1)
#endif
#define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE) #define VMALLOC_END (VMALLOC_START + VMALLOC_SIZE)
/* /*
* The second half of the kernel virtual space is used for IO mappings, * The second half of the kernel virtual space is used for IO mappings,
* it's itself carved into the PIO region (ISA and PHB IO space) and * it's itself carved into the PIO region (ISA and PHB IO space) and
@ -64,7 +52,6 @@
#define IOREMAP_BASE (PHB_IO_END) #define IOREMAP_BASE (PHB_IO_END)
#define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE) #define IOREMAP_END (KERN_VIRT_START + KERN_VIRT_SIZE)
/* /*
* Region IDs * Region IDs
*/ */
@ -79,32 +66,39 @@
/* /*
* Defines the address of the vmemap area, in its own region on * Defines the address of the vmemap area, in its own region on
* hash table CPUs and after the vmalloc space on Book3E * hash table CPUs.
*/ */
#ifdef CONFIG_PPC_BOOK3E
#define VMEMMAP_BASE VMALLOC_END
#define VMEMMAP_END KERN_IO_START
#else
#define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT) #define VMEMMAP_BASE (VMEMMAP_REGION_ID << REGION_SHIFT)
#endif
#define vmemmap ((struct page *)VMEMMAP_BASE) #define vmemmap ((struct page *)VMEMMAP_BASE)
/*
* Include the PTE bits definitions
*/
#ifdef CONFIG_PPC_BOOK3S
#include <asm/book3s/64/hash.h>
#else
#include <asm/pte-book3e.h>
#endif
#include <asm/pte-common.h>
#ifdef CONFIG_PPC_MM_SLICES #ifdef CONFIG_PPC_MM_SLICES
#define HAVE_ARCH_UNMAPPED_AREA #define HAVE_ARCH_UNMAPPED_AREA
#define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN #define HAVE_ARCH_UNMAPPED_AREA_TOPDOWN
#endif /* CONFIG_PPC_MM_SLICES */ #endif /* CONFIG_PPC_MM_SLICES */
/*
* THP pages can't be special. So use the _PAGE_SPECIAL
*/
#define _PAGE_SPLITTING _PAGE_SPECIAL
/*
* We need to differentiate between explicit huge page and THP huge
* page, since THP huge page also need to track real subpage details
*/
#define _PAGE_THP_HUGE _PAGE_4K_PFN
/*
* set of bits not changed in pmd_modify.
*/
#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \
_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
_PAGE_THP_HUGE)
/*
* Default defines for things which we don't use.
* We should get this removed.
*/
#include <asm/pte-common.h>
#ifndef __ASSEMBLY__ #ifndef __ASSEMBLY__
/* /*
@ -206,7 +200,6 @@ static inline unsigned long pte_update(struct mm_struct *mm,
unsigned long set, unsigned long set,
int huge) int huge)
{ {
#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp; unsigned long old, tmp;
__asm__ __volatile__( __asm__ __volatile__(
@ -220,18 +213,12 @@ static inline unsigned long pte_update(struct mm_struct *mm,
: "=&r" (old), "=&r" (tmp), "=m" (*ptep) : "=&r" (old), "=&r" (tmp), "=m" (*ptep)
: "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set) : "r" (ptep), "r" (clr), "m" (*ptep), "i" (_PAGE_BUSY), "r" (set)
: "cc" ); : "cc" );
#else
unsigned long old = pte_val(*ptep);
*ptep = __pte((old & ~clr) | set);
#endif
/* huge pages use the old page table lock */ /* huge pages use the old page table lock */
if (!huge) if (!huge)
assert_pte_locked(mm, addr); assert_pte_locked(mm, addr);
#ifdef CONFIG_PPC_STD_MMU_64
if (old & _PAGE_HASHPTE) if (old & _PAGE_HASHPTE)
hpte_need_flush(mm, addr, ptep, old, huge); hpte_need_flush(mm, addr, ptep, old, huge);
#endif
return old; return old;
} }
@ -313,7 +300,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
unsigned long bits = pte_val(entry) & unsigned long bits = pte_val(entry) &
(_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC); (_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_RW | _PAGE_EXEC);
#ifdef PTE_ATOMIC_UPDATES
unsigned long old, tmp; unsigned long old, tmp;
__asm__ __volatile__( __asm__ __volatile__(
@ -326,10 +312,6 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
:"=&r" (old), "=&r" (tmp), "=m" (*ptep) :"=&r" (old), "=&r" (tmp), "=m" (*ptep)
:"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY) :"r" (bits), "r" (ptep), "m" (*ptep), "i" (_PAGE_BUSY)
:"cc"); :"cc");
#else
unsigned long old = pte_val(*ptep);
*ptep = __pte(old | bits);
#endif
} }
#define __HAVE_ARCH_PTE_SAME #define __HAVE_ARCH_PTE_SAME
@ -367,27 +349,7 @@ static inline void __ptep_set_access_flags(pte_t *ptep, pte_t entry)
void pgtable_cache_add(unsigned shift, void (*ctor)(void *)); void pgtable_cache_add(unsigned shift, void (*ctor)(void *));
void pgtable_cache_init(void); void pgtable_cache_init(void);
#endif /* __ASSEMBLY__ */
/*
* THP pages can't be special. So use the _PAGE_SPECIAL
*/
#define _PAGE_SPLITTING _PAGE_SPECIAL
/*
* We need to differentiate between explicit huge page and THP huge
* page, since THP huge page also need to track real subpage details
*/
#define _PAGE_THP_HUGE _PAGE_4K_PFN
/*
* set of bits not changed in pmd_modify.
*/
#define _HPAGE_CHG_MASK (PTE_RPN_MASK | _PAGE_HPTEFLAGS | \
_PAGE_DIRTY | _PAGE_ACCESSED | _PAGE_SPLITTING | \
_PAGE_THP_HUGE)
#ifndef __ASSEMBLY__
/* /*
* The linux hugepage PMD now include the pmd entries followed by the address * The linux hugepage PMD now include the pmd entries followed by the address
* to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits. * to the stashed pgtable_t. The stashed pgtable_t contains the hpte bits.

1
arch/powerpc/include/asm/book3s/pgtable.h
View File

@ -7,4 +7,5 @@
#include <asm/book3s/32/pgtable.h> #include <asm/book3s/32/pgtable.h>
#endif #endif
#define FIRST_USER_ADDRESS 0UL
#endif #endif