ARM: shmobile: r8a7794: Add MMP and VSP1 clocks to device tree
Signed-off-by: Yoshifumi Hosoya <yoshifumi.hosoya.wj@renesas.com> Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
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@ -461,15 +461,19 @@ mstp0_clks: mstp0_clks@e6150130 {
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mstp1_clks: mstp1_clks@e6150134 {
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compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
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reg = <0 0xe6150134 0 4>, <0 0xe6150038 0 4>;
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clocks = <&p_clk>, <&zg_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>,
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<&cp_clk>, <&zs_clk>, <&zs_clk>, <&zs_clk>;
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clocks = <&zs_clk>, <&zs_clk>, <&p_clk>, <&zg_clk>, <&zs_clk>,
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<&zs_clk>, <&p_clk>, <&p_clk>, <&rclk_clk>, <&cp_clk>,
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<&zs_clk>, <&zs_clk>;
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#clock-cells = <1>;
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renesas,clock-indices = <
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R8A7794_CLK_TMU1 R8A7794_CLK_3DG R8A7794_CLK_TMU3
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R8A7794_CLK_TMU2 R8A7794_CLK_CMT0 R8A7794_CLK_TMU0
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R8A7794_CLK_VCP0 R8A7794_CLK_VPC0 R8A7794_CLK_TMU1
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R8A7794_CLK_3DG R8A7794_CLK_2DDMAC R8A7794_CLK_FDP1_0
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R8A7794_CLK_TMU3 R8A7794_CLK_TMU2 R8A7794_CLK_CMT0
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R8A7794_CLK_TMU0 R8A7794_CLK_VSP1_DU0 R8A7794_CLK_VSP1_S
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>;
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clock-output-names =
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"tmu1", "3dg", "tmu3", "tmu2", "cmt0", "tmu0";
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"vcp0", "vpc0", "tmu1", "3dg", "2ddmac", "fdp1-0",
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"tmu3", "tmu2", "cmt0", "tmu0", "vsp1-du0", "vsps";
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};
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mstp2_clks: mstp2_clks@e6150138 {
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compatible = "renesas,r8a7794-mstp-clocks", "renesas,cpg-mstp-clocks";
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@ -26,12 +26,18 @@
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#define R8A7794_CLK_MSIOF0 0
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/* MSTP1 */
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#define R8A7794_CLK_VCP0 1
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#define R8A7794_CLK_VPC0 3
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#define R8A7794_CLK_TMU1 11
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#define R8A7794_CLK_3DG 12
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#define R8A7794_CLK_2DDMAC 15
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#define R8A7794_CLK_FDP1_0 19
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#define R8A7794_CLK_TMU3 21
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#define R8A7794_CLK_TMU2 22
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#define R8A7794_CLK_CMT0 24
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#define R8A7794_CLK_TMU0 25
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#define R8A7794_CLK_VSP1_DU0 28
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#define R8A7794_CLK_VSP1_S 31
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/* MSTP2 */
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#define R8A7794_CLK_SCIFA2 2
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