Commit Graph

46283 Commits

Author SHA1 Message Date
Alex Deucher 2b6dc93a3d drm/amdgpu/display: remove VEGAM config option
Leftover from bringup.  No need to keep it around for
upstream.

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:18 -05:00
Andrey Grodzovsky 563e1e664d drm/scheduler: Remove obsolete spinlock.
This spinlock is superfluous, any call to drm_sched_entity_push_job
should already be under a lock together with matching drm_sched_job_init
to match the order of insertion into queue with job's fence seqence
number.

v2:
Improve patch description.
Add functions documentation describing the locking considerations

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Acked-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:17 -05:00
Christian König b9245b9498 drm/amdgpu: remove unused member
This lock isn't used any more.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:17 -05:00
Rex Zhu 01233b8073 drm/amd/pp: Workaround flickering issue on RV
Screen flickering observed while running 1080p video using
MPV_VAAPI/VDPAU with 4x4K@60 monitors

Need to set higher mclk in this configuration.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:17 -05:00
Andrey Grodzovsky 20b6b7885d drm/amdgpu: Skip drm_sched_entity related ops for KIQ ring.
Following change 75fbed2 we never initialize or use the GPU
scheduler for KIQ and hence we need to skip KIQ ring when iterating
amdgpu_ctx's scheduler entites.

Signed-off-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:16 -05:00
Alex Deucher 950f23ebdc drm/amdgpu: flag Vega20 as experimental
Must set amdgpu.exp_hw_support=1 on the kernel command line in
grub to enable support.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:16 -05:00
Feifei Xu 1204a26e03 drm/amdgpu: Add vega20 pci ids
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:16 -05:00
Feifei Xu 698758bbb3 drm/amdgpu: Switch to use df_v3_6_funcs for vega20 (v2)
v2: fix whitespace (Alex)

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:15 -05:00
Feifei Xu 13b581502d drm/amdgpu/df: implement df v3_6 callback functions (v2)
New df helpers for 3.6.

v2: switch to using df 3.6 headers (Alex)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:15 -05:00
Alex Deucher 9883e9d751 drm/amdgpu: add df 3.6 headers
Needed for vega20.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:15 -05:00
James Zhu 705e98d77b drm/amdgpu/vg20:Enable UVD/VCE for Vega20
Vega20 ucode load type is set to AMDGPU_FW_LOAD_DIRECT for default.
So UVD/VCE needn't PSP IP block up. UVD/VCE for Vega20 can be enabled
at this moment.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:14 -05:00
James Zhu 04305acb9f drm/amdgpu/vg20:Enable 2nd instance queue maping for uvd 7.2
Enable 2nd instance uvd queue maping for uvd 7.2. For user, only one UVD
instance presents. there is two rings for uvd decode, and
4 rings for uvd encode.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:14 -05:00
James Zhu b53a6ebcc5 drm/amdgpu/vg20:Enable the 2nd instance IRQ for uvd 7.2
For Vega20, the 2nd instance uvd IRQ using different client id.
Enable the 2nd instance IRQ for uvd 7.2

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:13 -05:00
James Zhu 915893fd2b drm/amdgpu/vg20:Add IH client ID for the 2nd UVD
For Vega20, there are two UVD hardware. Need add
the 2nd IH client ID for the 2nd UVD Hardware.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:13 -05:00
James Zhu 9181dba670 drm/amdgpu/vg20:Enable the 2nd instance for uvd
For Vega20, set num of uvd instance to 2, to enble 2nd instance.
The IB test build-in registers need update for vega20 2nd instance.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:13 -05:00
James Zhu 3b17c62285 drm/amdgpu/vg20:increase 3 rings for AMDGPU_MAX_RINGS
For Vega20, there are two UVD Hardware. One more UVD hardware
adds one decode ring and two encode rings. So AMDGPU_MAX_RINGS
need increase by 3.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:12 -05:00
James Zhu 10dd74eac4 drm/amdgpu/vg20:Restruct uvd.inst to support multiple instances
Vega20 has dual-UVD. Need add multiple instances support for uvd.
Restruct uvd.inst, using uvd.inst[0] to replace uvd.inst->.
Repurpose amdgpu_ring::me for instance index, and initialize to 0.
There are no any logical changes here.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:12 -05:00
James Zhu 2bb795f5ba drm/amdgpu/vg20:Restruct uvd to support multiple uvds
Vega20 has dual-UVD. Need Restruct amdgpu_device::uvd to support
multiple uvds. There are no any logical changes here.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:12 -05:00
Feifei Xu 602ed6c69b drm/amdgpu: Disable ip modules that are not ready yet
Please enable above ips on soc15.c when they're available.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:11 -05:00
Evan Quan 3fdbab5f56 drm/amd/powerplay: update vega20 cg flags (v2)
v2: remove duplicate flag.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-18 16:08:11 -05:00
Thierry Reding acae8a9d05 drm/tegra: vic: Track interface version
Set the interface version implemented by the VIC module. This allows
userspace to pass the correct command stream when programming the VIC
module.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 22:00:41 +02:00
Thierry Reding 33f150ea82 drm/tegra: gr3d: Track interface version
Set the interface version implemented by the gr3d module. This allows
userspace to pass the correct command stream when programming the gr3d
module.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 22:00:25 +02:00
Thierry Reding 840fd213fc drm/tegra: gr2d: Track interface version
Set the interface version implemented by the gr2d module. This allows
userspace to pass the correct command stream when programming the gr2d
module.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 22:00:13 +02:00
Thierry Reding f3b3cfcc3f drm/tegra: Track client version
Userspace needs to know the version of the interface implemented by a
client so it can create the proper command streams. Allow individual
drivers to store this version along with the client so that it can be
returned to userspace upon opening a channel.

Acked-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:59:51 +02:00
Thierry Reding 995c5a509f drm/tegra: dc: Support rotation property
Currently only the DRM_MODE_REFLECT_Y rotation is supported. The driver
already supports reflection on the Y axis via a custom flag which is not
very useful because it requires custom userspace. Add the standard
rotation property that supports 0 degree rotation and Y axis reflection
for primary and overlay planes to provide a better interface than the
custom flag.

v2: keep custom flag for ABI compatibility (Dmitry)

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:56:21 +02:00
Thierry Reding 4bd91a5b5d drm/tegra: gem: Fill in missing export info
Set the owner and name of the exported DMA-BUF in addition to the
already filled-in fields.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:52:19 +02:00
Thierry Reding 326bbd79fd gpu: host1x: Use not explicitly sized types
The number of words and the offset in a gather don't need to be
explicitly sized, so make them unsigned int instead.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:51:37 +02:00
Thierry Reding 06490bb99e gpu: host1x: Rename relocarray -> relocs for consistency
All other array variables use a plural, and this is the only one using
the *array suffix. This is confusing, so rename it for consistency.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:51:25 +02:00
Thierry Reding ac330f45c7 gpu: host1x: Drop unnecessary host1x argument
Functions taking a pointer to a host1x syncpoint as an argument don't
need to specify a pointer to a host1x instance because it can be
obtained from the syncpoint.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:51:01 +02:00
Thierry Reding d4ad3ad9b8 gpu: host1x: Cleanup loop variable usage
Use unsigned int where possible and don't unnecessarily initialize the
loop variable.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:50:40 +02:00
Thierry Reding bf3d41ccab gpu: host1x: Store pointer to client in jobs
Rather than storing some identifier derived from the application
context that can't be used concretely anywhere, store a pointer to the
client directly so that accesses can be made directly through that
client object.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:50:24 +02:00
Thierry Reding 24c94e166d gpu: host1x: Remove wait check support
The job submission userspace ABI doesn't support this and there are no
plans to implement it, so all of this code is dead and can be removed.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 21:50:04 +02:00
Oded Gabbay fcdfa432a5 drm/amdgpu: conditionally compile amdgpu's amdkfd files
In case CONFIG_HSA_AMD is not chosen, there is no need to compile amdkfd
files that reside inside amdgpu dirver. In addition, because amdkfd
depends on x86_64 architecture and amdgpu is not, compiling amdkfd files
under i386 architecture can cause compiler errors and warnings.

This patch modifies amdgpu's makefile to build amdkfd files only if
CONFIG_HSA_AMD is chosen. The only file to be compiled unconditionally
is amdgpu_amdkfd.c

There are stub functions that are compiled only if amdkfd is not
compiled. In that case, calls from amdgpu driver proper will go to those
functions instead of the real functions.

v2: instead of using function pointers, use stub functions

v3: initialize kgd2kfd to NULL in case amdkfd is not compiled

Reviewed-by: Felix Kuehling <Felix.Kuehling@amd.com>
Signed-off-by: Oded Gabbay <oded.gabbay@gmail.com>
2018-05-18 22:18:16 +03:00
Lucas Stach f6ffbd4fc1 drm/etnaviv: replace license text with SPDX tags
This replaces the repetitive GPL-2.0 license text in code and header files
with the SPDX tags. Generated hardware headers aren't changed, as any changes
there need to be done in the upstream rnndb repository.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-05-18 15:27:56 +02:00
Lucas Stach 931e97f3af drm/etnaviv: mmuv2: support 40 bit phys address
MMUv2 supports up to 40 bits of physical address by folding the upper
8 bits into bits [4:11] of the PTE.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18 15:27:56 +02:00
Lucas Stach a1fb6f204f drm/etnaviv: mmuv2: allocate 2nd level page tables on demand
With etnaviv not being tied into the IOMMU framework anymore, the MMU
functions will only be called under sleeping locks. Thus we are able
to allocate the memory for the 2nd level page tables on demand without
having to deal with memory allocation in atomic context.

This speeds up driver intitialization on MMUv2 GPU cores, as we don't
need to preallocate all the page table memory and also reduces memory
consumption for most workloads, as most of them won't use the full
GPU virtual address space.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-05-18 15:27:56 +02:00
Lucas Stach 1af998b27c drm/etnaviv: switch MMU page tables to writecombine memory
We are likely to write multiple page entries at once and already ensure
proper write buffer flushing before GPU submit, so this improves CPU
time usage in the submit path without any downsides.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Philipp Zabel <p.zabel@pengutronix.de>
2018-05-18 15:27:56 +02:00
Lucas Stach a98b1e7808 drm/etnaviv: remove register logging
I'm not aware of any case where tracing GPU register manipulation at the
kernel level would have been useful. It only adds more indirections and
adds to the code size.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian Gmeiner <christian.gmeiner@gmail.com>
2018-05-18 15:27:56 +02:00
Lucas Stach ccae45928f drm/etnaviv: remove cycling through MMU address space
This was useful on MMUv1 GPUs, which don't generate proper faults,
when the GPU write caches weren't fully understood and not properly
handled by the kernel driver. As this has been fixed for quite some
time, the cycling though the MMU address space needlessly spreads
out the MMU mappings.

Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18 15:27:56 +02:00
Russell King d066b246d4 drm/etnaviv: correct timeout calculation
The old way did clamp the jiffy conversion and thus caused the timeouts
to become negative after some time. Also it didn't work with userspace
which actually fills the upper 32bits of the 64bit timestamp value.

clock_gettime() is 32-bit on 32-bit architectures. Using 64-bit timespec
math, like we do in this commit, means that when a wrap occurs, the
specified timeout goes into the past and we can't request a timeout in
the future. As the Linux implementation of CLOCK_MONOTONIC is reasonable
and starts at 0, the first such timer wrap will occur after approx. 68
years of system uptime.

Signed-off-by: Russell King <rmk+kernel@armlinux.org.uk>
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
2018-05-18 15:27:56 +02:00
Emil Goode 2f8a6da866 gpu: host1x: Fix compiler errors by converting to dma_addr_t
The compiler is complaining with the following errors:

drivers/gpu/host1x/cdma.c:94:48: error:
	passing argument 3 of ‘dma_alloc_wc’ from incompatible pointer type
	[-Werror=incompatible-pointer-types]

drivers/gpu/host1x/cdma.c:113:48: error:
	passing argument 3 of ‘dma_alloc_wc’ from incompatible pointer type
	[-Werror=incompatible-pointer-types]

The expected pointer type of the third argument to dma_alloc_wc() is
dma_addr_t but phys_addr_t is passed.

Change the phys member of struct push_buffer to be dma_addr_t so that we
pass the correct type to dma_alloc_wc().
Also check pb->mapped for non-NULL in the destroy function as that is the
right way of checking if dma_alloc_wc() was successful.

Signed-off-by: Emil Goode <emil.fsw@goode.io>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-18 11:23:48 +02:00
Ben Skeggs 6c46d01f25 drm/nouveau/gr/gf100-: insert some WFIs during gr init
Inserted wait-for-gr-idle in the places it seems that RM does it, seems
to prevent some random mmio timeouts on Quadro GV100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 17:09:35 +10:00
Arushi Singhal dd3b89be3e drm/nouveau/clk: Use list_for_each_entry_from_reverse
It's better to use "list_for_each_entry_from_reverse" for iterating list
than "for loop" as it makes the code more clear to read.
This patch replace "for loop" with "list_for_each_entry_from_reverse"
and "start" variable with "cstate" which helps in refactoring
the code and also "cstate" variable is more commonly used in the other
functions.

changes in v2:
"start" variable is removed, before "cstate" variable was removed
but "cstate" is more common so preferred "cstate" over "start".

Signed-off-by: Arushi Singhal <arushisinghal19971997@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 17:09:35 +10:00
Ilia Mirkin 7a22c737fa drm/nouveau: fix temp/pwm visibility, skip hwmon when no sensors exist
A NV34 GPU was seeing temp and pwm entries in hwmon, which would error
out when read. These should not have been visible, but also the whole
hwmon object should just not have been registered in the first place.

Signed-off-by: Ilia Mirkin <imirkin@alum.mit.edu>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 17:09:48 +10:00
Luc Van Oostenryck f43cda5c76 drm/nouveau: fix nouveau_dsm_get_client_id()'s return type
The method struct vga_switcheroo_handler::get_client_id() is defined
as returning an 'enum vga_switcheroo_client_id' but the implementation
in this driver, nouveau_dsm_get_client_id(), returns an 'int'.

Fix this by returning 'enum vga_switcheroo_client_id' in this driver too.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 17:09:46 +10:00
Luc Van Oostenryck 54b202f1d8 drm/nouveau: fix mode_valid's return type
The method struct drm_connector_helper_funcs::mode_valid is defined
as returning an 'enum drm_mode_status' but the driver implementation
for this method uses an 'int' for it.

Fix this by using 'enum drm_mode_status' in the driver too.

Signed-off-by: Luc Van Oostenryck <luc.vanoostenryck@gmail.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 17:09:35 +10:00
Ben Skeggs d521097f58 drm/nouveau/gr/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:47 +10:00
Ben Skeggs 6e1f34e33c drm/nouveau/ce/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 37e1c45a58 drm/nouveau/fifo/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs facaed62b4 drm/nouveau/kms/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:46 +10:00
Ben Skeggs 290ffeafcc drm/nouveau/disp/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:43 +10:00
Ben Skeggs 6fb566b913 drm/nouveau/dma/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:39 +10:00
Ben Skeggs 24a7513c10 drm/nouveau/therm/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:39 +10:00
Ben Skeggs ada0c56281 drm/nouveau/pmu/gv100: initial support
Appears to be compatible with GP102.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:39 +10:00
Ben Skeggs 8b811951c6 drm/nouveau/fault/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:38 +10:00
Ben Skeggs 013b7b3773 drm/nouveau/bar/gv100: initial support
Appears to be compatible with GM107.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:38 +10:00
Ben Skeggs edf50395c7 drm/nouveau/mmu/gv100: initial support
VEID support hacked in here, as it's the most convenient place for now.

Will be refined once it's better understood.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:38 +10:00
Ben Skeggs 1bce57250a drm/nouveau/ltc/gv100: initial support
Appears to be compatible with GP102.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:38 +10:00
Ben Skeggs 3582942c28 drm/nouveau/fb/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs a4a0cfb642 drm/nouveau/imem/gv100: initial support
Can't imagine this will be any different.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 936240c9bb drm/nouveau/tmr/gv100: initial support
Appears to be compatible with GK20A.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 9506bd2407 drm/nouveau/bus/gv100: initial support
Appears to be compatible with GF100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 41af75bd35 drm/nouveau/mc/gv100: initial support
Appears to be compatible with GP100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 292550499a drm/nouveau/fuse/gv100: initial support
Appears to be compatible with GM107.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs d2e3b57d81 drm/nouveau/i2c/gv100: initial support
Appears to be compatible with GM200.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 8afbcca549 drm/nouveau/gpio/gv100: initial support
Appears to be compatible with GK104.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 46fe1a813a drm/nouveau/ibus/gv100: initial support
Appears to be compatible with GM200.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs a1c771a5cb drm/nouveau/top/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:34 +10:00
Ben Skeggs 8769dc989c drm/nouveau/devinit/gv100: initial support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 6827c9a868 drm/nouveau/bios/pll: limits table 5.0
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 75e482efd3 drm/nouveau/bios/gv100: initial support
No real surprises here so far.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 893855d821 drm/nouveau/pci/gv100: initial support
Appears to be compatible with GP100.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs c1f856bb99 drm/nouveau/core: recognise gv100
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 890c85f3ee drm/nouveau/core: increase maximum number of copy engines to 9
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 2ce7f38629 drm/nouveau/kms/nv50-: initial overlay support
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:31 +10:00
Ben Skeggs 88b600d421 drm/nouveau/kms/gk104-: add support for [XA]2R10G10B10 formats
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:30 +10:00
Ben Skeggs 01d380ab4f drm/nouveau/kms/gk104-: support additional cursor sizes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:30 +10:00
Ben Skeggs b05d873808 drm/nouveau/kms/nv50-: separate blocklinear vs linear pitch
Will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:30 +10:00
Ben Skeggs 119608a7f3 drm/nouveau/kms/nv50-: handle degamma LUT from window channels
Required to eventually support DRM colour management APIs, and to
support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs e349a05dc8 drm/nouveau/kms/nv50-: plane updates don't always require image_set()
When only the position of a window changes, there's no need to submit
an image update as well.

Will be required to support the overlays, and Volta windows.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 859b456b6b drm/nouveau/kms/nv50-: store window visibility in state
Window visibility is going to become a little more complicated with the
upcoming LUT changes, so store the calculated value to avoid needing to
recalculate the armed state again.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 45a2945a37 drm/nouveau/kms/nv50-: simplify swap interval handling
This is just cleaning up some left-overs from when we needed a custom
legacy page flip implementation.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 04fc14be77 drm/nouveau/kms/nv50-: decouple window state changes, and update method submisssion
This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 53e0a3e70d drm/nouveau/kms/nv50-: simplify tracking of channel interlocks
Instead of windows returning their core channel interlock mask if they
know core has been modified, it's recorded unconditionally and used if
required when update methods are emitted.

This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 34508f9d26 drm/nouveau/kms/nv50-: determine MST support from DP Info Table
GV100 doesn't support MST, use the information provided in VBIOS tables to
detect its presence instead.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 261fcfa969 drm/nouveau/kms/nv50-: extend window image data for stereo/planar formats
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:29 +10:00
Ben Skeggs 43c181e9de drm/nouveau/kms/nv50-: move drm format->hw conversion into common code
This will be required to support additional HW features.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs f88bc9d3ec drm/nouveau/kms/nv50-: unify set/clr masks
This is a simplification that'll be used to improve interlock handling.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 9d6c2fe191 drm/nouveau/kms/nv50-: allow specification of valid heads for a window
This will be required to support Volta, where window ID != head.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs ccd27db8c7 drm/nouveau/kms/nv50-: split base implementation by hardware class
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 09e1b78aab drm/nouveau/kms/nv50-: split core implementation by hardware class
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 1590700d94 drm/nouveau/kms/nv50-: split each resource type into their own source files
There should be no code changes here, just shuffling stuff around.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 0a3687716b drm/nouveau/kms/nv50: abstract OR interfaces so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 2ca7fb5c1c drm/nouveau/kms/nv50: handle SetControlOutputResource from head
Removes duplicated code from OR-specific functions.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 10ffe0fad5 drm/nouveau/kms/nv50-: abstract head interfaces so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs 9ca6f1ebba drm/nouveau/kms/nv50: modify core allocation so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs d7c6e97a32 drm/nouveau/kms/nv50-: modify base allocation so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:28 +10:00
Ben Skeggs b97ace4072 drm/nouveau/kms/nv50-: modify cursor allocation so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:27 +10:00
Ben Skeggs a97c530eb9 drm/nouveau/kms/nv50-: modify overlay allocation so the code can be split
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:27 +10:00
Ben Skeggs 5bca1621c0 drm/nouveau/kms/nv50-: move fb ctxdma tracking into windows
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:27 +10:00
Ben Skeggs 62b290fc7b drm/nouveau/kms/nv50-: fix i2c-over-aux on anx9805
We don't support address-only transactions there.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:27 +10:00
Ben Skeggs 30ed49b55b drm/nouveau/kms/nv50-: move code underneath dispnv50/
The code is about to be split up, and this matches dispnv04.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 0d4a2c5767 drm/nouveau/kms: move display class instantiation to library
This function is useful outside of DRM code.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 512fa0b8a3 drm/nouveau/drm/nv50-: remove allocation of sw class
Hasn't been required for a long time.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 92b4eaaf9a drm/nouveau: no need to create ctxdma for push buffers on fermi and up
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 11e451e740 drm/nouveau: remove fence wait code from deferred client work handler
Fences attached to deferred client work items now originate from channels
belonging to the client, meaning we can be certain they've been signalled
before we destroy a client.

This closes a race that could happen if the dma_fence_wait_timeout() call
didn't succeed.  When the fence was later signalled, a use-after-free was
possible.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 470db8b781 drm/nouveau/gem: tie deferred unmapping of buffers to VMA fence completion
As VMAs are per-client, unlike buffers, this allows us to avoid referencing
foreign fences (those that belong to another client/driver) from the client
deferred work handler, and prevent some not-fun race conditions that can be
triggered when a fence stalls.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 0db912af8f drm/nouveau/gem: attach fences to VMAs to track GPU usage
An upcoming patch will use these to fix issues related to the deferred
unmapping of GEM objects.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 19ca10d82e drm/nouveau/gem: lookup VMAs for buffers referenced by pushbuf ioctl
We previously only did this for push buffers, but an upcoming patch will
need to attach fences to all VMAs to resolve another issue.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 4b2c71edf0 drm/nouveau/gr/gp102-: setup stencil zbc
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs e9d03335f6 drm/nouveau/gr/gp100-: use correct registers for zbc colour/depth setup
These were missed the first time around due to the driver version I traced
using the older registers still.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 7a058a900c drm/nouveau/gr/gp100-: fix attrib cb setup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 17f2d4df32 drm/nouveau/gr/gp100-: fix pagepool setup
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 191e323278 drm/nouveau/gr/gf100-gm10x: update register lists
There are differences on GM200 and newer too, but we can't fix them there
as they come from firmware packages.

A request has been made to NVIDIA to release updated firmware.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 6f0233329b drm/nouveau/gr/gf100-: swap bundle and pagepool
Makes it easier to diff against RM traces.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 068cae743c drm/nouveau/gr/gf100-: calculate and use sm mapping table
There's a number of places that require this data, so let's separate out
the calculations to ensure they remain consistent.

This is incorrect for GM200 and newer, but will produce the same results
as we did before.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs d00ffc0c40 drm/nouveau/gr/gf100-: port zcull tile mapping calculations from NVGPU
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 5f6474a4e6 drm/nouveau/gr/gf100-: port tile mapping calculations from NVGPU
There's also a couple of hardcoded tables for a couple of very specific
configurations that NVGPU's algorithm didn't work for.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:26 +10:00
Ben Skeggs 5c05a58985 drm/nouveau/gr/gf100-: virtualise trap_mp
Required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs 74b6068bd6 drm/nouveau/gr/gf100-: add missing reset sequence before golden context init
RM and NVGPU both have a variant of this, we probably should too.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs 201ed6f651 drm/nouveau/gr/gf100-: delete duplicated grctx init code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs a5537f980e drm/nouveau/gr/gf100-: update r408840 where required
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs 8d56fc48d3 drm/nouveau/gr/gf100-: update 419a3c where required
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs c2592adea7 drm/nouveau/gr/gf100-: virtualise r418e94
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs 18d17221dd drm/nouveau/gr/gf100-: virtualise r419e00
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:25 +10:00
Ben Skeggs ad45a92b9a drm/nouveau/gr/gf100-: update 419eb0 where required
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 5b54b5b925 drm/nouveau/gr/gf100-: note missing 418800 modifications
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 99a3c67e84 drm/nouveau/gr/gf100-gf119: update 419cb8 where required
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 0e5a5e86f3 drm/nouveau/gr/gf100-: support firmware-provided bundle/method everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs fc36076441 drm/nouveau/gr/gf100-: virtualise tpc_mask + apply fixes from traces
We weren't placing higher TPC IDs in the right place on some configurations.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs aa5e38dc9f drm/nouveau/gr/gf100-: virtualise r419f78 + apply fixes from traces
Removed from GK110[B]/GK208 as RM traces show it not being touched.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 60c0264a66 drm/nouveau/gr/gf100-: virtualise gpc_tpc_nr
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs e7163b1922 drm/nouveau/gr/gf100-: virtualise r406500
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 60770fa28b drm/nouveau/gr/gf100-: virtualise dist_skip_table + improve algorithm
The algorithm for GM200 and newer matches RM for all the boards I have, but
I don't have enough data to try and figure something out for earlier boards,
so these will still write zeroes to the table as we did before.

The code in NVGPU isn't helpful here, it appears to handle specific cases.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs c4a2b6385d drm/nouveau/gr/gf100-gf119: modify max_ways_evict where required
I don't think this is done after Fermi, NVGPU used to do it but removed
the code, and I've not seen RM traces touching it either.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 43952c6f43 drm/nouveau/gr/gf100-: virtualise alpha_beta_tables + improve algorithms
I haven't yet been able to find a fully programatic way of calculating the
same mapping as NVIDIA for GF100-GF119, so the algorithm partially depends
on data tables for specific configurations.

I couldn't find traces for every possibility, so the algorithm will switch
to a mapping similar to what GK104-GM10x use if it encounters one.  We did
the wrong thing before anyway, so shouldn't matter too much.

The algorithm used in the GK104 implementation was ported from NVGPU.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs ff209c235d drm/nouveau/gr/gf100-: virtualise rop_mapping
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs 9d8a80df73 drm/nouveau/gr/gf100-: virtualise r4060a8 + apply fixes from traces
Also fixes some GPUs where we write too many registers.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs e51f75d501 drm/nouveau/gr/gf100-: virtualise tpc_per_gpc
GM20B now also shares the same code, as NVGPU shows it doesn't need
special treatment.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs fc740f545d drm/nouveau/gr/gf100-: virtualise sm_id/tpc_nr
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs ea4a2bb530 drm/nouveau/gr/gf100-: virtualise patch_ltc, noting missing init
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:24 +10:00
Ben Skeggs aedc49fd0e drm/nouveau/gr/gf100-: support firmware-provided sw_ctx everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 525230cb20 drm/nouveau/gr/gf100-: delete duplicated init code
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 04547482ae drm/nouveau/gr/gf100-: virtualise init_400054
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 6df6d2b95e drm/nouveau/gr/gf100-: apply be exception fixes from traces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 4615e9b438 drm/nouveau/gr/gf100-: virtualise init_shader_exceptions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs ab4d49a349 drm/nouveau/gr/gf100-: virtualise init_504430
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs f3ef80c0c4 drm/nouveau/gr/gf100-: virtualise init_tex_hww_esr
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 70d2148209 drm/nouveau/gr/gf100-: virtualise init_ppc_exceptions
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 778f18c607 drm/nouveau/gr/gf100-: virtualise init_419c9c + apply fixes from traces
Deliberately removed from non-GP100, as RM doesn't touch it.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 0a84a51334 drm/nouveau/gr/gf100-: virtualise init_419eb4 + apply fixes from traces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 0feab0250d drm/nouveau/gr/gf100-: virtualise init_419cc0 + apply fixes from traces
Pulled some init out of main per-GPC/TPC loops to match RM.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 0a5b97304b drm/nouveau/gr/gf100-: virtualise init_sked_hww_esr
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 2b297b0d6d drm/nouveau/gr/gf100-: virtualise init_40601c
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:23 +10:00
Ben Skeggs 3ac72e98b4 drm/nouveau/gr/gf100-: virtualise init_ds_hww_esr_2
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 2585a1b131 drm/nouveau/gr/gf100-: virtualise init_fecs_exceptions + apply fixes from traces
The value for GF100 has changed here, but it matches RM now.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 7c76ebb65a drm/nouveau/gr/gf100: write 0x400124 during init
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs dff30dbd1d drm/nouveau/gr/gf100-: virtualise init_swdx_pes_mask
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 0f78acc86b drm/nouveau/gr/gf100-: implement another chunk of bios-provided init
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 429412e231 drm/nouveau/gr/gf100-: virtualise init_rop_active_fbps
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs bfd27f39b5 drm/nouveau/gr/gf100-: virtualise init_num_active_ltcs
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 02917aa39d drm/nouveau/gr/gf100-: virtualise init_zcull
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 2fe5ff6371 drm/nouveau/gr/gf100-: virtualise init_vsc_stream_master
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs a37279e94c drm/nouveau/gr/gf100-: virtualise init_bios
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs cd9662f89e drm/nouveau/gr/gf100-: support clkgate_pack everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 8b058ca518 drm/nouveau/gr/gf100-: virtualise r405a14
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 6f63a5fb1e drm/nouveau/gr/gf100-: support firmware-provided sw_nonctx everywhere
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 1246f1dc22 drm/nouveau/gr/gf100-: virtualise init_gpc_mmu + apply fixes from traces
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 334cc26d4d drm/nouveau/fifo/gp100-: force individual channels into a channel group
RM does this for some reason, and is enforced in HW on Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs eda12417d3 drm/nouveau/fifo/gm107-: write instance address in channel runlist entry
RM does this for some reason.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 79bb4b617f drm/nouveau/fifo/gk208-: write pbdma timeout regs during initialisation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 8c4e9f9dff drm/nouveau/fifo/gk110-: support writing channel group runlist entries
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:22 +10:00
Ben Skeggs 4f2fc25c0f drm/nouveau/fifo/gk104-: poll for runlist update completion
Newer HW doesn't appear to send this event, which will cause long delays
in runlist updates if they don't complete immediately.

RM doesn't use these events anywhere, and an NVGPU commit message notes
that polling is the preferred method even on HW that supports the event.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 665870837a drm/nouveau/fifo/gk104-: add interfaces to support different runlist layouts
This will be required to support features on newer hardware.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs f9360c3aa6 drm/nouveau/fifo/gk104-: simplify definition of channel classes
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs a7cf01809b drm/nouveau/fifo/gk104-: require explicit runlist selection for channel allocation
We didn't used to be aware that runlist/engine IDs weren't the same thing,
or that there was such variability in configuration between GPUs.

By exposing this information to a client, and giving it explicit control
of which runlist it's allocating a channel on, we're able to make better
choices.

The immediate effect of this is that on GPUs where CE0 is the "GRCE", we
will now be allocating a copy engine running asynchronously to GR for BO
migrations - as intended.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs cc36205085 drm/nouveau/fifo/gk104-: support querying engines available on each runlist
Will be used to improve channel runlist selection.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs ddc669e256 drm/nouveau/fifo/gk104-: allow fault recovery code to be called by other subdevs
This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 55b8e85b0b drm/nouveau/fifo/gk104-: accept engine contexts for CE3 and up
These can exist on GP100 and newer.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs eb47db4f3b drm/nouveau/fifo: support channel count query
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 6eb01aa898 drm/nouveau/device: support querying available engines of a specific type
Will be used for fifo runlist selection.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs c5c9127b25 drm/nouveau/device: implement a generic method to query device-specific properties
We have a need to fetch data from GPU-specific sub-devices that is not
tied to any particular engine object.

This commit provides the framework to support such queries.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs f5650478ab drm/nouveau/disp/nv50-: pass nvkm_memory objects for channel push buffers
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs a9c44a88ca drm/nouveau/disp/nv50-: add channel interfaces to control error interrupts
This will be required to support Volta, but also allows us to remove code
that's duplicated for each channel type already.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 4a8621a24a drm/nouveau/disp/nv50-: add channel interfaces to determine the user area
This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 8531f57027 drm/nouveau/disp/nv50-: merge handling of pio and dma channels
Unnecessarily complicated, and a barrier to cleanly supporting Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 9b096283bf drm/nouveau/disp/nv50-: simplify definiton of core channels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 6d41a7536f drm/nouveau/disp/nv50-: simplify definition of cursor channels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs 3ceeef9c03 drm/nouveau/disp/nv50-: simplify definition of base channels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:21 +10:00
Ben Skeggs c2c3a00310 drm/nouveau/disp/nv50-: simplify definition of overlay immediate channels
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 46f74a8ad7 drm/nouveau/disp/nv50-: simplify definition of overlay channels
Introduces a new method of defining channels available from the display,
common to all channel types, allowing for more flexibility in available
channel types/counts, and reducing the amount of boiler-plate required.

This will be required to support Volta.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs abc1d4379b drm/nouveau/disp/nv50-: replace user object with engine pointer in channels
More simplification.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs bb3b0a4220 drm/nouveau/disp/nv50-: initialise from the engine, rather than the user object
Engines are initialised on an as-needed basis, so this results in the
same behaviour, whilst allowing us to simplify things a bit.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs f5e088d6f0 drm/nouveau/disp/nv50-: fetch mask of available piors during oneinit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 9fe4e17704 drm/nouveau/disp/nv50-: fetch mask of available sors during oneinit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs bf5d1a6b6a drm/nouveau/disp/nv50-: fetch mask of available dacs during oneinit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs f7b2ece37f drm/nouveau/disp/nv50-: fetch mask of available heads during oneinit
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 3b9ba66ab0 drm/nouveau/disp/nv50-: delay subunit construction until oneinit
We should be reading registers to determine which subunits are really
present on a given board, and this needs to be done after DEVINIT.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 85a3b9c839 drm/nouveau/fb/gm200-: fix overwriting of big page setting
Likely a rebase bug.  Should have no impact in default configuration due
to using per-instance setting by default.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs d1ea77ab5f drm/nouveau/fb/gf100-: bump size of mmu debug buffers to match big page size
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs d0e9351e42 drm/nouveau/fault/gp100: implement replayable fault buffer initialisation
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 36780d7eee drm/nouveau/fault: add infrastructure to support fault buffers
GPU-specific support will be added separately.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 2f68234fb3 drm/nouveau/mc/gp100-: route fault buffer interrupts to FAULT
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Ben Skeggs 1ce466894b drm/nouveau/core: define FAULT subdev
This will be responsible for the handling of MMU fault buffers on GPUs
that support them.

Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Gustavo A. R. Silva 7bf5b70bef drm/nouveau/secboot: remove VLA usage
In preparation to enabling -Wvla, remove VLA. In this particular
case directly use macro NVKM_MSGQUEUE_CMDLINE_SIZE instead of local
variable cmdline_size. Also, remove cmdline_size as it is not
actually useful anymore.

The use of stack Variable Length Arrays needs to be avoided, as they
can be a vector for stack exhaustion, which can be both a runtime bug
or a security flaw. Also, in general, as code evolves it is easy to
lose track of how big a VLA can get. Thus, we can end up having runtime
failures that are hard to debug.

Also, fixed as part of the directive to remove all VLAs from
the kernel: https://lkml.org/lkml/2018/3/7/621

Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:20 +10:00
Arnd Bergmann 9dfbd73199 drm/nouveau: nouveau: use larger buffer in nvif_vmm_map
gcc points out a buffer that is clearly too small to be used
in a meaningful way, as the 'sizeof(*args) + argc > sizeof(stack)'
will always fail:

In function 'memcpy',
    inlined from 'nvif_vmm_map' at drivers/gpu/drm/nouveau/nvif/vmm.c:55:2:
include/linux/string.h:353:9: error: '__builtin_memcpy' offset 40 is out of the bounds [0, 16] of object 'stack' with type 'u8[16]' {aka 'unsigned char[16]'} [-Werror=array-bounds]
  return __builtin_memcpy(p, q, size);
         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~
drivers/gpu/drm/nouveau/nvif/vmm.c: In function 'nvif_vmm_map':
drivers/gpu/drm/nouveau/nvif/vmm.c:40:5: note: 'stack' declared here

This makes the buffer large enough so it should serve the purpose
that the author presumably had in mind. Alternatively we could
just get rid of it completely and simplify the code at the cost
of always doing the kmalloc (as we do in the current version).

Fixes: 920d2b5ef2 ("drm/nouveau/mmu: define user interfaces to mmu vmm opertaions")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Ben Skeggs <bskeggs@redhat.com>
2018-05-18 15:01:19 +10:00
Dave Airlie 1fafef9dfe urgent i686 mmap fix for drm drivers
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Merge drm-fixes-for-v4.17-rc6-urgent into drm-next

Need to backmerge some nouveau fixes to reduce
the nouveau -next conflicts a lot.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-05-18 14:08:53 +10:00
Dave Airlie 1827cad96d Merge tag 'drm-intel-fixes-2018-05-17' of git://anongit.freedesktop.org/drm/drm-intel into drm-fixes
- Userptr IOCTL zero size check (Matt)
- Two hardware quirk fixes (Michel & Chris)

* tag 'drm-intel-fixes-2018-05-17' of git://anongit.freedesktop.org/drm/drm-intel:
  drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
  drm/i915/execlists: Use rmb() to order CSB reads
  drm/i915/userptr: reject zero user_size
2018-05-18 12:01:49 +10:00
Daniel Stone 5cb8b9969b drm/tegra: Use drm_gem_fb_destroy
Now that our destroy function is the same as the helper, use that
directly.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Daniel Stone c34a997d03 drm/tegra: Move fbdev unmap special case
User framebuffers are created with either bo->pages or bo->vaddr set,
depending on whether or not an IOMMU is present. On the other hand, the
framebuffer created for fbdev emulation has a vaddr mapping made if
bo->pages is set after creation. This is set up in fbdev probe.

Remove the special case unmapping from the general-purpose framebuffer
destroy, and move it to fbdev teardown.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Daniel Stone dbc33c7d65 drm/tegra: tegra_fb -> drm_framebuffer
Since tegra_fb is now the same as drm_framebuffer, we can just replace
the type completely.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Daniel Stone 0bc6af006f drm/tegra: Move GEM BOs to drm_framebuffer
Since drm_framebuffer can now store GEM objects directly, place them
there rather than in our own subclass. As this makes the framebuffer
create_handle function the same as the GEM framebuffer helper, we
can reuse that.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Daniel Stone e1189921b5 drm/tegra: Remove duplicate framebuffer num_planes
drm_framebuffer already stores num_planes for us.

Signed-off-by: Daniel Stone <daniels@collabora.com>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Souptick Joarder cc7add70ca drm/tegra: Adding new typedef vm_fault_t
Use new return type vm_fault_t for fault handler. For now, this is just
documenting that the function returns a VM_FAULT value rather than an
errno. Once all instances are converted, vm_fault_t will become a
distinct type.

Reference id -> 1c8f422059 ("mm: change return type to vm_fault_t")

Previously vm_insert_page() returns err which driver mapped into
VM_FAULT_* type. The new function vmf_insert_page() will replace this
inefficiency by returning VM_FAULT_* type.

Signed-off-by: Souptick Joarder <jrdr.linux@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Thierry Reding f40e1590c5 gpu: host1x: Acquire a reference to the IOVA cache
The IOVA API uses a memory cache to allocate IOVA nodes from. To make
sure that this cache is available, obtain a reference to it and release
the reference when the cache is no longer needed.

On 64-bit ARM this is hidden by the fact that the DMA mapping API gets
that reference and never releases it. On 32-bit ARM, this is papered
over by the Tegra DRM driver (the sole user of the host1x API requiring
the cache) acquiring a reference to the IOVA cache for its own purposes.
However, there may be additional users of this API in the future, so fix
this upfront to avoid surprises.

Fixes: 404bfb78da ("gpu: host1x: Add IOMMU support")
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Thierry Reding 24cfdc1ac7 drm/tegra: Acquire a reference to the IOVA cache
The IOVA API uses a memory cache to allocate IOVA nodes from. To make
sure that this cache is available, obtain a reference to it and release
the reference when the cache is no longer needed.

On 64-bit ARM this is hidden by the fact that the DMA mapping API gets
that reference and never releases it. On 32-bit ARM, however, the DMA
mapping API doesn't do that, so allocation of IOVA nodes fails.

Fixes: ad92601521 ("drm/tegra: Add Tegra DRM allocation API")
Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Tested-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Thierry Reding 5f43ac8d80 drm/tegra: Fix order of teardown in IOMMU case
The original code works fine, this is merely a cosmetic change to make
the teardown order the reverse of the setup order.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Dmitry Osipenko 27db6a0073 gpu: host1x: Fix dma_free_wc() argument in the error path
If IOVA allocation or IOMMU mapping fails, dma_free_wc() is invoked with
size=0 because of a typo, that triggers "kernel BUG at mm/vmalloc.c:124!".

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Reviewed-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 17:44:48 +02:00
Feifei Xu 24e6bc7843 drm/amdgpu: Set vega20 load_type to AMDGPU_FW_LOAD_DIRECT.
Please revert this patch when psp load fw is enabled.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:22 -05:00
Alex Deucher 3251c0438a drm/amdgpu: Use vbios table for gpu info on vega20
Use the vbios table rather than gpu info firmware.

Squash of the following patches:
drm/amdgpu/vg20: fallback to vbios table if gpu info fw is not available (v2)
drm/amdgpu: drop gpu_info firmware for vega20

Reviewed-by: Amber Lin <Amber.Lin@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:22 -05:00
Alex Deucher 59b0b509f1 drm/amdgpu/atomfirmware: add parser for gfx_info table
Add support for the gfx_info table on boards that use atomfirmware.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:22 -05:00
Alex Deucher 6f68711dd6 drm/amdgpu/atomfirmware: add new gfx_info data table v2.4 (v2)
Adds additional gfx configuration data.

v2: fix typo

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:21 -05:00
Jerry (Fangzhi) Zuo 8ad63122f9 drm/amd/display: Add harvest IP support for Vega20
Retrieve fuses to determine the availability of pipes, and
eliminate pipes that cannot be used.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Tony Cheng <Tony.Cheng@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
2018-05-17 10:13:21 -05:00
Jerry (Fangzhi) Zuo 1edb2c8a32 drm/amd/display: Add BIOS smu_info v3_3 support for Vega20
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
2018-05-17 10:13:20 -05:00
Feifei Xu 14a13a0ef0 drm/amd/display: Remove COMBO_DISPLAY_PLL0 from Vega20
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Hersen Wu <hersenxs.wu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
2018-05-17 10:13:20 -05:00
Jerry (Fangzhi) Zuo 138bc36051 drm/amd/display: Add Vega20 config. support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Jerry (Fangzhi) Zuo <Jerry.Zuo@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:20 -05:00
Roman Li d82420b56a drm/amd: Add dce-12.1 gpio aux registers (v2)
Updating dce12 register headers by adding dc registers
required for potential DP LTTPR support.

v2: fix mode change

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Roman Li <Roman.Li@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:19 -05:00
Feifei Xu c6034aa2c4 drm/amdgpu: Add vega20 to dc support check (v2)
v2: fix whitespace

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:19 -05:00
Feifei Xu 1fe6bf2f33 drm/amd/display/dm: Add vega20 support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:18 -05:00
Feifei Xu a95d89e2d8 drm/amdgpu: Add nbio support for vega20 (v2)
Some register offset in nbio v7.4 are different with v7.0.

v2: Use nbio7.0 for now.

TODO: add a new nbio 7.4 module (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:18 -05:00
Feifei Xu 7c7af6c10d drm/amdgpu/soc15: Add ip blocks for vega20 (v2)
Same as vega10 now.

v2: squash in typo fix

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:18 -05:00
Feifei Xu 8ee273e516 drm/amdgpu/soc15: dynamic initialize ip offset for vega20
Vega20 need a seperate vega20_reg_init.c due to ip base
offset difference.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:17 -05:00
Feifei Xu f980d127db drm/amdgpu/soc15: Set common clockgating for vega20.
Same as vega10 for now.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:17 -05:00
Feifei Xu 935be7a0ce drm/amdgpu/soc15:Add vega20 soc15_common_early_init support
Set external_rev_id and disable cg,pg for now.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:17 -05:00
Feifei Xu 28b576b27a drm/amdgpu/gfx9: Add clockgatting support for vega20
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:16 -05:00
Feifei Xu 61324ddc5b drm/amdgpu/gfx9: Add support for vega20
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:16 -05:00
Feifei Xu d3adedb455 drm/amdgpu/gfx9: Add gfx config for vega20. (v4)
v2: clean up (Alex)
v3: additional cleanups (Alex)
v4: drop leftover TODO (Alex)

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:15 -05:00
Feifei Xu bb5368aac5 drm/amdgpu/gfx9: Add vega20 golden settings (v3)
v2: squash in updates (Alex)
v3: squash in more updates (Alex)

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:15 -05:00
Feifei Xu 940328fe35 drm/amdgpu/gfx9: Add support for vega20 firmware
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:15 -05:00
Feifei Xu 7eb32a7012 drm/amdgpu/sdma4: Add clockgating support for vega20
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:14 -05:00
Feifei Xu 84f50e9c80 drm/amdgpu/sdma4: Add vega20 golden settings (v3)
v2: squash in updates (Alex)
v3: squash in more updates (Alex)

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:14 -05:00
Feifei Xu 54a29ef758 drm/amdgpu/sdma4: Specify vega20 firmware
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:14 -05:00
Feifei Xu c2d7fd2bae drm/amdgpu/mmhub: Add clockgating support for vega20
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:13 -05:00
Feifei Xu d96b428c3c drm/amdgpu/gmc9: Add vega20 support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:13 -05:00
Feifei Xu a2c319b63e drm/amdgpu/virtual_dce: Add vega20 support
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:13 -05:00
Feifei Xu 341b4ce233 drm/amdgpu: Specify vega20 vce firmware
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:12 -05:00
Feifei Xu cac18c82e0 drm/amdgpu: Specify vega20 uvd firmware
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:12 -05:00
Feifei Xu 4b1f540ae1 drm/amdgpu: Add vega20 ucode loading method
The same as vega10.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:11 -05:00
Feifei Xu 8fd2d849da drm/amdgpu/psp: Add initial psp support for vega20
The same as vega10 for now.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:11 -05:00
Feifei Xu d3bfb6647c drm/amdgpu/powerplay: Add initial vega20 support v2
Initial powerplay support the same as vega10 for now.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:11 -05:00
Feifei Xu a167ae2509 drm/amdgpu: Add smu firmware support for vega20
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:10 -05:00
Feifei Xu e4bd817040 drm/amdgpu: set asic family for vega20.
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:10 -05:00
Feifei Xu 27c0bc7163 drm/amdgpu: Add gpu_info firmware for vega20. (v2)
vega20_gpu_info firmware stores gpu configuration for vega20.

v2: drop gpu info firmware for vega20

Squash of:
drm/amdgpu: Add gpu_info firmware for vega20.
drm/amdgpu: drop gpu_info firmware for vega20

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:10 -05:00
Feifei Xu 956fcddc0b drm/amdgpu: Add vega20 to asic_type enum.
Add vega20 to amd_asic_type enum and amdgpu_asic_name[].

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:09 -05:00
James Zhu b2f87c9182 drm/amd/include/vg20: adjust VCE_BASE to reuse vce 4.0 header files
Vega20 uses vce 4.1 engine, all the registers have the
same absolute offset with vce 4.0. By adjusting vega20
VCE_BASE, vce 4.1 can reuse vce 4.0 header files.

Signed-off-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:09 -05:00
Feifei Xu 5eb26e7ae1 drm/amd: Add vega20_ip_offset.h headerfile for vega20. (v2)
This headerfile contains vega20's ip base addresses.

v2: squash in MP1_BASE fix

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 10:13:09 -05:00
Feifei Xu b6110c00ce drm/amdgpu: Fix hardcoded base offset of vram pages
In gmc_v9_0_vram_gtt_location(),the vram_base_offset is hardcoded
to 0 in dGPU. Fix it by reading mmMC_VM_FB_OFFSET or return
zfb_phys_addr if ZFB is enabled.

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Signed-off-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 08:54:24 -05:00
Feifei Xu cc3a98cc6e drm/amdgpu: Drop the unused header files in soc15.c.
Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 08:54:23 -05:00
Evan Quan 11a89b431e drm/amd/powerplay: add a framework for perfroming pre display
configuration change settings

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 08:54:23 -05:00
Evan Quan 73aa1b9af5 drm/amd/powerplay: new framework to honour DAL clock limits
This is needed for vega12 and vega20 which do not support legacy
powerstate. With this new framework, the DAL clocks limits can also
be honored on these asics.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 08:54:22 -05:00
Feifei Xu c5fb5426dd drm/amdgpu/gfx9: Update golden setting for gfx9_0.
Update golden_settings_gc_9_0[].

Signed-off-by: Feifei Xu <Feifei.Xu@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-17 08:54:22 -05:00
Dmitry Osipenko a43d0a00ea drm/tegra: dc: Rename supports_blending to has_legacy_blending
Older Tegra chips do support blending as well. Rename the SoC info entry
.supports_blending to .has_legacy_blending to eliminate the confusion.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 14:08:44 +02:00
Dmitry Osipenko 3dae08bc07 drm/tegra: plane: Implement zpos plane property for older Tegras
Older Tegra's do not support plane's Z position handling in hardware,
but the hardware provides knobs to implement it in software.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 14:08:44 +02:00
Dmitry Osipenko acc6a3a9af drm/tegra: dc: Enable plane scaling filters
Currently resized plane produces a "pixelated" image which doesn't look
nice, especially in a case of a video overlay. Enable scaling filters that
significantly improve image quality of a scaled overlay.

Signed-off-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 14:08:44 +02:00
Thierry Reding 0c407de5ed drm/tegra: Refactor IOMMU attach/detach
Attaching to and detaching from an IOMMU uses the same code sequence in
every driver, so factor it out into separate helpers.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 14:08:40 +02:00
Thierry Reding 230630bd38 drm/tegra: gr3d: Properly clean up resources
Failure to register the Tegra DRM client would leak the resources. Move
cleanup code to error unwinding gotos to fix that and share the cleanup
code with the other error paths.

Reviewed-by: Dmitry Osipenko <digetx@gmail.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2018-05-17 14:03:30 +02:00
Laurent Pinchart 47a52d024e media: drm: rcar-du: Add support for CRC computation
Implement CRC computation configuration and reporting through the DRM
debugfs-based CRC API. The CRC source can be configured to any input
plane or the pipeline output.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-05-17 06:22:08 -04:00
Laurent Pinchart 6e274b43b5 media: v4l: vsp1: Extend the DU API to support CRC computation
Add a parameter (in the form of a structure to ease future API
extensions) to the VSP atomic flush handler to pass CRC source
configuration, and pass the CRC value to the completion callback.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Reviewed-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Signed-off-by: Mauro Carvalho Chehab <mchehab+samsung@kernel.org>
2018-05-17 06:22:08 -04:00
Laurent Pinchart 315852b422 drm: rcar-du: Fix build failure
Commit 75a07f399c ("drm: rcar-du: Zero-out sg_tables when duplicating
plane state") introduced a reference to the alpha field of struct
rcar_du_vsp_plane_state that got removed in commit 301a9b8d54
("drm/rcar-du: Convert to the new generic alpha property"). The issue
stems from the merge of the two commits through separate branches and
breaks compilation of the driver. Fix it.

Fixes: 75a07f399c ("drm: rcar-du: Zero-out sg_tables when duplicating plane state")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Tested-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180515174752.28954-1-laurent.pinchart+renesas@ideasonboard.com
2018-05-17 15:03:40 +10:00
Laurent Pinchart dd856d924b drm: rcar-du: Fix rcar_du_of_init() stub
The rcar_du_of_init() function is supposed to be defined as a stub when
CONFIG_DRM_RCAR_LVDS is disabled as the rcar_du_of.c file isn't compiled
in that case. However, a bug in the configuration option check makes it
a stub when CONFIG_DRM_RCAR_LVDS=m as well, which prevents legacy DTs
from being fixed at boot time. Fix the configuration option check by
using IS_ENABLED.

Fixes: 81c0e3dd82 ("drm: rcar-du: Fix legacy DT to create LVDS encoder nodes")
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Reviewed-by: Kieran Bingham <kieran.bingham+renesas@ideasonboard.com>
Signed-off-by: Dave Airlie <airlied@redhat.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180515155736.3379-1-laurent.pinchart+renesas@ideasonboard.com
2018-05-17 15:03:32 +10:00
Stephen Rothwell 548da31da9 drm/amdgpu: include pagemap.h for release_pages()
Fixes: 5ae0283e83 ("drm/amdgpu: Add userptr support for KFD"
Cc: Felix Kuehling <Felix.Kuehling@amd.com>
Cc: Oded Gabbay <oded.gabbay@gmail.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-05-17 14:59:08 +10:00
Dave Airlie bc91d1810f Merge branch 'vmwgfx-fixes-4.17' of git://people.freedesktop.org/~thomash/linux into drm-fixes
A single fix for a recent regression.

* 'vmwgfx-fixes-4.17' of git://people.freedesktop.org/~thomash/linux:
  drm/vmwgfx: Set dmabuf_size when vmw_dmabuf_init is successful
2018-05-17 12:00:53 +10:00
Dave Airlie 3d3aa969cb - core: Fix regression in dev node offsets (Haneen)
- vc4: Fix memory leak on driver close (Eric)
 - dumb-buffers: Prevent overflow in DIV_ROUND_UP() (Dan)
 
 Cc: Haneen Mohammed <hamohammed.sa@gmail.com>
 Cc: Eric Anholt <eric@anholt.net>
 Cc: Dan Carpenter <dan.carpenter@oracle.com>
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Merge tag 'drm-misc-fixes-2018-05-16' of git://anongit.freedesktop.org/drm/drm-misc into drm-fixes

- core: Fix regression in dev node offsets (Haneen)
- vc4: Fix memory leak on driver close (Eric)
- dumb-buffers: Prevent overflow in DIV_ROUND_UP() (Dan)

Cc: Haneen Mohammed <hamohammed.sa@gmail.com>
Cc: Eric Anholt <eric@anholt.net>
Cc: Dan Carpenter <dan.carpenter@oracle.com>

* tag 'drm-misc-fixes-2018-05-16' of git://anongit.freedesktop.org/drm/drm-misc:
  drm/dumb-buffers: Integer overflow in drm_mode_create_ioctl()
  drm/vc4: Fix leak of the file_priv that stored the perfmon.
  drm: Match sysfs name in link removal to link creation
2018-05-17 12:00:17 +10:00
Dan Carpenter 2b6207291b drm/dumb-buffers: Integer overflow in drm_mode_create_ioctl()
There is a comment here which says that DIV_ROUND_UP() and that's where
the problem comes from.  Say you pick:

	args->bpp = UINT_MAX - 7;
	args->width = 4;
	args->height = 1;

The integer overflow in DIV_ROUND_UP() means "cpp" is UINT_MAX / 8 and
because of how we picked args->width that means cpp < UINT_MAX / 4.

I've fixed it by preventing the integer overflow in DIV_ROUND_UP().  I
removed the check for !cpp because it's not possible after this change.
I also changed all the 0xffffffffU references to U32_MAX.

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Link: https://patchwork.freedesktop.org/patch/msgid/20180516140026.GA19340@mwanda
2018-05-16 17:56:06 +02:00
Michel Thierry b579f924a9 drm/i915/gen9: Add WaClearHIZ_WM_CHICKEN3 for bxt and glk
Factor in clear values wherever required while updating destination
min/max.

References: HSDES#1604444184
Signed-off-by: Michel Thierry <michel.thierry@intel.com>
Cc: mesa-dev@lists.freedesktop.org
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Oscar Mateo <oscar.mateo@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Link: https://patchwork.freedesktop.org/patch/msgid/20180510200708.18097-1-michel.thierry@intel.com
Cc: stable@vger.kernel.org
Cc: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
Link: https://patchwork.freedesktop.org/patch/msgid/20180514165445.9198-1-michel.thierry@intel.com
(backported from commit 0c79f9cb77)
Signed-off-by: Joonas Lahtinen <joonas.lahtinen@linux.intel.com>
2018-05-16 11:21:09 +03:00
Deepak Rawat 91ba9f28a3 drm/vmwgfx: Set dmabuf_size when vmw_dmabuf_init is successful
SOU primary plane prepare_fb hook depends upon dmabuf_size to pin up BO
(and not call a new vmw_dmabuf_init) when a new fb size is same as
current fb. This was changed in a recent commit which is causing
page_flip to fail on VM with low display memory and multi-mon failure
when cycle monitors from secondary display.

Cc: <stable@vger.kernel.org> # 4.14, 4.16
Fixes: 20fb5a635a ("drm/vmwgfx: Unpin the screen object backup buffer when not used")
Signed-off-by: Deepak Rawat <drawat@vmware.com>
Reviewed-by: Sinclair Yeh <syeh@vmware.com>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
2018-05-16 08:01:20 +02:00
Dave Airlie 95d2c3e15d Merge branch 'drm-next-4.18' of git://people.freedesktop.org/~agd5f/linux into drm-next
Main changes for 4.18.  I'd like to do a separate pull for vega20 later
this week or next.  Highlights:
- Reserve pre-OS scanout buffer during init for seemless transition from
  console to driver
- VEGAM support
- Improved GPU scheduler documentation
- Initial gfxoff support for raven
- SR-IOV fixes
- Default to non-AGP on PowerPC for radeon
- Fine grained clock voltage control for vega10
- Power profiles for vega10
- Further clean up of powerplay/driver interface
- Underlay fixes
- Display link bw updates
- Gamma fixes
- Scatter/Gather display support on CZ/ST
- Misc bug fixes and clean ups

[airlied: fixup v3d vs scheduler API change]

Link: https://patchwork.freedesktop.org/patch/msgid/20180515185450.1113-1-alexander.deucher@amd.com
Signed-off-by: Dave Airlie <airlied@redhat.com>
2018-05-16 08:31:29 +10:00
Dave Airlie b8a71080ad Last drm/i915 changes for v4.18:
- NV12 enabling (Chandra, Maarten)
 - ICL workarounds (Oscar)
 - ICL basic DPLL enabling (Paulo)
 - GVT updates
 - DP link config refactoring (Jani)
 - Module parameter to override DMC firmware (Jani)
 - PSR updates (José, DK, Daniel, Ville)
 - ICL DP vswing programming (Manasi)
 - ICL DBuf slice updates (Mahesh)
 - Selftest fixes and updates (Chris, Matthew, Oscar)
 - Execlist fixes and updates (Chris)
 - Stolen memory first 4k fix (Hans de Goede)
 - wait_for fixes (Mika)
 - Tons of GEM improvements (Chris)
 - Plenty of other fixes and improvements (Everyone)
 - Crappy changelog (Me)
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Merge tag 'drm-intel-next-2018-05-14' of git://anongit.freedesktop.org/drm/drm-intel into drm-next

Last drm/i915 changes for v4.18:

- NV12 enabling (Chandra, Maarten)
- ICL workarounds (Oscar)
- ICL basic DPLL enabling (Paulo)
- GVT updates
- DP link config refactoring (Jani)
- Module parameter to override DMC firmware (Jani)
- PSR updates (José, DK, Daniel, Ville)
- ICL DP vswing programming (Manasi)
- ICL DBuf slice updates (Mahesh)
- Selftest fixes and updates (Chris, Matthew, Oscar)
- Execlist fixes and updates (Chris)
- Stolen memory first 4k fix (Hans de Goede)
- wait_for fixes (Mika)
- Tons of GEM improvements (Chris)
- Plenty of other fixes and improvements (Everyone)
- Crappy changelog (Me)

Signed-off-by: Dave Airlie <airlied@redhat.com>

# gpg: Signature made Mon 14 May 2018 11:04:24 PM AEST
# gpg:                using RSA key D398079D26ABEE6F
# gpg: Good signature from "Jani Nikula <jani.nikula@intel.com>"
# gpg: WARNING: This key is not certified with a trusted signature!
# gpg:          There is no indication that the signature belongs to the owner.
# Primary key fingerprint: 1565 A65B 77B0 632E 1124  E59C D398 079D 26AB EE6F

# Conflicts:
#	drivers/gpu/drm/i915/intel_lrc.c
#	drivers/gpu/drm/i915/intel_sprite.c
Link: https://patchwork.freedesktop.org/patch/msgid/87k1s51bvw.fsf@intel.com
2018-05-16 07:10:13 +10:00
Nayan Deshmukh 8344c53f57 drm/scheduler: remove unused parameter
this patch also effect the amdgpu and etnaviv drivers which
use the function drm_sched_entity_init

Signed-off-by: Nayan Deshmukh <nayan26deshmukh@gmail.com>
Suggested-by: Christian König <christian.koenig@amd.com>
Acked-by: Lucas Stach <l.stach@pengutronix.de>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:27 -05:00
Dirk Hohndel 1297bf2e91 Add SPDX idenitifier and clarify license
This is dual licensed under GPL-2.0 or MIT.

Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org>
Signed-off-by: Thomas Hellstrom <thellstrom@vmware.com>
Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:27 -05:00
Christian König 6b155d6af0 drm/amdgpu: print the BO flags in the gem debugfs entry
Quite useful to know.

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:27 -05:00
Christian König c7535379f6 drm/amdgpu: drop printing the BO offset in the gem debugfs (v2)
It is meaningless anyway.

v2: remove unused variable (Alex)

Signed-off-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:26 -05:00
Yong Zhao 959a2091fa drm/amdgpu: Add support to change mtype for 2nd part of gart BOs on GFX9
This change prepares for a workaround in amdkfd for a GFX9 HW bug. It
requires the control stack memory of compute queues, which is allocated
from the second page of MQD gart BOs, to have mtype NC, rather than
the default UC.

Signed-off-by: Yong Zhao <yong.zhao@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:26 -05:00
Mikita Lipski 8eb7719813 drm/amd/powerplay: Add notify PWE function to SMU10
Functionality to message smc to enable pwe after gpu suspense.
It is used in case when display resumes from S3 and wants to start
audio driver by enabling pwe.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:25 -05:00
Shirish S a2a330ad66 drm/amd/display: remove need of modeset flag for overlay planes (V2)
This patch is in continuation to the
"843e3c7 drm/amd/display: defer modeset check in dm_update_planes_state"
where we started to eliminate the dependency on
DRM_MODE_ATOMIC_ALLOW_MODESET to be set by the user space,
which as such is not mandatory.

After deferring, this patch eliminates the dependency on the flag
for overlay planes.

This has to be done in stages as its a pretty complex and requires thorough
testing before we free primary planes as well from dependency on modeset
flag.

V2: Simplified the plane type check.

Signed-off-by: Shirish S <shirish.s@amd.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:25 -05:00
Junwei Zhang c430bc9770 drm/amdgpu: fix null pointer for bo unmap trace function
fix crash in trace.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:25 -05:00
Alex Deucher 323a9dbc45 drm/amdgpu/gmc9: remove unused register defs
These got moved to the new df module so no longer
used in this file.

Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:24 -05:00
Christian König 996cab9553 drm/amdgpu: add HDP flush dummy for UVD 6/7
The UVD firmware doesn't seem to like the HDP flush here.

This worked for years without HDP flush, so just skip it.

Signed-off-by: Christian König <christian.koenig@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:24 -05:00
Junwei Zhang a50cb94819 drm/amdgpu: set ttm bo priority before initialization
Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: David Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:23 -05:00
Junwei Zhang 967c650d49 drm/ttm: remove priority hard code when initializing ttm bo
Then priority could be set before initialization.
By default, it requires to kzalloc ttm bo. In fact, we always do so.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: David Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:23 -05:00
Rex Zhu 9164e8b7b3 drm/amd/pp: Fix performance drop on Fiji
The performance drop if the default TDP more than 256 Watt

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:23 -05:00
Rex Zhu 4ccd2d931c drm/amd/pp: Implement force_clock_level for RV
under manual dpm mode, user can set gfx/mem clock
through sysfs pp_dpm_sclk/mclk on Rv.

Reviewed-by: Evan Quan <evan.quan@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:22 -05:00
Junwei Zhang 267256b5d8 drm/amd/powerplay: add PME smu message for raven
Used for working around an audio bug on some platforms.

Signed-off-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:22 -05:00
Colin Ian King f4c2cc4321 drm/amd/display: clean up assignment of amdgpu_crtc
The declaration of pointer amdgpu_crtc has a redundant assignment to
amdgpu_crtc. Clean this up by removing it.

Detected by CoverityScan, CID#1460299 ("Evaluation order violation")

Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:21 -05:00
Colin Ian King 3d3c4f1b4d drm/amd/powerplay: fix spelling mistake: "contruct" -> "construct"
Trivial fix to spelling mistake in PP_ASSERT_WITH_CODE message text

Signed-off-by: Colin Ian King <colin.king@canonical.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:21 -05:00
Rex Zhu 4aa8c41bfb drm/amd/pp: Refine the output of pp_power_profile_mode on VI
In order to keep consist with Vega,
the output format of the pp_power_profile_mode would be
<integer><mode name string>< “*” for current profile>:"detail settings"
and remove the "CURRENT" mode line.

for example:
NUM        MODE_NAME     SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL     MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
  0   3D_FULL_SCREEN:        0              100               30                0              100               10
  1     POWER_SAVING:       10                0               30                -                -                -
  2            VIDEO:        -                -                -               10               16               31
  3               VR:        0               11               50                0              100               10
  4          COMPUTE:        0                5               30                -                -                -
  5         CUSTOM *:        0                5               30                0              100               10
NUM        MODE_NAME     SCLK_UP_HYST   SCLK_DOWN_HYST SCLK_ACTIVE_LEVEL     MCLK_UP_HYST   MCLK_DOWN_HYST MCLK_ACTIVE_LEVEL
  0   3D_FULL_SCREEN:        0              100               30                0              100               10
  1   POWER_SAVING *:       10                0               30                0              100               10
  2            VIDEO:        -                -                -               10               16               31
  3               VR:        0               11               50                0              100               10
  4          COMPUTE:        0                5               30                -                -                -
  5           CUSTOM:        -                -                -                -                -                -

Reviewed-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:21 -05:00
Chunming Zhou 4bebcceede drm/amdgpu: invalidate parent bo when shadow bo was invalidated
Shadow BO is located on GTT and its parent (PT and PD) BO could located on VRAM.
In some case, the BO on GTT could be evicted but the parent did not. This may
cause the shadow BO not be put in the evict list and could not be invalidate
correctly.
v2: suggested by Christian

Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reported-by: Shaoyun Liu <Shaoyun.Liu@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:20 -05:00
Chunming Zhou 3f4299bee6 drm/amdgpu: abstract bo_base init function
Signed-off-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:20 -05:00
Tom St Denis 7e4237dbe4 drm/amd/amdgpu: Add some documentation to the debugfs entries
Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Huang Rui <ray.huang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:19 -05:00
Tom St Denis dfe8a0187c drm/amd/amdgpu: vcn10 Add callback for emit_reg_write_reg_wait
The callback .emit_reg_write_reg_wait was missing for vcn decode
which resulted in a kernel oops.

Signed-off-by: Tom St Denis <tom.stdenis@amd.com>
Reviewed-by: Andrey Grodzovsky <andrey.grodzovsky@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-05-15 13:44:19 -05:00