p71924506
/
linux_old1
1
0
Fork 0
Code Issues Pull Requests Projects Releases Wiki Activity
389,285 Commits 2 Branches 0 Tags 3.6 GiB
Commit Graph

389285 Commits

Author SHA1 Message Date
Alex Deucher 9e9d976205 drm/radeon/dpm: add new callback for powergating UVD (v4) 
Starting on CIK, multi-media blocks like UVD no longer
have special power state.  Rather they have their own
DPM implementation which adjusts their clocks dynamically
when active.  When they are not active, the blocks are
powergated to save power.

v2: add missing pm locks
v3: rebase on uvd state selection rework
v4: fix inverted logic typo noticed by Christian

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:34 -04:00
Alex Deucher 2b4c8022fa drm/radeon/dpm: implement force performance level for KB/KV 
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:33 -04:00
Alex Deucher ae3e40e871 drm/radeon/dpm: add debugfs support for KB/KV 
This allows you to look at the current DPM state via
debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:32 -04:00
Alex Deucher 5496131e45 drm/radeon/dpm: implement vblank_too_short callback for CI 
Check if we can switch the mclk during the vblank time otherwise
we may get artifacts on the screen when the mclk changes.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:31 -04:00
Alex Deucher 89536fd600 drm/radeon/dpm: implement force performance level for CI 
Allows you to force the selected performance level via sysfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:30 -04:00
Alex Deucher 94b4adc5ae drm/radeon/dpm: add debugfs support for CI 
This allows you to look at the current DPM state via debugfs.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:30 -04:00
Alex Deucher cc8dbbb4f6 drm/radeon: add dpm support for CI dGPUs (v2) 
This adds dpm support for btc asics. This includes:
- dynamic engine clock scaling
- dynamic memory clock scaling
- dynamic voltage scaling
- dynamic pcie gen switching

Set radeon.dpm=1 to enable.

v2: remove unused radeon_atombios.c changes,
    make missing smc ucode non-fatal

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:29 -04:00
Alex Deucher 41a524abff drm/radeon/kms: add dpm support for KB/KV 
This adds dpm support for KB/KV asics.  This includes:
- dynamic engine clock scaling
- dynamic voltage scaling
- power containment
- shader power scaling

Set radeon.dpm=1 to enable.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:28 -04:00
Alex Deucher 6bb5c0d74c drm/radeon/dpm: add helper to fetch the vrefresh of the current mode 
Needed for DPM on CI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:27 -04:00
Alex Deucher 61fb192a1c drm/radeon/dpm: add a helper to encode pcie lane setting 
convert from number of lanes to register setting.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:26 -04:00
Alex Deucher c4453e6613 drm/radeon/dpm: add vce clocks to radeon_ps 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:26 -04:00
Alex Deucher 4df5ac2652 drm/radeon: add r600_get_pcie_lane_support helper 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:25 -04:00
Alex Deucher 96d2af2150 drm/radeon: parse the acp clock voltage deps table 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:24 -04:00
Alex Deucher 3cb928ff1e drm/radeon: parse the samu clock voltage deps table 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:23 -04:00
Alex Deucher becfa6989b drm/radeon/dpm: clean up the extended table error pathes 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:22 -04:00
Alex Deucher 018042b15b drm/radeon: parse the uvd clock voltage deps table 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:22 -04:00
Alex Deucher 57ff476171 drm/radeon: parse the vce clock voltage deps table 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:21 -04:00
Alex Deucher 94a914f51e drm/radeon: add clock voltage dep tables for acp, samu 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:20 -04:00
Alex Deucher d29f013b20 drm/radeon: add structs to store vce clock voltage deps 
Used for vce power management.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:19 -04:00
Alex Deucher dd621a22cf drm/radeon/dpm: grab mvdd_dependency_on_mclk info from vbios 
Required for dpm on CI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:19 -04:00
Alex Deucher 58cb7632df drm/radeon/dpm: add support for parsing the atom powertune table 
Needed for DPM on CI.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:18 -04:00
Alex Deucher ef976ec4e2 drm/radeon/dpm: update cac leakage table parsing for CI 
Uses a different table format if the board supports EVV.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:17 -04:00
Alex Deucher 9dd9333b2f drm/radeon: adjust si_dpm function for code sharing 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:16 -04:00
Alex Deucher 286d9cc67a drm/radeon: add get_temperature() callbacks for CIK (v2) 
This added support for the on-chip thermal sensors on
CIK asics.

v2: fix register offset.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:15 -04:00
Alex Deucher 12262906b1 drm/radeon: add KB/KV to r600_is_internal_thermal_sensor 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:15 -04:00
Alex Deucher 2aacd48fa7 drm/radeon: add CI to r600_is_internal_thermal_sensor() 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:14 -04:00
Alex Deucher 16fbe00d24 drm/radeon: add support for thermal controller on KB/KV 
No support for reading temperature back yet.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:13 -04:00
Alex Deucher a412fce054 drm/radeon/cik: add rlc helpers for DPM 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:12 -04:00
Alex Deucher 84a9d9eeab drm/radeon: add structs to store uvd clock voltage deps 
Used for uvd power management.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:12 -04:00
Alex Deucher f7466e6ca0 drm/radeon: switch to pptable.h 
Internally we switched to using a separate header for
atombios pplib definitions.  Switch over the open source
driver.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:11 -04:00
Alex Deucher 03243fc656 drm/radeon/sumo add helper to go from vid7 to vid2 
Needed for DPM on KB/KV.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:10 -04:00
Alex Deucher 1d58234d5e drm/radeon: add indirect accessors for dift registers on CIK 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:09 -04:00
Alex Deucher 22c775ce80 drm/radeon: implement clock and power gating for CIK (v3) 
Only the APUs support power gating.

v2: disable cgcg for now
v3: workaround hw issue in mgcg

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:08 -04:00
Alex Deucher 1fd11777c2 drm/radeon: convert SI,CIK to use sumo_rlc functions 
and remove duplicate si_rlc functions.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:08 -04:00
Alex Deucher 10b7ca7e09 drm/radeon: clean up sumo_rlc_init() for code sharing 
This will eventually be shared with newer asics to
reduce code duplication.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:07 -04:00
Alex Deucher 866d83de0c drm/radeon/cik: restructure rlc setup 
Restructure rlc setup to handle clock and power
gating.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:06 -04:00
Alex Deucher 7235711a43 drm/radeon: add support for ASPM on CIK asics 
Enables PCIE ASPM (Active State Power Management) on
CIK asics.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:05 -04:00
Alex Deucher 8a7cd27679 drm/radeon/cik: add support for pcie gen1/2/3 switching 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:04 -04:00
Alex Deucher 8c68e39388 drm/radeon: switch CIK to use radeon_ucode.h 
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:04 -04:00
Alex Deucher 62c35fd7d2 drm/radeon/cik: implement some more atom helpers for DPM 
Required for DPM on CIK.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:03 -04:00
Alex Deucher 58ea2deab3 drm/radeon/kms: fix up dce8 display watermark calc for dpm 
Calculate the low and high watermarks based on the low and high
clocks for the current power state.  The dynamic pm hw will select
the appropriate watermark based on the internal dpm state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:02 -04:00
Alex Deucher d4d3278c65 drm/radeon/dpm: use performance state if no UVD state 
Newer asics don't have specific UVD states.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:01 -04:00
Alex Deucher edcd26e81f drm/radeon: default to 1024M gart size on rv770+ 
Newer asics have a lot of vram so it's less of an
issue to waste a little more space for the gart
page table.  This gives us some additional gart space
before having to migrate to non-gart system ram
for games, etc. where we use up most of vram.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:00 -04:00
Alex Deucher 6032034761 drm/radeon/dpm: rework thermal state handling 
1. Handle the the thermal state directly in the work handler.
Remove the state selection function since nothing else uses it now.
2. On some asics there is no thermal state, so we just use a regular
state and force the low performance state.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:30:00 -04:00
Alex Deucher ce3537d571 drm/radeon/dpm: use multiple UVD power states (v3) 
Use the UVD handle information to determine which
which power states to select when using UVD.  For
example, decoding a single SD stream requires much
lower clocks than multiple HD streams.

v2: switch to a cleaner dpm/uvd interface
v3: change the uvd power state while streams
are active if need be

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:29:59 -04:00
Alex Deucher 85a129ca8d drm/radeon: add UVD->DPM helper function (v5) 
Add a helper function for counting the number of open stream handles.

v2: fix copy-pasta in comments and whitespace error
v3: make function static since it's only used in radeon_uvd.c
at the moment
v4: make non-static again for future changes
v5: make static again for new rework of dpm uvd changes

Signed-off-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:29:58 -04:00
Alex Deucher 4f86296758 drm/radeon/kms: remove r6xx+ blit copy routines 
No longer used now that we use the async dma engines or
CP DMA for bo copies.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:29:57 -04:00
Alex Deucher 8dddb993bc drm/radeon: switch r6xx+ to using CP DMA for the blit copy callback 
CP DMA is lighter weight than using the 3D engine.

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
 2013-08-30 16:29:57 -04:00
Alex Deucher 118bdbd86b drm/edid: add quirk for Medion MD30217PG 
This LCD monitor (1280x1024 native) has a completely
bogus detailed timing (640x350@70hz).  User reports that
1280x1024@60 has waves so prefer 1280x1024@75.

Manufacturer: MED  Model: 7b8  Serial#: 99188
Year: 2005  Week: 5
EDID Version: 1.3
Analog Display Input,  Input Voltage Level: 0.700/0.700 V
Sync:  Separate
Max Image Size [cm]: horiz.: 34  vert.: 27
Gamma: 2.50
DPMS capabilities: Off; RGB/Color Display
First detailed timing is preferred mode
redX: 0.645 redY: 0.348   greenX: 0.280 greenY: 0.605
blueX: 0.142 blueY: 0.071   whiteX: 0.313 whiteY: 0.329
Supported established timings:
720x400@70Hz
640x480@60Hz
640x480@72Hz
640x480@75Hz
800x600@56Hz
800x600@60Hz
800x600@72Hz
800x600@75Hz
1024x768@60Hz
1024x768@70Hz
1024x768@75Hz
1280x1024@75Hz
Manufacturer's mask: 0
Supported standard timings:
Supported detailed timing:
clock: 25.2 MHz   Image Size:  337 x 270 mm
h_active: 640  h_sync: 688  h_sync_end 784 h_blank_end 800 h_border: 0
v_active: 350  v_sync: 350  v_sync_end 352 v_blanking: 449 v_border: 0
Monitor name: MD30217PG
Ranges: V min: 56 V max: 76 Hz, H min: 30 H max: 83 kHz, PixClock max 145 MHz
Serial No: 501099188
EDID (in hex):
          00ffffffffffff0034a4b80774830100
          050f010368221b962a0c55a559479b24
          125054afcf00310a0101010101018180
          000000000000d60980a0205e63103060
          0200510e1100001e000000fc004d4433
          3032313750470a202020000000fd0038
          4c1e530e000a202020202020000000ff
          003530313039393138380a2020200078

Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Reported-by: friedrich@mailstation.de
Cc: stable@vger.kernel.org
 2013-08-30 16:29:56 -04:00
Jakob Bornecrantz 6e4dcff3ad drm/vmwgfx: Split GMR2_REMAP commands if they are to large 
This fixes the piglit test texturing/max-texture-size
causing the VM to die due to a too large SVGA command.

Signed-off-by: Jakob Bornecrantz <jakob@vmware.com>
Reviewed-by: Biran Paul <brianp@vmware.com>
Reviewed-by: Zack Rusin <zackr@vmware.com>
Cc: stable@vger.kernel.org
Signed-off-by: Dave Airlie <airlied@gmail.com>
 2013-08-30 09:03:39 +10:00