2018-08-22 06:02:17 +08:00
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// SPDX-License-Identifier: GPL-2.0
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2011-03-23 19:42:44 +08:00
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/*
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2017-05-10 17:25:25 +08:00
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* Driver for the MMC / SD / SDIO IP found in:
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*
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* TC6393XB, TC6391XB, TC6387XB, T7L66XB, ASIC3, SH-Mobile SoCs
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2011-03-23 19:42:44 +08:00
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*
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2019-03-15 06:54:41 +08:00
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* Copyright (C) 2015-19 Renesas Electronics Corporation
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* Copyright (C) 2016-19 Sang Engineering, Wolfram Sang
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2017-05-30 20:50:52 +08:00
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* Copyright (C) 2017 Horms Solutions, Simon Horman
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2011-03-23 19:42:44 +08:00
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* Copyright (C) 2011 Guennadi Liakhovetski
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* Copyright (C) 2007 Ian Molton
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* Copyright (C) 2004 Ian Molton
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*
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* This driver draws mainly on scattered spec sheets, Reverse engineering
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* of the toshiba e800 SD driver and some parts of the 2.4 ASIC3 driver (4 bit
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* support). (Further 4 bit support from a later datasheet).
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*
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* TODO:
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* Investigate using a workqueue for PIO transfers
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* Eliminate FIXMEs
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* Better Power management
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* Handle MMC errors better
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* double buffer support
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*
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*/
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#include <linux/delay.h>
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#include <linux/device.h>
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#include <linux/highmem.h>
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#include <linux/interrupt.h>
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#include <linux/io.h>
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#include <linux/irq.h>
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#include <linux/mfd/tmio.h>
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2016-11-03 22:16:03 +08:00
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#include <linux/mmc/card.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/mmc/host.h>
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2012-06-21 01:10:35 +08:00
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#include <linux/mmc/mmc.h>
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2012-05-01 05:31:57 +08:00
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#include <linux/mmc/slot-gpio.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/module.h>
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#include <linux/pagemap.h>
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#include <linux/platform_device.h>
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2012-03-13 08:01:51 +08:00
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#include <linux/pm_qos.h>
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2011-05-06 00:13:12 +08:00
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#include <linux/pm_runtime.h>
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2013-02-15 23:14:00 +08:00
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#include <linux/regulator/consumer.h>
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2014-08-25 11:00:25 +08:00
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#include <linux/mmc/sdio.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/scatterlist.h>
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mmc: tmio: fix access width of Block Count Register
In R-Car Gen2 or later, the maximum number of transfer blocks are
changed from 0xFFFF to 0xFFFFFFFF. Therefore, Block Count Register
should use iowrite32().
If another system (U-boot, Hypervisor OS, etc) uses bit[31:16], this
value will not be cleared. So, SD/MMC card initialization fails.
So, check for the bigger register and use apropriate write. Also, mark
the register as extended on Gen2.
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: use max_blk_count in if(), add Gen2, update commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: stable@kernel.org
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
[Ulf: Fixed build error]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-22 03:38:05 +08:00
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#include <linux/sizes.h>
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2011-03-23 19:42:44 +08:00
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#include <linux/spinlock.h>
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2017-10-20 11:12:41 +08:00
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#include <linux/swiotlb.h>
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2012-01-06 20:06:51 +08:00
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#include <linux/workqueue.h>
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2011-03-23 19:42:44 +08:00
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#include "tmio_mmc.h"
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2017-05-10 17:25:26 +08:00
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static inline void tmio_mmc_start_dma(struct tmio_mmc_host *host,
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struct mmc_data *data)
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{
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if (host->dma_ops)
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host->dma_ops->start(host, data);
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}
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static inline void tmio_mmc_enable_dma(struct tmio_mmc_host *host, bool enable)
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{
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if (host->dma_ops)
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host->dma_ops->enable(host, enable);
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}
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static inline void tmio_mmc_request_dma(struct tmio_mmc_host *host,
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struct tmio_mmc_data *pdata)
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{
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if (host->dma_ops) {
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host->dma_ops->request(host, pdata);
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} else {
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host->chan_tx = NULL;
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host->chan_rx = NULL;
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}
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}
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static inline void tmio_mmc_release_dma(struct tmio_mmc_host *host)
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{
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if (host->dma_ops)
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host->dma_ops->release(host);
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}
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static inline void tmio_mmc_abort_dma(struct tmio_mmc_host *host)
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{
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if (host->dma_ops)
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host->dma_ops->abort(host);
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}
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2017-06-21 22:00:28 +08:00
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static inline void tmio_mmc_dataend_dma(struct tmio_mmc_host *host)
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{
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if (host->dma_ops)
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host->dma_ops->dataend(host);
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}
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2011-03-23 19:42:44 +08:00
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void tmio_mmc_enable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
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{
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2011-08-25 09:27:25 +08:00
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host->sdcard_irq_mask &= ~(i & TMIO_MASK_IRQ);
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2016-04-28 00:51:23 +08:00
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sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
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2011-03-23 19:42:44 +08:00
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}
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2017-05-30 20:50:51 +08:00
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EXPORT_SYMBOL_GPL(tmio_mmc_enable_mmc_irqs);
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2011-03-23 19:42:44 +08:00
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void tmio_mmc_disable_mmc_irqs(struct tmio_mmc_host *host, u32 i)
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{
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2011-08-25 09:27:25 +08:00
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host->sdcard_irq_mask |= (i & TMIO_MASK_IRQ);
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2016-04-28 00:51:23 +08:00
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sd_ctrl_write32_as_16_and_16(host, CTL_IRQ_MASK, host->sdcard_irq_mask);
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2011-03-23 19:42:44 +08:00
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}
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2017-05-30 20:50:51 +08:00
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EXPORT_SYMBOL_GPL(tmio_mmc_disable_mmc_irqs);
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2011-03-23 19:42:44 +08:00
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static void tmio_mmc_ack_mmc_irqs(struct tmio_mmc_host *host, u32 i)
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{
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2016-04-28 00:51:23 +08:00
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sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, ~i);
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2011-03-23 19:42:44 +08:00
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}
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static void tmio_mmc_init_sg(struct tmio_mmc_host *host, struct mmc_data *data)
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{
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host->sg_len = data->sg_len;
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host->sg_ptr = data->sg;
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host->sg_orig = data->sg;
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host->sg_off = 0;
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}
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static int tmio_mmc_next_sg(struct tmio_mmc_host *host)
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{
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host->sg_ptr = sg_next(host->sg_ptr);
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host->sg_off = 0;
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return --host->sg_len;
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}
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2015-07-20 00:39:59 +08:00
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#define CMDREQ_TIMEOUT 5000
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2011-03-23 19:42:44 +08:00
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static void tmio_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable)
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{
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struct tmio_mmc_host *host = mmc_priv(mmc);
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2013-10-24 21:58:45 +08:00
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if (enable && !host->sdio_irq_enabled) {
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2017-01-20 04:07:18 +08:00
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u16 sdio_status;
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2013-10-24 21:58:45 +08:00
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/* Keep device active while SDIO irq is enabled */
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pm_runtime_get_sync(mmc_dev(mmc));
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2017-01-20 04:07:18 +08:00
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host->sdio_irq_enabled = true;
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2017-06-17 00:11:03 +08:00
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host->sdio_irq_mask = TMIO_SDIO_MASK_ALL & ~TMIO_SDIO_STAT_IOIRQ;
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2017-01-20 04:07:18 +08:00
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/* Clear obsolete interrupts before enabling */
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sdio_status = sd_ctrl_read16(host, CTL_SDIO_STATUS) & ~TMIO_SDIO_MASK_ALL;
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if (host->pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS)
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sdio_status |= TMIO_SDIO_SETBITS_MASK;
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sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
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2011-08-25 09:27:25 +08:00
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sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
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2013-10-24 21:58:45 +08:00
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} else if (!enable && host->sdio_irq_enabled) {
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2011-08-25 09:27:25 +08:00
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host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
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sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
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2013-10-24 21:58:45 +08:00
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host->sdio_irq_enabled = false;
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2013-10-24 22:42:33 +08:00
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pm_runtime_mark_last_busy(mmc_dev(mmc));
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pm_runtime_put_autosuspend(mmc_dev(mmc));
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2011-03-23 19:42:44 +08:00
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}
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}
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static void tmio_mmc_reset(struct tmio_mmc_host *host)
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{
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/* FIXME - should we set stop clock reg here */
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0000);
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2017-11-03 17:36:28 +08:00
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usleep_range(10000, 11000);
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2011-03-23 19:42:44 +08:00
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sd_ctrl_write16(host, CTL_RESET_SD, 0x0001);
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2017-11-03 17:36:28 +08:00
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usleep_range(10000, 11000);
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2017-05-23 21:34:08 +08:00
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if (host->pdata->flags & TMIO_MMC_SDIO_IRQ) {
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sd_ctrl_write16(host, CTL_SDIO_IRQ_MASK, host->sdio_irq_mask);
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sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0001);
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}
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2011-03-23 19:42:44 +08:00
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}
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2018-11-27 01:02:46 +08:00
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static void tmio_mmc_hw_reset(struct mmc_host *mmc)
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{
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struct tmio_mmc_host *host = mmc_priv(mmc);
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host->reset(host);
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tmio_mmc_abort_dma(host);
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if (host->hw_reset)
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host->hw_reset(host);
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}
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2011-03-23 19:42:44 +08:00
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static void tmio_mmc_reset_work(struct work_struct *work)
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{
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struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
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delayed_reset_work.work);
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struct mmc_request *mrq;
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unsigned long flags;
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spin_lock_irqsave(&host->lock, flags);
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mrq = host->mrq;
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2011-04-21 15:20:16 +08:00
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/*
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* is request already finished? Since we use a non-blocking
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* cancel_delayed_work(), it can happen, that a .set_ios() call preempts
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* us, so, have to check for IS_ERR(host->mrq)
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*/
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2017-06-17 00:11:03 +08:00
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if (IS_ERR_OR_NULL(mrq) ||
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time_is_after_jiffies(host->last_req_ts +
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msecs_to_jiffies(CMDREQ_TIMEOUT))) {
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2011-03-23 19:42:44 +08:00
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spin_unlock_irqrestore(&host->lock, flags);
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return;
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}
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dev_warn(&host->pdev->dev,
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2017-06-17 00:11:03 +08:00
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"timeout waiting for hardware interrupt (CMD%u)\n",
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mrq->cmd->opcode);
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2011-03-23 19:42:44 +08:00
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if (host->data)
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host->data->error = -ETIMEDOUT;
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else if (host->cmd)
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host->cmd->error = -ETIMEDOUT;
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else
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mrq->cmd->error = -ETIMEDOUT;
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host->cmd = NULL;
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host->data = NULL;
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spin_unlock_irqrestore(&host->lock, flags);
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2018-11-27 01:02:46 +08:00
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tmio_mmc_hw_reset(host->mmc);
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2011-03-23 19:42:44 +08:00
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2011-04-21 15:20:16 +08:00
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/* Ready for new calls */
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host->mrq = NULL;
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2011-03-23 19:42:44 +08:00
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mmc_request_done(host->mmc, mrq);
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}
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/* These are the bitmasks the tmio chip requires to implement the MMC response
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* types. Note that R1 and R6 are the same in this scheme. */
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#define APP_CMD 0x0040
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#define RESP_NONE 0x0300
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#define RESP_R1 0x0400
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#define RESP_R1B 0x0500
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#define RESP_R2 0x0600
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#define RESP_R3 0x0700
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#define DATA_PRESENT 0x0800
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#define TRANSFER_READ 0x1000
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#define TRANSFER_MULTI 0x2000
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#define SECURITY_CMD 0x4000
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2014-08-25 11:00:25 +08:00
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#define NO_CMD12_ISSUE 0x4000 /* TMIO_MMC_HAVE_CMD12_CTRL */
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2011-03-23 19:42:44 +08:00
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2017-06-17 00:11:03 +08:00
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static int tmio_mmc_start_command(struct tmio_mmc_host *host,
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struct mmc_command *cmd)
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2011-03-23 19:42:44 +08:00
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{
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struct mmc_data *data = host->data;
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int c = cmd->opcode;
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switch (mmc_resp_type(cmd)) {
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case MMC_RSP_NONE: c |= RESP_NONE; break;
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2016-09-20 04:57:48 +08:00
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case MMC_RSP_R1:
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case MMC_RSP_R1_NO_CRC:
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c |= RESP_R1; break;
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2011-03-23 19:42:44 +08:00
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case MMC_RSP_R1B: c |= RESP_R1B; break;
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case MMC_RSP_R2: c |= RESP_R2; break;
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case MMC_RSP_R3: c |= RESP_R3; break;
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default:
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pr_debug("Unknown response type %d\n", mmc_resp_type(cmd));
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return -EINVAL;
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}
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host->cmd = cmd;
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/* FIXME - this seems to be ok commented out but the spec suggest this bit
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* should be set when issuing app commands.
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* if(cmd->flags & MMC_FLAG_ACMD)
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* c |= APP_CMD;
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*/
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if (data) {
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c |= DATA_PRESENT;
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if (data->blocks > 1) {
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2017-03-14 18:09:16 +08:00
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sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, TMIO_STOP_SEC);
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2011-03-23 19:42:44 +08:00
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c |= TRANSFER_MULTI;
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2014-08-25 11:00:25 +08:00
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/*
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2017-06-17 00:11:03 +08:00
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* Disable auto CMD12 at IO_RW_EXTENDED and
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* SET_BLOCK_COUNT when doing multiple block transfer
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2014-08-25 11:00:25 +08:00
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*/
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if ((host->pdata->flags & TMIO_MMC_HAVE_CMD12_CTRL) &&
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2017-05-19 21:31:54 +08:00
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(cmd->opcode == SD_IO_RW_EXTENDED || host->mrq->sbc))
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2014-08-25 11:00:25 +08:00
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|
|
c |= NO_CMD12_ISSUE;
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
if (data->flags & MMC_DATA_READ)
|
|
|
|
c |= TRANSFER_READ;
|
|
|
|
}
|
|
|
|
|
2018-07-25 16:46:14 +08:00
|
|
|
tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_CMD);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
/* Fire off the command */
|
2016-04-28 00:51:23 +08:00
|
|
|
sd_ctrl_write32_as_16_and_16(host, CTL_ARG_REG, cmd->arg);
|
2011-03-23 19:42:44 +08:00
|
|
|
sd_ctrl_write16(host, CTL_SD_CMD, c);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2014-09-10 15:23:24 +08:00
|
|
|
static void tmio_mmc_transfer_data(struct tmio_mmc_host *host,
|
|
|
|
unsigned short *buf,
|
|
|
|
unsigned int count)
|
|
|
|
{
|
|
|
|
int is_read = host->data->flags & MMC_DATA_READ;
|
|
|
|
u8 *buf8;
|
|
|
|
|
|
|
|
/*
|
|
|
|
* Transfer the data
|
|
|
|
*/
|
2016-09-12 22:15:06 +08:00
|
|
|
if (host->pdata->flags & TMIO_MMC_32BIT_DATA_PORT) {
|
2017-07-12 23:40:01 +08:00
|
|
|
u32 data = 0;
|
|
|
|
u32 *buf32 = (u32 *)buf;
|
2016-09-12 22:15:06 +08:00
|
|
|
|
|
|
|
if (is_read)
|
2017-07-12 23:40:01 +08:00
|
|
|
sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, buf32,
|
2016-09-12 22:15:06 +08:00
|
|
|
count >> 2);
|
|
|
|
else
|
2017-07-12 23:40:01 +08:00
|
|
|
sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, buf32,
|
2016-09-12 22:15:06 +08:00
|
|
|
count >> 2);
|
|
|
|
|
|
|
|
/* if count was multiple of 4 */
|
|
|
|
if (!(count & 0x3))
|
|
|
|
return;
|
|
|
|
|
2017-07-12 23:40:01 +08:00
|
|
|
buf32 += count >> 2;
|
2016-09-12 22:15:06 +08:00
|
|
|
count %= 4;
|
|
|
|
|
|
|
|
if (is_read) {
|
2017-07-12 23:40:01 +08:00
|
|
|
sd_ctrl_read32_rep(host, CTL_SD_DATA_PORT, &data, 1);
|
|
|
|
memcpy(buf32, &data, count);
|
2016-09-12 22:15:06 +08:00
|
|
|
} else {
|
2017-07-12 23:40:01 +08:00
|
|
|
memcpy(&data, buf32, count);
|
|
|
|
sd_ctrl_write32_rep(host, CTL_SD_DATA_PORT, &data, 1);
|
2016-09-12 22:15:06 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2014-09-10 15:23:24 +08:00
|
|
|
if (is_read)
|
|
|
|
sd_ctrl_read16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
|
|
|
|
else
|
|
|
|
sd_ctrl_write16_rep(host, CTL_SD_DATA_PORT, buf, count >> 1);
|
|
|
|
|
|
|
|
/* if count was even number */
|
|
|
|
if (!(count & 0x1))
|
|
|
|
return;
|
|
|
|
|
|
|
|
/* if count was odd number */
|
|
|
|
buf8 = (u8 *)(buf + (count >> 1));
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME
|
|
|
|
*
|
|
|
|
* driver and this function are assuming that
|
|
|
|
* it is used as little endian
|
|
|
|
*/
|
|
|
|
if (is_read)
|
|
|
|
*buf8 = sd_ctrl_read16(host, CTL_SD_DATA_PORT) & 0xff;
|
|
|
|
else
|
|
|
|
sd_ctrl_write16(host, CTL_SD_DATA_PORT, *buf8);
|
|
|
|
}
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
/*
|
|
|
|
* This chip always returns (at least?) as much data as you ask for.
|
|
|
|
* I'm unsure what happens if you ask for less than a block. This should be
|
2011-03-31 09:57:33 +08:00
|
|
|
* looked into to ensure that a funny length read doesn't hose the controller.
|
2011-03-23 19:42:44 +08:00
|
|
|
*/
|
|
|
|
static void tmio_mmc_pio_irq(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
void *sg_virt;
|
|
|
|
unsigned short *buf;
|
|
|
|
unsigned int count;
|
|
|
|
unsigned long flags;
|
|
|
|
|
2018-10-12 23:03:08 +08:00
|
|
|
if (host->dma_on) {
|
2011-03-23 19:42:44 +08:00
|
|
|
pr_err("PIO IRQ in DMA mode!\n");
|
|
|
|
return;
|
|
|
|
} else if (!data) {
|
|
|
|
pr_debug("Spurious PIO IRQ\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
sg_virt = tmio_mmc_kmap_atomic(host->sg_ptr, &flags);
|
|
|
|
buf = (unsigned short *)(sg_virt + host->sg_off);
|
|
|
|
|
|
|
|
count = host->sg_ptr->length - host->sg_off;
|
|
|
|
if (count > data->blksz)
|
|
|
|
count = data->blksz;
|
|
|
|
|
|
|
|
pr_debug("count: %08x offset: %08x flags %08x\n",
|
|
|
|
count, host->sg_off, data->flags);
|
|
|
|
|
|
|
|
/* Transfer the data */
|
2014-09-10 15:23:24 +08:00
|
|
|
tmio_mmc_transfer_data(host, buf, count);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
host->sg_off += count;
|
|
|
|
|
|
|
|
tmio_mmc_kunmap_atomic(host->sg_ptr, &flags, sg_virt);
|
|
|
|
|
|
|
|
if (host->sg_off == host->sg_ptr->length)
|
|
|
|
tmio_mmc_next_sg(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_check_bounce_buffer(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
if (host->sg_ptr == &host->bounce_sg) {
|
|
|
|
unsigned long flags;
|
|
|
|
void *sg_vaddr = tmio_mmc_kmap_atomic(host->sg_orig, &flags);
|
2017-06-17 00:11:03 +08:00
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
memcpy(sg_vaddr, host->bounce_buf, host->bounce_sg.length);
|
|
|
|
tmio_mmc_kunmap_atomic(host->sg_orig, &flags, sg_vaddr);
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
/* needs to be called with host->lock held */
|
|
|
|
void tmio_mmc_do_data_irq(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_data *data = host->data;
|
|
|
|
struct mmc_command *stop;
|
|
|
|
|
|
|
|
host->data = NULL;
|
|
|
|
|
|
|
|
if (!data) {
|
|
|
|
dev_warn(&host->pdev->dev, "Spurious data end IRQ\n");
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
stop = data->stop;
|
|
|
|
|
|
|
|
/* FIXME - return correct transfer count on errors */
|
|
|
|
if (!data->error)
|
|
|
|
data->bytes_xfered = data->blocks * data->blksz;
|
|
|
|
else
|
|
|
|
data->bytes_xfered = 0;
|
|
|
|
|
|
|
|
pr_debug("Completed data request\n");
|
|
|
|
|
|
|
|
/*
|
|
|
|
* FIXME: other drivers allow an optional stop command of any given type
|
|
|
|
* which we dont do, as the chip can auto generate them.
|
|
|
|
* Perhaps we can be smarter about when to use auto CMD12 and
|
|
|
|
* only issue the auto request when we know this is the desired
|
|
|
|
* stop command, allowing fallback to the stop command the
|
|
|
|
* upper layers expect. For now, we do what works.
|
|
|
|
*/
|
|
|
|
|
|
|
|
if (data->flags & MMC_DATA_READ) {
|
2018-10-12 23:03:08 +08:00
|
|
|
if (host->dma_on)
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_check_bounce_buffer(host);
|
|
|
|
dev_dbg(&host->pdev->dev, "Complete Rx request %p\n",
|
|
|
|
host->mrq);
|
|
|
|
} else {
|
|
|
|
dev_dbg(&host->pdev->dev, "Complete Tx request %p\n",
|
|
|
|
host->mrq);
|
|
|
|
}
|
|
|
|
|
2017-05-19 21:31:54 +08:00
|
|
|
if (stop && !host->mrq->sbc) {
|
2017-03-14 18:09:18 +08:00
|
|
|
if (stop->opcode != MMC_STOP_TRANSMISSION || stop->arg)
|
|
|
|
dev_err(&host->pdev->dev, "unsupported stop: CMD%u,0x%x. We did CMD12,0\n",
|
|
|
|
stop->opcode, stop->arg);
|
|
|
|
|
2017-03-14 18:09:19 +08:00
|
|
|
/* fill in response from auto CMD12 */
|
|
|
|
stop->resp[0] = sd_ctrl_read16_and_16_as_32(host, CTL_RESPONSE);
|
|
|
|
|
2017-03-14 18:09:18 +08:00
|
|
|
sd_ctrl_write16(host, CTL_STOP_INTERNAL_ACTION, 0);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
2011-07-14 18:12:38 +08:00
|
|
|
schedule_work(&host->done);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_do_data_irq);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2016-11-03 22:16:00 +08:00
|
|
|
static void tmio_mmc_data_irq(struct tmio_mmc_host *host, unsigned int stat)
|
2011-03-23 19:42:44 +08:00
|
|
|
{
|
|
|
|
struct mmc_data *data;
|
2017-06-17 00:11:03 +08:00
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
spin_lock(&host->lock);
|
|
|
|
data = host->data;
|
|
|
|
|
|
|
|
if (!data)
|
|
|
|
goto out;
|
|
|
|
|
2016-11-03 22:16:00 +08:00
|
|
|
if (stat & TMIO_STAT_CRCFAIL || stat & TMIO_STAT_STOPBIT_ERR ||
|
|
|
|
stat & TMIO_STAT_TXUNDERRUN)
|
|
|
|
data->error = -EILSEQ;
|
2018-10-12 23:03:08 +08:00
|
|
|
if (host->dma_on && (data->flags & MMC_DATA_WRITE)) {
|
2016-04-28 00:51:23 +08:00
|
|
|
u32 status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
|
2014-08-25 11:01:32 +08:00
|
|
|
bool done = false;
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
/*
|
|
|
|
* Has all data been written out yet? Testing on SuperH showed,
|
|
|
|
* that in most cases the first interrupt comes already with the
|
|
|
|
* BUSY status bit clear, but on some operations, like mount or
|
|
|
|
* in the beginning of a write / sync / umount, there is one
|
|
|
|
* DATAEND interrupt with the BUSY bit set, in this cases
|
|
|
|
* waiting for one more interrupt fixes the problem.
|
|
|
|
*/
|
2014-08-25 11:01:32 +08:00
|
|
|
if (host->pdata->flags & TMIO_MMC_HAS_IDLE_WAIT) {
|
2016-04-28 00:51:26 +08:00
|
|
|
if (status & TMIO_STAT_SCLKDIVEN)
|
2014-08-25 11:01:32 +08:00
|
|
|
done = true;
|
|
|
|
} else {
|
|
|
|
if (!(status & TMIO_STAT_CMD_BUSY))
|
|
|
|
done = true;
|
|
|
|
}
|
|
|
|
|
|
|
|
if (done) {
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
|
2017-06-21 22:00:28 +08:00
|
|
|
tmio_mmc_dataend_dma(host);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2018-10-12 23:03:08 +08:00
|
|
|
} else if (host->dma_on && (data->flags & MMC_DATA_READ)) {
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_disable_mmc_irqs(host, TMIO_STAT_DATAEND);
|
2017-06-21 22:00:28 +08:00
|
|
|
tmio_mmc_dataend_dma(host);
|
2011-03-23 19:42:44 +08:00
|
|
|
} else {
|
|
|
|
tmio_mmc_do_data_irq(host);
|
|
|
|
tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_READOP | TMIO_MASK_WRITEOP);
|
|
|
|
}
|
|
|
|
out:
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
}
|
|
|
|
|
2017-06-17 00:11:03 +08:00
|
|
|
static void tmio_mmc_cmd_irq(struct tmio_mmc_host *host, unsigned int stat)
|
2011-03-23 19:42:44 +08:00
|
|
|
{
|
|
|
|
struct mmc_command *cmd = host->cmd;
|
|
|
|
int i, addr;
|
|
|
|
|
|
|
|
spin_lock(&host->lock);
|
|
|
|
|
|
|
|
if (!host->cmd) {
|
|
|
|
pr_debug("Spurious CMD irq\n");
|
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
/* This controller is sicker than the PXA one. Not only do we need to
|
|
|
|
* drop the top 8 bits of the first response word, we also need to
|
|
|
|
* modify the order of the response for short response command types.
|
|
|
|
*/
|
|
|
|
|
|
|
|
for (i = 3, addr = CTL_RESPONSE ; i >= 0 ; i--, addr += 4)
|
2016-04-28 00:51:23 +08:00
|
|
|
cmd->resp[i] = sd_ctrl_read16_and_16_as_32(host, addr);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
if (cmd->flags & MMC_RSP_136) {
|
|
|
|
cmd->resp[0] = (cmd->resp[0] << 8) | (cmd->resp[1] >> 24);
|
|
|
|
cmd->resp[1] = (cmd->resp[1] << 8) | (cmd->resp[2] >> 24);
|
|
|
|
cmd->resp[2] = (cmd->resp[2] << 8) | (cmd->resp[3] >> 24);
|
|
|
|
cmd->resp[3] <<= 8;
|
|
|
|
} else if (cmd->flags & MMC_RSP_R3) {
|
|
|
|
cmd->resp[0] = cmd->resp[3];
|
|
|
|
}
|
|
|
|
|
|
|
|
if (stat & TMIO_STAT_CMDTIMEOUT)
|
|
|
|
cmd->error = -ETIMEDOUT;
|
2016-11-03 22:16:00 +08:00
|
|
|
else if ((stat & TMIO_STAT_CRCFAIL && cmd->flags & MMC_RSP_CRC) ||
|
|
|
|
stat & TMIO_STAT_STOPBIT_ERR ||
|
|
|
|
stat & TMIO_STAT_CMD_IDX_ERR)
|
2011-03-23 19:42:44 +08:00
|
|
|
cmd->error = -EILSEQ;
|
|
|
|
|
|
|
|
/* If there is data to handle we enable data IRQs here, and
|
|
|
|
* we will ultimatley finish the request in the data_end handler.
|
|
|
|
* If theres no data or we encountered an error, finish now.
|
|
|
|
*/
|
2016-11-03 22:16:00 +08:00
|
|
|
if (host->data && (!cmd->error || cmd->error == -EILSEQ)) {
|
2011-03-23 19:42:44 +08:00
|
|
|
if (host->data->flags & MMC_DATA_READ) {
|
2018-10-12 23:03:08 +08:00
|
|
|
if (!host->dma_on) {
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_READOP);
|
mmc: tmio: move TMIO_MASK_{READOP, WRITEOP} handling to correct place
As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ}
are asserted for DMA mode as well as for PIO. I need to disable the
those IRQs in dma_ops->start hook, otherwise the DMA transfer fails
with the following error message:
PIO IRQ in DMA mode!
Renesas chips are the same cases since I see their dma_ops->start
hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!).
If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling
should be entirely moved to the core. tmio_mmc_cmd_irq() will
be a suitable place to disable them.
The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd.
/* Unmask the IRQs we want to know about */
if (!_host->chan_rx)
irq_mask |= TMIO_MASK_READOP;
if (!_host->chan_tx)
irq_mask |= TMIO_MASK_WRITEOP;
At this point, _host->{chan_rx,chan_tx} are _always_ NULL because
tmio_mmc_request_dma() is called after this code. Consequently,
TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not.
Remove this pointless code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2018-01-18 00:28:14 +08:00
|
|
|
} else {
|
|
|
|
tmio_mmc_disable_mmc_irqs(host,
|
|
|
|
TMIO_MASK_READOP);
|
2011-03-23 19:42:44 +08:00
|
|
|
tasklet_schedule(&host->dma_issue);
|
mmc: tmio: move TMIO_MASK_{READOP, WRITEOP} handling to correct place
As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ}
are asserted for DMA mode as well as for PIO. I need to disable the
those IRQs in dma_ops->start hook, otherwise the DMA transfer fails
with the following error message:
PIO IRQ in DMA mode!
Renesas chips are the same cases since I see their dma_ops->start
hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!).
If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling
should be entirely moved to the core. tmio_mmc_cmd_irq() will
be a suitable place to disable them.
The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd.
/* Unmask the IRQs we want to know about */
if (!_host->chan_rx)
irq_mask |= TMIO_MASK_READOP;
if (!_host->chan_tx)
irq_mask |= TMIO_MASK_WRITEOP;
At this point, _host->{chan_rx,chan_tx} are _always_ NULL because
tmio_mmc_request_dma() is called after this code. Consequently,
TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not.
Remove this pointless code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2018-01-18 00:28:14 +08:00
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
} else {
|
2018-10-12 23:03:08 +08:00
|
|
|
if (!host->dma_on) {
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_enable_mmc_irqs(host, TMIO_MASK_WRITEOP);
|
mmc: tmio: move TMIO_MASK_{READOP, WRITEOP} handling to correct place
As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ}
are asserted for DMA mode as well as for PIO. I need to disable the
those IRQs in dma_ops->start hook, otherwise the DMA transfer fails
with the following error message:
PIO IRQ in DMA mode!
Renesas chips are the same cases since I see their dma_ops->start
hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!).
If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling
should be entirely moved to the core. tmio_mmc_cmd_irq() will
be a suitable place to disable them.
The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd.
/* Unmask the IRQs we want to know about */
if (!_host->chan_rx)
irq_mask |= TMIO_MASK_READOP;
if (!_host->chan_tx)
irq_mask |= TMIO_MASK_WRITEOP;
At this point, _host->{chan_rx,chan_tx} are _always_ NULL because
tmio_mmc_request_dma() is called after this code. Consequently,
TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not.
Remove this pointless code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2018-01-18 00:28:14 +08:00
|
|
|
} else {
|
|
|
|
tmio_mmc_disable_mmc_irqs(host,
|
|
|
|
TMIO_MASK_WRITEOP);
|
2011-03-23 19:42:44 +08:00
|
|
|
tasklet_schedule(&host->dma_issue);
|
mmc: tmio: move TMIO_MASK_{READOP, WRITEOP} handling to correct place
As far as I tested the IP on UniPhier SoCs, TMIO_STAT_{RXRDY,TXRQ}
are asserted for DMA mode as well as for PIO. I need to disable the
those IRQs in dma_ops->start hook, otherwise the DMA transfer fails
with the following error message:
PIO IRQ in DMA mode!
Renesas chips are the same cases since I see their dma_ops->start
hooks explicitly clear TMIO_STAT_{RXRDY,TXRQ} (with nice comment!).
If we do this sanity check in TMIO MMC core, RXRDY/TXRQ handling
should be entirely moved to the core. tmio_mmc_cmd_irq() will
be a suitable place to disable them.
The probe function sets TMIO_MASK_{READOP,WRITEOP} but this is odd.
/* Unmask the IRQs we want to know about */
if (!_host->chan_rx)
irq_mask |= TMIO_MASK_READOP;
if (!_host->chan_tx)
irq_mask |= TMIO_MASK_WRITEOP;
At this point, _host->{chan_rx,chan_tx} are _always_ NULL because
tmio_mmc_request_dma() is called after this code. Consequently,
TMIO_MASK_{READOP,WRITEOP} are set here whether DMA is used or not.
Remove this pointless code.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Tested-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
2018-01-18 00:28:14 +08:00
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
} else {
|
2011-07-14 18:12:38 +08:00
|
|
|
schedule_work(&host->done);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
out:
|
|
|
|
spin_unlock(&host->lock);
|
|
|
|
}
|
|
|
|
|
2011-08-25 09:27:26 +08:00
|
|
|
static bool __tmio_mmc_card_detect_irq(struct tmio_mmc_host *host,
|
2017-06-17 00:11:03 +08:00
|
|
|
int ireg, int status)
|
2011-08-25 09:27:26 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2011-05-15 21:24:41 +08:00
|
|
|
/* Card insert / remove attempts */
|
|
|
|
if (ireg & (TMIO_STAT_CARD_INSERT | TMIO_STAT_CARD_REMOVE)) {
|
|
|
|
tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CARD_INSERT |
|
|
|
|
TMIO_STAT_CARD_REMOVE);
|
2011-07-14 18:16:59 +08:00
|
|
|
if ((((ireg & TMIO_STAT_CARD_REMOVE) && mmc->card) ||
|
|
|
|
((ireg & TMIO_STAT_CARD_INSERT) && !mmc->card)) &&
|
|
|
|
!work_pending(&mmc->detect.work))
|
2011-07-14 18:12:38 +08:00
|
|
|
mmc_detect_change(host->mmc, msecs_to_jiffies(100));
|
2011-08-25 09:27:26 +08:00
|
|
|
return true;
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
2011-08-25 09:27:26 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2017-06-17 00:11:03 +08:00
|
|
|
static bool __tmio_mmc_sdcard_irq(struct tmio_mmc_host *host, int ireg,
|
|
|
|
int status)
|
2011-08-25 09:27:26 +08:00
|
|
|
{
|
2011-05-15 21:24:41 +08:00
|
|
|
/* Command completion */
|
|
|
|
if (ireg & (TMIO_STAT_CMDRESPEND | TMIO_STAT_CMDTIMEOUT)) {
|
2017-06-17 00:11:03 +08:00
|
|
|
tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_CMDRESPEND |
|
|
|
|
TMIO_STAT_CMDTIMEOUT);
|
2011-05-15 21:24:41 +08:00
|
|
|
tmio_mmc_cmd_irq(host, status);
|
2011-08-25 09:27:26 +08:00
|
|
|
return true;
|
2011-05-15 21:24:41 +08:00
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2011-05-15 21:24:41 +08:00
|
|
|
/* Data transfer */
|
|
|
|
if (ireg & (TMIO_STAT_RXRDY | TMIO_STAT_TXRQ)) {
|
|
|
|
tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_RXRDY | TMIO_STAT_TXRQ);
|
|
|
|
tmio_mmc_pio_irq(host);
|
2011-08-25 09:27:26 +08:00
|
|
|
return true;
|
2011-05-15 21:24:41 +08:00
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2011-05-15 21:24:41 +08:00
|
|
|
/* Data transfer completion */
|
|
|
|
if (ireg & TMIO_STAT_DATAEND) {
|
|
|
|
tmio_mmc_ack_mmc_irqs(host, TMIO_STAT_DATAEND);
|
2016-11-03 22:16:00 +08:00
|
|
|
tmio_mmc_data_irq(host, status);
|
2011-08-25 09:27:26 +08:00
|
|
|
return true;
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2011-05-15 21:24:41 +08:00
|
|
|
|
2011-08-25 09:27:26 +08:00
|
|
|
return false;
|
|
|
|
}
|
|
|
|
|
2019-02-19 01:45:40 +08:00
|
|
|
static bool __tmio_mmc_sdio_irq(struct tmio_mmc_host *host)
|
2011-08-25 09:27:26 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
struct tmio_mmc_data *pdata = host->pdata;
|
|
|
|
unsigned int ireg, status;
|
2014-08-25 11:00:52 +08:00
|
|
|
unsigned int sdio_status;
|
2011-08-25 09:27:26 +08:00
|
|
|
|
|
|
|
if (!(pdata->flags & TMIO_MMC_SDIO_IRQ))
|
2019-02-19 01:45:40 +08:00
|
|
|
return false;
|
2011-08-25 09:27:26 +08:00
|
|
|
|
|
|
|
status = sd_ctrl_read16(host, CTL_SDIO_STATUS);
|
2016-11-13 22:29:11 +08:00
|
|
|
ireg = status & TMIO_SDIO_MASK_ALL & ~host->sdio_irq_mask;
|
2011-08-25 09:27:26 +08:00
|
|
|
|
2014-08-25 11:00:52 +08:00
|
|
|
sdio_status = status & ~TMIO_SDIO_MASK_ALL;
|
2017-01-20 04:07:17 +08:00
|
|
|
if (pdata->flags & TMIO_MMC_SDIO_STATUS_SETBITS)
|
2017-01-20 04:07:18 +08:00
|
|
|
sdio_status |= TMIO_SDIO_SETBITS_MASK;
|
2014-08-25 11:00:52 +08:00
|
|
|
|
|
|
|
sd_ctrl_write16(host, CTL_SDIO_STATUS, sdio_status);
|
2011-08-25 09:27:26 +08:00
|
|
|
|
|
|
|
if (mmc->caps & MMC_CAP_SDIO_IRQ && ireg & TMIO_SDIO_STAT_IOIRQ)
|
|
|
|
mmc_signal_sdio_irq(mmc);
|
2019-02-19 01:45:40 +08:00
|
|
|
|
|
|
|
return ireg;
|
2011-08-25 09:27:26 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
irqreturn_t tmio_mmc_irq(int irq, void *devid)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = devid;
|
|
|
|
unsigned int ireg, status;
|
|
|
|
|
2016-04-28 00:51:23 +08:00
|
|
|
status = sd_ctrl_read16_and_16_as_32(host, CTL_STATUS);
|
2016-04-26 23:55:25 +08:00
|
|
|
ireg = status & TMIO_MASK_IRQ & ~host->sdcard_irq_mask;
|
|
|
|
|
|
|
|
/* Clear the status except the interrupt status */
|
2016-04-28 00:51:23 +08:00
|
|
|
sd_ctrl_write32_as_16_and_16(host, CTL_STATUS, TMIO_MASK_IRQ);
|
2011-08-25 09:27:26 +08:00
|
|
|
|
|
|
|
if (__tmio_mmc_card_detect_irq(host, ireg, status))
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
if (__tmio_mmc_sdcard_irq(host, ireg, status))
|
|
|
|
return IRQ_HANDLED;
|
|
|
|
|
2019-02-19 01:45:40 +08:00
|
|
|
if (__tmio_mmc_sdio_irq(host))
|
|
|
|
return IRQ_HANDLED;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2019-02-19 01:45:40 +08:00
|
|
|
return IRQ_NONE;
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_irq);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
static int tmio_mmc_start_data(struct tmio_mmc_host *host,
|
2017-06-17 00:11:03 +08:00
|
|
|
struct mmc_data *data)
|
2011-03-23 19:42:44 +08:00
|
|
|
{
|
|
|
|
struct tmio_mmc_data *pdata = host->pdata;
|
|
|
|
|
|
|
|
pr_debug("setup data transfer: blocksize %08x nr_blocks %d\n",
|
|
|
|
data->blksz, data->blocks);
|
|
|
|
|
2016-09-20 04:57:48 +08:00
|
|
|
/* Some hardware cannot perform 2 byte requests in 4/8 bit mode */
|
|
|
|
if (host->mmc->ios.bus_width == MMC_BUS_WIDTH_4 ||
|
|
|
|
host->mmc->ios.bus_width == MMC_BUS_WIDTH_8) {
|
2011-03-23 19:42:44 +08:00
|
|
|
int blksz_2bytes = pdata->flags & TMIO_MMC_BLKSZ_2BYTES;
|
|
|
|
|
|
|
|
if (data->blksz < 2 || (data->blksz < 4 && !blksz_2bytes)) {
|
2016-09-20 04:57:48 +08:00
|
|
|
pr_err("%s: %d byte block unsupported in 4/8 bit mode\n",
|
2011-03-23 19:42:44 +08:00
|
|
|
mmc_hostname(host->mmc), data->blksz);
|
|
|
|
return -EINVAL;
|
|
|
|
}
|
|
|
|
}
|
|
|
|
|
|
|
|
tmio_mmc_init_sg(host, data);
|
|
|
|
host->data = data;
|
2018-10-12 23:03:08 +08:00
|
|
|
host->dma_on = false;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
/* Set transfer length / blocksize */
|
|
|
|
sd_ctrl_write16(host, CTL_SD_XFER_LEN, data->blksz);
|
mmc: tmio: fix access width of Block Count Register
In R-Car Gen2 or later, the maximum number of transfer blocks are
changed from 0xFFFF to 0xFFFFFFFF. Therefore, Block Count Register
should use iowrite32().
If another system (U-boot, Hypervisor OS, etc) uses bit[31:16], this
value will not be cleared. So, SD/MMC card initialization fails.
So, check for the bigger register and use apropriate write. Also, mark
the register as extended on Gen2.
Signed-off-by: Takeshi Saito <takeshi.saito.xv@renesas.com>
[wsa: use max_blk_count in if(), add Gen2, update commit message]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Cc: stable@kernel.org
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
[Ulf: Fixed build error]
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-02-22 03:38:05 +08:00
|
|
|
if (host->mmc->max_blk_count >= SZ_64K)
|
|
|
|
sd_ctrl_write32(host, CTL_XFER_BLK_COUNT, data->blocks);
|
|
|
|
else
|
|
|
|
sd_ctrl_write16(host, CTL_XFER_BLK_COUNT, data->blocks);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
tmio_mmc_start_dma(host, data);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
2016-11-03 22:16:03 +08:00
|
|
|
static int tmio_mmc_execute_tuning(struct mmc_host *mmc, u32 opcode)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
int i, ret = 0;
|
|
|
|
|
2017-03-17 17:04:50 +08:00
|
|
|
if (!host->init_tuning || !host->select_tuning)
|
|
|
|
/* Tuning is not supported */
|
|
|
|
goto out;
|
2016-11-03 22:16:03 +08:00
|
|
|
|
2017-03-17 17:04:50 +08:00
|
|
|
host->tap_num = host->init_tuning(host);
|
|
|
|
if (!host->tap_num)
|
|
|
|
/* Tuning is not supported */
|
|
|
|
goto out;
|
2016-11-03 22:16:03 +08:00
|
|
|
|
|
|
|
if (host->tap_num * 2 >= sizeof(host->taps) * BITS_PER_BYTE) {
|
|
|
|
dev_warn_once(&host->pdev->dev,
|
2017-06-17 00:11:03 +08:00
|
|
|
"Too many taps, skipping tuning. Please consider updating size of taps field of tmio_mmc_host\n");
|
2016-11-03 22:16:03 +08:00
|
|
|
goto out;
|
|
|
|
}
|
|
|
|
|
|
|
|
bitmap_zero(host->taps, host->tap_num * 2);
|
|
|
|
|
|
|
|
/* Issue CMD19 twice for each tap */
|
|
|
|
for (i = 0; i < 2 * host->tap_num; i++) {
|
|
|
|
if (host->prepare_tuning)
|
|
|
|
host->prepare_tuning(host, i % host->tap_num);
|
|
|
|
|
|
|
|
ret = mmc_send_tuning(mmc, opcode, NULL);
|
|
|
|
if (ret == 0)
|
|
|
|
set_bit(i, host->taps);
|
|
|
|
}
|
|
|
|
|
|
|
|
ret = host->select_tuning(host);
|
|
|
|
|
|
|
|
out:
|
|
|
|
if (ret < 0) {
|
|
|
|
dev_warn(&host->pdev->dev, "Tuning procedure failed\n");
|
|
|
|
tmio_mmc_hw_reset(mmc);
|
|
|
|
}
|
|
|
|
|
|
|
|
return ret;
|
|
|
|
}
|
|
|
|
|
2017-06-17 00:11:03 +08:00
|
|
|
static void tmio_process_mrq(struct tmio_mmc_host *host,
|
|
|
|
struct mmc_request *mrq)
|
2017-05-19 21:31:51 +08:00
|
|
|
{
|
2017-05-19 21:31:54 +08:00
|
|
|
struct mmc_command *cmd;
|
2017-05-19 21:31:51 +08:00
|
|
|
int ret;
|
|
|
|
|
2017-05-19 21:31:54 +08:00
|
|
|
if (mrq->sbc && host->cmd != mrq->sbc) {
|
|
|
|
cmd = mrq->sbc;
|
|
|
|
} else {
|
|
|
|
cmd = mrq->cmd;
|
|
|
|
if (mrq->data) {
|
|
|
|
ret = tmio_mmc_start_data(host, mrq->data);
|
|
|
|
if (ret)
|
|
|
|
goto fail;
|
|
|
|
}
|
2017-05-19 21:31:51 +08:00
|
|
|
}
|
|
|
|
|
2017-05-19 21:31:54 +08:00
|
|
|
ret = tmio_mmc_start_command(host, cmd);
|
2017-05-19 21:31:51 +08:00
|
|
|
if (ret)
|
|
|
|
goto fail;
|
|
|
|
|
|
|
|
schedule_delayed_work(&host->delayed_reset_work,
|
|
|
|
msecs_to_jiffies(CMDREQ_TIMEOUT));
|
|
|
|
return;
|
|
|
|
|
|
|
|
fail:
|
|
|
|
host->mrq = NULL;
|
|
|
|
mrq->cmd->error = ret;
|
|
|
|
mmc_request_done(host->mmc, mrq);
|
|
|
|
}
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
/* Process requests from the MMC layer */
|
|
|
|
static void tmio_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
2011-04-21 15:20:16 +08:00
|
|
|
unsigned long flags;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2011-04-21 15:20:16 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
if (host->mrq) {
|
2011-03-23 19:42:44 +08:00
|
|
|
pr_debug("request not null\n");
|
2011-04-21 15:20:16 +08:00
|
|
|
if (IS_ERR(host->mrq)) {
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
mrq->cmd->error = -EAGAIN;
|
|
|
|
mmc_request_done(mmc, mrq);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
host->last_req_ts = jiffies;
|
|
|
|
wmb();
|
|
|
|
host->mrq = mrq;
|
|
|
|
|
2011-04-21 15:20:16 +08:00
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
2017-05-19 21:31:51 +08:00
|
|
|
tmio_process_mrq(host, mrq);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
2017-05-19 21:31:53 +08:00
|
|
|
static void tmio_mmc_finish_request(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_request *mrq;
|
|
|
|
unsigned long flags;
|
|
|
|
|
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
|
|
|
|
mrq = host->mrq;
|
|
|
|
if (IS_ERR_OR_NULL(mrq)) {
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-05-19 21:31:54 +08:00
|
|
|
/* If not SET_BLOCK_COUNT, clear old data */
|
|
|
|
if (host->cmd != mrq->sbc) {
|
|
|
|
host->cmd = NULL;
|
|
|
|
host->data = NULL;
|
|
|
|
host->mrq = NULL;
|
|
|
|
}
|
2017-05-19 21:31:53 +08:00
|
|
|
|
|
|
|
cancel_delayed_work(&host->delayed_reset_work);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
|
|
|
|
|
|
|
if (mrq->cmd->error || (mrq->data && mrq->data->error))
|
|
|
|
tmio_mmc_abort_dma(host);
|
|
|
|
|
2018-08-30 07:32:07 +08:00
|
|
|
if (host->check_scc_error && host->check_scc_error(host))
|
|
|
|
mrq->cmd->error = -EILSEQ;
|
2017-05-19 21:31:53 +08:00
|
|
|
|
2017-05-19 21:31:54 +08:00
|
|
|
/* If SET_BLOCK_COUNT, continue with main command */
|
2018-04-04 05:57:03 +08:00
|
|
|
if (host->mrq && !mrq->cmd->error) {
|
2017-05-19 21:31:54 +08:00
|
|
|
tmio_process_mrq(host, mrq);
|
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
2017-05-19 21:31:53 +08:00
|
|
|
mmc_request_done(host->mmc, mrq);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_done_work(struct work_struct *work)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = container_of(work, struct tmio_mmc_host,
|
|
|
|
done);
|
|
|
|
tmio_mmc_finish_request(host);
|
|
|
|
}
|
|
|
|
|
2013-02-15 23:14:00 +08:00
|
|
|
static void tmio_mmc_power_on(struct tmio_mmc_host *host, unsigned short vdd)
|
2012-06-21 01:10:33 +08:00
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
2013-02-15 23:14:00 +08:00
|
|
|
int ret = 0;
|
|
|
|
|
|
|
|
/* .set_ios() is returning void, so, no chance to report an error */
|
2012-06-21 01:10:33 +08:00
|
|
|
|
2013-09-06 19:29:05 +08:00
|
|
|
if (host->set_pwr)
|
|
|
|
host->set_pwr(host->pdev, 1);
|
|
|
|
|
2013-02-15 23:14:00 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vmmc)) {
|
|
|
|
ret = mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd);
|
|
|
|
/*
|
|
|
|
* Attention: empiric value. With a b43 WiFi SDIO card this
|
|
|
|
* delay proved necessary for reliable card-insertion probing.
|
|
|
|
* 100us were not enough. Is this the same 140us delay, as in
|
|
|
|
* tmio_mmc_set_ios()?
|
|
|
|
*/
|
2017-11-15 06:51:04 +08:00
|
|
|
usleep_range(200, 300);
|
2013-02-15 23:14:00 +08:00
|
|
|
}
|
|
|
|
/*
|
|
|
|
* It seems, VccQ should be switched on after Vcc, this is also what the
|
|
|
|
* omap_hsmmc.c driver does.
|
|
|
|
*/
|
|
|
|
if (!IS_ERR(mmc->supply.vqmmc) && !ret) {
|
2013-07-08 17:38:09 +08:00
|
|
|
ret = regulator_enable(mmc->supply.vqmmc);
|
2017-11-15 06:51:04 +08:00
|
|
|
usleep_range(200, 300);
|
2013-02-15 23:14:00 +08:00
|
|
|
}
|
2013-07-08 17:38:09 +08:00
|
|
|
|
|
|
|
if (ret < 0)
|
|
|
|
dev_dbg(&host->pdev->dev, "Regulators failed to power up: %d\n",
|
|
|
|
ret);
|
2013-02-15 23:14:00 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_power_off(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
|
|
|
if (!IS_ERR(mmc->supply.vqmmc))
|
|
|
|
regulator_disable(mmc->supply.vqmmc);
|
|
|
|
|
2012-06-21 01:10:33 +08:00
|
|
|
if (!IS_ERR(mmc->supply.vmmc))
|
2013-02-15 23:14:00 +08:00
|
|
|
mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
|
2013-09-06 19:29:05 +08:00
|
|
|
|
|
|
|
if (host->set_pwr)
|
|
|
|
host->set_pwr(host->pdev, 0);
|
2012-06-21 01:10:33 +08:00
|
|
|
}
|
|
|
|
|
2013-10-24 23:42:53 +08:00
|
|
|
static void tmio_mmc_set_bus_width(struct tmio_mmc_host *host,
|
2017-06-17 00:11:03 +08:00
|
|
|
unsigned char bus_width)
|
2013-10-24 23:42:53 +08:00
|
|
|
{
|
2016-09-20 04:57:48 +08:00
|
|
|
u16 reg = sd_ctrl_read16(host, CTL_SD_MEM_CARD_OPT)
|
|
|
|
& ~(CARD_OPT_WIDTH | CARD_OPT_WIDTH8);
|
|
|
|
|
|
|
|
/* reg now applies to MMC_BUS_WIDTH_4 */
|
|
|
|
if (bus_width == MMC_BUS_WIDTH_1)
|
|
|
|
reg |= CARD_OPT_WIDTH;
|
|
|
|
else if (bus_width == MMC_BUS_WIDTH_8)
|
|
|
|
reg |= CARD_OPT_WIDTH8;
|
|
|
|
|
|
|
|
sd_ctrl_write16(host, CTL_SD_MEM_CARD_OPT, reg);
|
2013-10-24 23:42:53 +08:00
|
|
|
}
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
/* Set MMC clock / power.
|
|
|
|
* Note: This controller uses a simple divider scheme therefore it cannot
|
|
|
|
* run a MMC card at full speed (20MHz). The max clock is 24MHz on SD, but as
|
|
|
|
* MMC wont run that fast, it has to be clocked at 12MHz which is the next
|
|
|
|
* slowest setting.
|
|
|
|
*/
|
|
|
|
static void tmio_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
2012-02-10 05:57:16 +08:00
|
|
|
struct device *dev = &host->pdev->dev;
|
2011-04-21 15:20:16 +08:00
|
|
|
unsigned long flags;
|
|
|
|
|
2011-07-14 18:12:38 +08:00
|
|
|
mutex_lock(&host->ios_lock);
|
|
|
|
|
2011-04-21 15:20:16 +08:00
|
|
|
spin_lock_irqsave(&host->lock, flags);
|
|
|
|
if (host->mrq) {
|
|
|
|
if (IS_ERR(host->mrq)) {
|
2012-02-10 05:57:16 +08:00
|
|
|
dev_dbg(dev,
|
2011-04-21 15:20:16 +08:00
|
|
|
"%s.%d: concurrent .set_ios(), clk %u, mode %u\n",
|
|
|
|
current->comm, task_pid_nr(current),
|
|
|
|
ios->clock, ios->power_mode);
|
|
|
|
host->mrq = ERR_PTR(-EINTR);
|
|
|
|
} else {
|
2012-02-10 05:57:16 +08:00
|
|
|
dev_dbg(dev,
|
2011-04-21 15:20:16 +08:00
|
|
|
"%s.%d: CMD%u active since %lu, now %lu!\n",
|
|
|
|
current->comm, task_pid_nr(current),
|
2017-06-17 00:11:03 +08:00
|
|
|
host->mrq->cmd->opcode, host->last_req_ts,
|
|
|
|
jiffies);
|
2011-04-21 15:20:16 +08:00
|
|
|
}
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2011-07-14 18:12:38 +08:00
|
|
|
|
|
|
|
mutex_unlock(&host->ios_lock);
|
2011-04-21 15:20:16 +08:00
|
|
|
return;
|
|
|
|
}
|
|
|
|
|
|
|
|
host->mrq = ERR_PTR(-EBUSY);
|
|
|
|
|
|
|
|
spin_unlock_irqrestore(&host->lock, flags);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2013-10-24 23:53:15 +08:00
|
|
|
switch (ios->power_mode) {
|
|
|
|
case MMC_POWER_OFF:
|
|
|
|
tmio_mmc_power_off(host);
|
2018-08-23 12:44:16 +08:00
|
|
|
host->set_clock(host, 0);
|
2013-10-24 23:53:15 +08:00
|
|
|
break;
|
|
|
|
case MMC_POWER_UP:
|
|
|
|
tmio_mmc_power_on(host, ios->vdd);
|
2018-08-23 12:44:16 +08:00
|
|
|
host->set_clock(host, ios->clock);
|
2013-10-24 23:42:53 +08:00
|
|
|
tmio_mmc_set_bus_width(host, ios->bus_width);
|
2013-10-24 23:53:15 +08:00
|
|
|
break;
|
|
|
|
case MMC_POWER_ON:
|
2018-08-23 12:44:16 +08:00
|
|
|
host->set_clock(host, ios->clock);
|
2013-10-24 23:53:15 +08:00
|
|
|
tmio_mmc_set_bus_width(host, ios->bus_width);
|
|
|
|
break;
|
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
/* Let things settle. delay taken from winCE driver */
|
2017-11-15 06:51:04 +08:00
|
|
|
usleep_range(140, 200);
|
2011-04-21 15:20:16 +08:00
|
|
|
if (PTR_ERR(host->mrq) == -EINTR)
|
|
|
|
dev_dbg(&host->pdev->dev,
|
|
|
|
"%s.%d: IOS interrupted: clk %u, mode %u",
|
|
|
|
current->comm, task_pid_nr(current),
|
|
|
|
ios->clock, ios->power_mode);
|
|
|
|
host->mrq = NULL;
|
2011-07-14 18:12:38 +08:00
|
|
|
|
2013-10-30 07:16:17 +08:00
|
|
|
host->clk_cache = ios->clock;
|
|
|
|
|
2011-07-14 18:12:38 +08:00
|
|
|
mutex_unlock(&host->ios_lock);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
|
|
|
static int tmio_mmc_get_ro(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
2017-06-17 00:11:03 +08:00
|
|
|
|
2018-01-18 00:28:10 +08:00
|
|
|
return !(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
|
|
|
|
TMIO_STAT_WRPROTECT);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
|
|
|
|
2018-01-18 00:28:12 +08:00
|
|
|
static int tmio_mmc_get_cd(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
return !!(sd_ctrl_read16_and_16_as_32(host, CTL_STATUS) &
|
|
|
|
TMIO_STAT_SIGSTATE);
|
|
|
|
}
|
|
|
|
|
2014-09-09 14:45:25 +08:00
|
|
|
static int tmio_multi_io_quirk(struct mmc_card *card,
|
|
|
|
unsigned int direction, int blk_size)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(card->host);
|
|
|
|
|
2015-01-13 12:58:10 +08:00
|
|
|
if (host->multi_io_quirk)
|
|
|
|
return host->multi_io_quirk(card, direction, blk_size);
|
2014-09-09 14:45:25 +08:00
|
|
|
|
|
|
|
return blk_size;
|
|
|
|
}
|
|
|
|
|
2018-06-18 20:57:50 +08:00
|
|
|
static int tmio_mmc_prepare_hs400_tuning(struct mmc_host *mmc,
|
|
|
|
struct mmc_ios *ios)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (host->prepare_hs400_tuning)
|
|
|
|
host->prepare_hs400_tuning(host);
|
|
|
|
|
|
|
|
return 0;
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_hs400_downgrade(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (host->hs400_downgrade)
|
|
|
|
host->hs400_downgrade(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_hs400_complete(struct mmc_host *mmc)
|
|
|
|
{
|
|
|
|
struct tmio_mmc_host *host = mmc_priv(mmc);
|
|
|
|
|
|
|
|
if (host->hs400_complete)
|
|
|
|
host->hs400_complete(host);
|
|
|
|
}
|
|
|
|
|
2017-11-25 00:24:41 +08:00
|
|
|
static const struct mmc_host_ops tmio_mmc_ops = {
|
2011-03-23 19:42:44 +08:00
|
|
|
.request = tmio_mmc_request,
|
|
|
|
.set_ios = tmio_mmc_set_ios,
|
|
|
|
.get_ro = tmio_mmc_get_ro,
|
2018-01-18 00:28:12 +08:00
|
|
|
.get_cd = tmio_mmc_get_cd,
|
2011-03-23 19:42:44 +08:00
|
|
|
.enable_sdio_irq = tmio_mmc_enable_sdio_irq,
|
2014-09-09 14:45:25 +08:00
|
|
|
.multi_io_quirk = tmio_multi_io_quirk,
|
2016-11-03 22:16:02 +08:00
|
|
|
.hw_reset = tmio_mmc_hw_reset,
|
2016-11-03 22:16:03 +08:00
|
|
|
.execute_tuning = tmio_mmc_execute_tuning,
|
2018-06-18 20:57:50 +08:00
|
|
|
.prepare_hs400_tuning = tmio_mmc_prepare_hs400_tuning,
|
|
|
|
.hs400_downgrade = tmio_mmc_hs400_downgrade,
|
|
|
|
.hs400_complete = tmio_mmc_hs400_complete,
|
2011-03-23 19:42:44 +08:00
|
|
|
};
|
|
|
|
|
2013-11-20 16:30:39 +08:00
|
|
|
static int tmio_mmc_init_ocr(struct tmio_mmc_host *host)
|
2012-06-21 01:10:33 +08:00
|
|
|
{
|
|
|
|
struct tmio_mmc_data *pdata = host->pdata;
|
|
|
|
struct mmc_host *mmc = host->mmc;
|
2017-09-22 19:22:17 +08:00
|
|
|
int err;
|
2012-06-21 01:10:33 +08:00
|
|
|
|
2017-09-22 19:22:17 +08:00
|
|
|
err = mmc_regulator_get_supply(mmc);
|
|
|
|
if (err)
|
|
|
|
return err;
|
2012-06-21 01:10:33 +08:00
|
|
|
|
2013-11-20 16:30:39 +08:00
|
|
|
/* use ocr_mask if no regulator */
|
2012-06-21 01:10:33 +08:00
|
|
|
if (!mmc->ocr_avail)
|
2019-01-10 06:21:50 +08:00
|
|
|
mmc->ocr_avail = pdata->ocr_mask;
|
2013-11-20 16:30:39 +08:00
|
|
|
|
|
|
|
/*
|
|
|
|
* try again.
|
|
|
|
* There is possibility that regulator has not been probed
|
|
|
|
*/
|
|
|
|
if (!mmc->ocr_avail)
|
|
|
|
return -EPROBE_DEFER;
|
|
|
|
|
|
|
|
return 0;
|
2012-06-21 01:10:33 +08:00
|
|
|
}
|
|
|
|
|
2013-02-15 23:13:56 +08:00
|
|
|
static void tmio_mmc_of_parse(struct platform_device *pdev,
|
2018-01-18 00:28:09 +08:00
|
|
|
struct mmc_host *mmc)
|
2013-02-15 23:13:56 +08:00
|
|
|
{
|
|
|
|
const struct device_node *np = pdev->dev.of_node;
|
2017-06-17 00:11:03 +08:00
|
|
|
|
2013-02-15 23:13:56 +08:00
|
|
|
if (!np)
|
|
|
|
return;
|
|
|
|
|
2018-01-18 00:28:11 +08:00
|
|
|
/*
|
|
|
|
* DEPRECATED:
|
|
|
|
* For new platforms, please use "disable-wp" instead of
|
|
|
|
* "toshiba,mmc-wrprotect-disable"
|
|
|
|
*/
|
2013-02-15 23:13:56 +08:00
|
|
|
if (of_get_property(np, "toshiba,mmc-wrprotect-disable", NULL))
|
2018-01-18 00:28:09 +08:00
|
|
|
mmc->caps2 |= MMC_CAP2_NO_WRITE_PROTECT;
|
2013-02-15 23:13:56 +08:00
|
|
|
}
|
|
|
|
|
2018-01-18 00:28:02 +08:00
|
|
|
struct tmio_mmc_host *tmio_mmc_host_alloc(struct platform_device *pdev,
|
|
|
|
struct tmio_mmc_data *pdata)
|
2011-03-23 19:42:44 +08:00
|
|
|
{
|
2015-01-13 12:57:22 +08:00
|
|
|
struct tmio_mmc_host *host;
|
2011-03-23 19:42:44 +08:00
|
|
|
struct mmc_host *mmc;
|
2018-01-18 00:28:01 +08:00
|
|
|
struct resource *res;
|
|
|
|
void __iomem *ctl;
|
2018-01-18 00:28:03 +08:00
|
|
|
int ret;
|
2018-01-18 00:28:01 +08:00
|
|
|
|
|
|
|
res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
|
|
|
|
ctl = devm_ioremap_resource(&pdev->dev, res);
|
|
|
|
if (IS_ERR(ctl))
|
|
|
|
return ERR_CAST(ctl);
|
2015-01-13 12:57:22 +08:00
|
|
|
|
|
|
|
mmc = mmc_alloc_host(sizeof(struct tmio_mmc_host), &pdev->dev);
|
|
|
|
if (!mmc)
|
2018-01-18 00:28:01 +08:00
|
|
|
return ERR_PTR(-ENOMEM);
|
2015-01-13 12:57:22 +08:00
|
|
|
|
|
|
|
host = mmc_priv(mmc);
|
2018-01-18 00:28:01 +08:00
|
|
|
host->ctl = ctl;
|
2015-01-13 12:57:22 +08:00
|
|
|
host->mmc = mmc;
|
|
|
|
host->pdev = pdev;
|
2018-01-18 00:28:02 +08:00
|
|
|
host->pdata = pdata;
|
2017-11-25 00:24:41 +08:00
|
|
|
host->ops = tmio_mmc_ops;
|
|
|
|
mmc->ops = &host->ops;
|
2015-01-13 12:57:22 +08:00
|
|
|
|
2018-01-18 00:28:03 +08:00
|
|
|
ret = mmc_of_parse(host->mmc);
|
|
|
|
if (ret) {
|
|
|
|
host = ERR_PTR(ret);
|
|
|
|
goto free;
|
|
|
|
}
|
|
|
|
|
2018-01-18 00:28:09 +08:00
|
|
|
tmio_mmc_of_parse(pdev, mmc);
|
2018-01-18 00:28:03 +08:00
|
|
|
|
2018-01-18 00:28:02 +08:00
|
|
|
platform_set_drvdata(pdev, host);
|
|
|
|
|
2018-01-18 00:28:03 +08:00
|
|
|
return host;
|
|
|
|
free:
|
|
|
|
mmc_free_host(mmc);
|
|
|
|
|
2015-01-13 12:57:22 +08:00
|
|
|
return host;
|
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_alloc);
|
2015-01-13 12:57:22 +08:00
|
|
|
|
|
|
|
void tmio_mmc_host_free(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
mmc_free_host(host->mmc);
|
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_free);
|
2015-01-13 12:57:22 +08:00
|
|
|
|
2018-01-18 00:28:04 +08:00
|
|
|
int tmio_mmc_host_probe(struct tmio_mmc_host *_host)
|
2015-01-13 12:57:22 +08:00
|
|
|
{
|
|
|
|
struct platform_device *pdev = _host->pdev;
|
2018-01-18 00:28:02 +08:00
|
|
|
struct tmio_mmc_data *pdata = _host->pdata;
|
2015-01-13 12:57:22 +08:00
|
|
|
struct mmc_host *mmc = _host->mmc;
|
2011-03-23 19:42:44 +08:00
|
|
|
int ret;
|
|
|
|
|
2018-01-18 00:28:02 +08:00
|
|
|
/*
|
2018-08-23 12:44:16 +08:00
|
|
|
* Check the sanity of mmc->f_min to prevent host->set_clock() from
|
2018-01-18 00:28:02 +08:00
|
|
|
* looping forever...
|
|
|
|
*/
|
|
|
|
if (mmc->f_min == 0)
|
|
|
|
return -EINVAL;
|
|
|
|
|
2013-02-15 23:13:50 +08:00
|
|
|
if (!(pdata->flags & TMIO_MMC_HAS_IDLE_WAIT))
|
2015-01-13 12:57:42 +08:00
|
|
|
_host->write16_hook = NULL;
|
2013-02-15 23:13:50 +08:00
|
|
|
|
2013-09-06 19:29:05 +08:00
|
|
|
_host->set_pwr = pdata->set_pwr;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2013-11-20 16:30:39 +08:00
|
|
|
ret = tmio_mmc_init_ocr(_host);
|
|
|
|
if (ret < 0)
|
2017-01-06 16:38:33 +08:00
|
|
|
return ret;
|
2013-11-20 16:30:39 +08:00
|
|
|
|
2018-12-02 16:43:19 +08:00
|
|
|
/*
|
|
|
|
* Look for a card detect GPIO, if it fails with anything
|
|
|
|
* else than a probe deferral, just live without it.
|
|
|
|
*/
|
|
|
|
ret = mmc_gpiod_request_cd(mmc, "cd", 0, false, 0, NULL);
|
|
|
|
if (ret == -EPROBE_DEFER)
|
|
|
|
return ret;
|
2017-11-25 00:24:43 +08:00
|
|
|
|
2013-02-15 23:13:56 +08:00
|
|
|
mmc->caps |= MMC_CAP_4_BIT_DATA | pdata->capabilities;
|
2013-11-20 16:16:14 +08:00
|
|
|
mmc->caps2 |= pdata->capabilities2;
|
2017-06-21 22:00:27 +08:00
|
|
|
mmc->max_segs = pdata->max_segs ? : 32;
|
2019-03-15 06:31:29 +08:00
|
|
|
mmc->max_blk_size = TMIO_MAX_BLK_SIZE;
|
2017-06-21 22:00:27 +08:00
|
|
|
mmc->max_blk_count = pdata->max_blk_count ? :
|
|
|
|
(PAGE_SIZE / mmc->max_blk_size) * mmc->max_segs;
|
2011-03-23 19:42:44 +08:00
|
|
|
mmc->max_req_size = mmc->max_blk_size * mmc->max_blk_count;
|
2017-10-20 11:12:41 +08:00
|
|
|
/*
|
|
|
|
* Since swiotlb has memory size limitation, this will calculate
|
|
|
|
* the maximum size locally (because we don't have any APIs for it now)
|
|
|
|
* and check the current max_req_size. And then, this will update
|
|
|
|
* the max_req_size if needed as a workaround.
|
|
|
|
*/
|
|
|
|
if (swiotlb_max_segment()) {
|
|
|
|
unsigned int max_size = (1 << IO_TLB_SHIFT) * IO_TLB_SEGSIZE;
|
|
|
|
|
|
|
|
if (mmc->max_req_size > max_size)
|
|
|
|
mmc->max_req_size = max_size;
|
|
|
|
}
|
2011-03-23 19:42:44 +08:00
|
|
|
mmc->max_seg_size = mmc->max_req_size;
|
|
|
|
|
2018-01-18 00:28:06 +08:00
|
|
|
if (mmc_can_gpio_ro(mmc))
|
|
|
|
_host->ops.get_ro = mmc_gpio_get_ro;
|
|
|
|
|
2018-01-18 00:28:12 +08:00
|
|
|
if (mmc_can_gpio_cd(mmc))
|
|
|
|
_host->ops.get_cd = mmc_gpio_get_cd;
|
|
|
|
|
2017-11-25 00:24:44 +08:00
|
|
|
_host->native_hotplug = !(mmc_can_gpio_cd(mmc) ||
|
2012-02-10 05:57:08 +08:00
|
|
|
mmc->caps & MMC_CAP_NEEDS_POLL ||
|
2017-01-10 23:10:52 +08:00
|
|
|
!mmc_card_is_removable(mmc));
|
2012-02-10 05:57:08 +08:00
|
|
|
|
2018-10-10 11:51:31 +08:00
|
|
|
if (!_host->reset)
|
|
|
|
_host->reset = tmio_mmc_reset;
|
|
|
|
|
2016-09-20 04:57:48 +08:00
|
|
|
/*
|
|
|
|
* On Gen2+, eMMC with NONREMOVABLE currently fails because native
|
|
|
|
* hotplug gets disabled. It seems RuntimePM related yet we need further
|
|
|
|
* research. Since we are planning a PM overhaul anyway, let's enforce
|
|
|
|
* for now the device being active by enabling native hotplug always.
|
|
|
|
*/
|
|
|
|
if (pdata->flags & TMIO_MMC_MIN_RCAR2)
|
|
|
|
_host->native_hotplug = true;
|
|
|
|
|
2011-12-24 06:03:13 +08:00
|
|
|
/*
|
2013-10-24 22:42:33 +08:00
|
|
|
* While using internal tmio hardware logic for card detection, we need
|
|
|
|
* to ensure it stays powered for it to work.
|
2011-12-24 06:03:13 +08:00
|
|
|
*/
|
2012-02-10 05:57:08 +08:00
|
|
|
if (_host->native_hotplug)
|
2011-12-24 06:03:13 +08:00
|
|
|
pm_runtime_get_noresume(&pdev->dev);
|
|
|
|
|
2017-05-23 21:34:08 +08:00
|
|
|
_host->sdio_irq_enabled = false;
|
|
|
|
if (pdata->flags & TMIO_MMC_SDIO_IRQ)
|
|
|
|
_host->sdio_irq_mask = TMIO_SDIO_MASK_ALL;
|
|
|
|
|
2018-08-23 12:44:16 +08:00
|
|
|
_host->set_clock(_host, 0);
|
2018-11-27 01:02:46 +08:00
|
|
|
tmio_mmc_hw_reset(mmc);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2016-04-28 00:51:23 +08:00
|
|
|
_host->sdcard_irq_mask = sd_ctrl_read16_and_16_as_32(_host, CTL_IRQ_MASK);
|
2011-03-23 19:42:44 +08:00
|
|
|
tmio_mmc_disable_mmc_irqs(_host, TMIO_MASK_ALL);
|
2012-06-21 01:10:30 +08:00
|
|
|
|
2018-01-18 00:28:13 +08:00
|
|
|
if (_host->native_hotplug)
|
|
|
|
tmio_mmc_enable_mmc_irqs(_host,
|
|
|
|
TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
spin_lock_init(&_host->lock);
|
2011-07-14 18:12:38 +08:00
|
|
|
mutex_init(&_host->ios_lock);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
/* Init delayed work for request timeouts */
|
|
|
|
INIT_DELAYED_WORK(&_host->delayed_reset_work, tmio_mmc_reset_work);
|
2011-07-14 18:12:38 +08:00
|
|
|
INIT_WORK(&_host->done, tmio_mmc_done_work);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
/* See if we also get DMA */
|
|
|
|
tmio_mmc_request_dma(_host, pdata);
|
|
|
|
|
2013-10-24 22:42:33 +08:00
|
|
|
pm_runtime_set_active(&pdev->dev);
|
|
|
|
pm_runtime_set_autosuspend_delay(&pdev->dev, 50);
|
|
|
|
pm_runtime_use_autosuspend(&pdev->dev);
|
|
|
|
pm_runtime_enable(&pdev->dev);
|
|
|
|
|
2012-06-21 01:10:31 +08:00
|
|
|
ret = mmc_add_host(mmc);
|
2017-10-28 01:09:17 +08:00
|
|
|
if (ret)
|
|
|
|
goto remove_host;
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2012-03-13 08:01:51 +08:00
|
|
|
dev_pm_qos_expose_latency_limit(&pdev->dev, 100);
|
|
|
|
|
2011-03-23 19:42:44 +08:00
|
|
|
return 0;
|
2017-10-28 01:09:17 +08:00
|
|
|
|
|
|
|
remove_host:
|
|
|
|
tmio_mmc_host_remove(_host);
|
|
|
|
return ret;
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_probe);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
|
|
|
void tmio_mmc_host_remove(struct tmio_mmc_host *host)
|
|
|
|
{
|
2011-05-06 00:13:12 +08:00
|
|
|
struct platform_device *pdev = host->pdev;
|
2012-02-10 05:57:09 +08:00
|
|
|
struct mmc_host *mmc = host->mmc;
|
|
|
|
|
2016-12-10 00:51:41 +08:00
|
|
|
if (host->pdata->flags & TMIO_MMC_SDIO_IRQ)
|
|
|
|
sd_ctrl_write16(host, CTL_TRANSACTION_CTL, 0x0000);
|
|
|
|
|
2012-02-10 05:57:08 +08:00
|
|
|
if (!host->native_hotplug)
|
2011-05-12 00:51:11 +08:00
|
|
|
pm_runtime_get_sync(&pdev->dev);
|
|
|
|
|
2012-03-13 08:01:51 +08:00
|
|
|
dev_pm_qos_hide_latency_limit(&pdev->dev);
|
|
|
|
|
2012-02-10 05:57:09 +08:00
|
|
|
mmc_remove_host(mmc);
|
2011-07-14 18:12:38 +08:00
|
|
|
cancel_work_sync(&host->done);
|
2011-03-23 19:42:44 +08:00
|
|
|
cancel_delayed_work_sync(&host->delayed_reset_work);
|
|
|
|
tmio_mmc_release_dma(host);
|
2011-05-06 00:13:12 +08:00
|
|
|
|
2019-01-10 06:34:51 +08:00
|
|
|
pm_runtime_dont_use_autosuspend(&pdev->dev);
|
2011-05-06 00:13:12 +08:00
|
|
|
pm_runtime_put_sync(&pdev->dev);
|
|
|
|
pm_runtime_disable(&pdev->dev);
|
2011-03-23 19:42:44 +08:00
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_remove);
|
2011-03-23 19:42:44 +08:00
|
|
|
|
2014-08-25 18:03:20 +08:00
|
|
|
#ifdef CONFIG_PM
|
2018-01-19 22:54:44 +08:00
|
|
|
static int tmio_mmc_clk_enable(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
if (!host->clk_enable)
|
|
|
|
return -ENOTSUPP;
|
|
|
|
|
|
|
|
return host->clk_enable(host);
|
|
|
|
}
|
|
|
|
|
|
|
|
static void tmio_mmc_clk_disable(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
if (host->clk_disable)
|
|
|
|
host->clk_disable(host);
|
|
|
|
}
|
|
|
|
|
2011-05-12 00:51:11 +08:00
|
|
|
int tmio_mmc_host_runtime_suspend(struct device *dev)
|
|
|
|
{
|
2017-11-25 00:24:39 +08:00
|
|
|
struct tmio_mmc_host *host = dev_get_drvdata(dev);
|
2013-10-30 07:16:17 +08:00
|
|
|
|
2014-08-25 17:55:57 +08:00
|
|
|
tmio_mmc_disable_mmc_irqs(host, TMIO_MASK_ALL);
|
|
|
|
|
2013-10-30 07:16:17 +08:00
|
|
|
if (host->clk_cache)
|
2018-08-23 12:44:16 +08:00
|
|
|
host->set_clock(host, 0);
|
2013-10-30 07:16:17 +08:00
|
|
|
|
2017-01-18 04:26:01 +08:00
|
|
|
tmio_mmc_clk_disable(host);
|
2013-10-30 07:16:17 +08:00
|
|
|
|
2011-05-12 00:51:11 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_runtime_suspend);
|
2011-05-12 00:51:11 +08:00
|
|
|
|
2016-11-03 22:16:03 +08:00
|
|
|
static bool tmio_mmc_can_retune(struct tmio_mmc_host *host)
|
|
|
|
{
|
|
|
|
return host->tap_num && mmc_can_retune(host->mmc);
|
|
|
|
}
|
|
|
|
|
2011-05-12 00:51:11 +08:00
|
|
|
int tmio_mmc_host_runtime_resume(struct device *dev)
|
|
|
|
{
|
2017-11-25 00:24:39 +08:00
|
|
|
struct tmio_mmc_host *host = dev_get_drvdata(dev);
|
2011-05-12 00:51:11 +08:00
|
|
|
|
2016-04-01 23:44:32 +08:00
|
|
|
tmio_mmc_clk_enable(host);
|
2018-11-27 01:02:46 +08:00
|
|
|
tmio_mmc_hw_reset(host->mmc);
|
2013-10-30 07:16:17 +08:00
|
|
|
|
2016-04-01 23:44:34 +08:00
|
|
|
if (host->clk_cache)
|
2018-08-23 12:44:16 +08:00
|
|
|
host->set_clock(host, host->clk_cache);
|
2013-10-30 07:16:17 +08:00
|
|
|
|
2018-01-18 00:28:13 +08:00
|
|
|
if (host->native_hotplug)
|
|
|
|
tmio_mmc_enable_mmc_irqs(host,
|
|
|
|
TMIO_STAT_CARD_REMOVE | TMIO_STAT_CARD_INSERT);
|
|
|
|
|
2011-07-15 00:39:10 +08:00
|
|
|
tmio_mmc_enable_dma(host, true);
|
2011-05-12 00:51:11 +08:00
|
|
|
|
2016-11-03 22:16:03 +08:00
|
|
|
if (tmio_mmc_can_retune(host) && host->select_tuning(host))
|
|
|
|
dev_warn(&host->pdev->dev, "Tuning selection failed\n");
|
|
|
|
|
2011-05-12 00:51:11 +08:00
|
|
|
return 0;
|
|
|
|
}
|
2017-05-30 20:50:51 +08:00
|
|
|
EXPORT_SYMBOL_GPL(tmio_mmc_host_runtime_resume);
|
2013-10-23 20:55:07 +08:00
|
|
|
#endif
|
2011-05-12 00:51:11 +08:00
|
|
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2011-03-23 19:42:44 +08:00
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MODULE_LICENSE("GPL v2");
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