2018-03-20 22:58:06 +08:00
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/* SPDX-License-Identifier: GPL-2.0 */
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/* Copyright (c) 2018, Intel Corporation. */
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#ifndef _ICE_COMMON_H_
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#define _ICE_COMMON_H_
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#include "ice.h"
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#include "ice_type.h"
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ice: Get switch config, scheduler config and device capabilities
This patch adds to the initialization flow by getting switch
configuration, scheduler configuration and device capabilities.
Switch configuration:
On boot, an L2 switch element is created in the firmware per physical
function. Each physical function is also mapped to a port, to which its
switch element is connected. In other words, this switch can be visualized
as an embedded vSwitch that can connect a physical function's virtual
station interfaces (VSIs) to the egress/ingress port. Egress/ingress
filters will be eventually created and applied on this switch element.
As part of the initialization flow, the driver gets configuration data
from this switch element and stores it.
Scheduler configuration:
The Tx scheduler is a subsystem responsible for setting and enforcing QoS.
As part of the initialization flow, the driver queries and stores the
default scheduler configuration for the given physical function.
Device capabilities:
As part of initialization, the driver has to determine what the device is
capable of (ex. max queues, VSIs, etc). This information is obtained from
the firmware and stored by the driver.
CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@oracle.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2018-03-20 22:58:08 +08:00
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#include "ice_switch.h"
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2018-09-20 08:42:55 +08:00
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#include <linux/avf/virtchnl.h>
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2018-03-20 22:58:06 +08:00
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2019-02-27 08:35:11 +08:00
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void
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ice_debug_cq(struct ice_hw *hw, u32 mask, void *desc, void *buf, u16 buf_len);
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2018-03-20 22:58:07 +08:00
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enum ice_status ice_init_hw(struct ice_hw *hw);
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void ice_deinit_hw(struct ice_hw *hw);
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enum ice_status ice_check_reset(struct ice_hw *hw);
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enum ice_status ice_reset(struct ice_hw *hw, enum ice_reset_req req);
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2018-03-20 22:58:06 +08:00
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enum ice_status ice_init_all_ctrlq(struct ice_hw *hw);
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void ice_shutdown_all_ctrlq(struct ice_hw *hw);
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enum ice_status
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2018-03-20 22:58:10 +08:00
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ice_clean_rq_elem(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_rq_event_info *e, u16 *pending);
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enum ice_status
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2018-03-20 22:58:18 +08:00
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ice_get_link_status(struct ice_port_info *pi, bool *link_up);
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2018-09-20 08:23:15 +08:00
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enum ice_status ice_update_link_info(struct ice_port_info *pi);
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2018-03-20 22:58:18 +08:00
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enum ice_status
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2018-03-20 22:58:07 +08:00
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ice_acquire_res(struct ice_hw *hw, enum ice_aq_res_ids res,
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2018-08-09 21:29:46 +08:00
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enum ice_aq_res_access_type access, u32 timeout);
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2018-03-20 22:58:07 +08:00
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void ice_release_res(struct ice_hw *hw, enum ice_aq_res_ids res);
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enum ice_status ice_init_nvm(struct ice_hw *hw);
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2019-02-27 08:35:11 +08:00
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enum ice_status
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ice_read_sr_buf(struct ice_hw *hw, u16 offset, u16 *words, u16 *data);
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2018-03-20 22:58:07 +08:00
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enum ice_status
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2018-03-20 22:58:06 +08:00
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ice_sq_send_cmd(struct ice_hw *hw, struct ice_ctl_q_info *cq,
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struct ice_aq_desc *desc, void *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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2018-03-20 22:58:07 +08:00
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void ice_clear_pxe_mode(struct ice_hw *hw);
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ice: Get switch config, scheduler config and device capabilities
This patch adds to the initialization flow by getting switch
configuration, scheduler configuration and device capabilities.
Switch configuration:
On boot, an L2 switch element is created in the firmware per physical
function. Each physical function is also mapped to a port, to which its
switch element is connected. In other words, this switch can be visualized
as an embedded vSwitch that can connect a physical function's virtual
station interfaces (VSIs) to the egress/ingress port. Egress/ingress
filters will be eventually created and applied on this switch element.
As part of the initialization flow, the driver gets configuration data
from this switch element and stores it.
Scheduler configuration:
The Tx scheduler is a subsystem responsible for setting and enforcing QoS.
As part of the initialization flow, the driver queries and stores the
default scheduler configuration for the given physical function.
Device capabilities:
As part of initialization, the driver has to determine what the device is
capable of (ex. max queues, VSIs, etc). This information is obtained from
the firmware and stored by the driver.
CC: Shannon Nelson <shannon.nelson@oracle.com>
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Acked-by: Shannon Nelson <shannon.nelson@oracle.com>
Tested-by: Tony Brelinski <tonyx.brelinski@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2018-03-20 22:58:08 +08:00
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enum ice_status ice_get_caps(struct ice_hw *hw);
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2018-10-18 23:37:07 +08:00
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void ice_dev_onetime_setup(struct ice_hw *hw);
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2018-03-20 22:58:13 +08:00
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enum ice_status
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ice_write_rxq_ctx(struct ice_hw *hw, struct ice_rlan_ctx *rlan_ctx,
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u32 rxq_index);
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2018-03-20 22:58:15 +08:00
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_aq_get_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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2018-03-20 22:58:15 +08:00
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u16 lut_size);
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_aq_set_rss_lut(struct ice_hw *hw, u16 vsi_handle, u8 lut_type, u8 *lut,
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2018-03-20 22:58:15 +08:00
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u16 lut_size);
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_aq_get_rss_key(struct ice_hw *hw, u16 vsi_handle,
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2018-03-20 22:58:15 +08:00
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struct ice_aqc_get_set_rss_keys *keys);
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_aq_set_rss_key(struct ice_hw *hw, u16 vsi_handle,
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2018-03-20 22:58:15 +08:00
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struct ice_aqc_get_set_rss_keys *keys);
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2018-09-20 08:23:13 +08:00
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2018-03-20 22:58:06 +08:00
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bool ice_check_sq_alive(struct ice_hw *hw, struct ice_ctl_q_info *cq);
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enum ice_status ice_aq_q_shutdown(struct ice_hw *hw, bool unloading);
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void ice_fill_dflt_direct_cmd_desc(struct ice_aq_desc *desc, u16 opcode);
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2018-03-20 22:58:13 +08:00
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extern const struct ice_ctx_ele ice_tlan_ctx_info[];
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enum ice_status
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ice_set_ctx(u8 *src_ctx, u8 *dest_ctx, const struct ice_ctx_ele *ce_info);
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2018-03-20 22:58:06 +08:00
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enum ice_status
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ice_aq_send_cmd(struct ice_hw *hw, struct ice_aq_desc *desc,
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void *buf, u16 buf_size, struct ice_sq_cd *cd);
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enum ice_status ice_aq_get_fw_ver(struct ice_hw *hw, struct ice_sq_cd *cd);
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2018-08-09 21:29:51 +08:00
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enum ice_status
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ice_aq_get_phy_caps(struct ice_port_info *pi, bool qual_mods, u8 report_mode,
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struct ice_aqc_get_phy_caps_data *caps,
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struct ice_sq_cd *cd);
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void
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2018-12-20 02:03:33 +08:00
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ice_update_phy_type(u64 *phy_type_low, u64 *phy_type_high,
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u16 link_speeds_bitmap);
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2018-03-20 22:58:19 +08:00
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enum ice_status
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2018-12-20 02:03:34 +08:00
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ice_aq_manage_mac_write(struct ice_hw *hw, const u8 *mac_addr, u8 flags,
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2018-03-20 22:58:19 +08:00
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struct ice_sq_cd *cd);
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2018-03-20 22:58:07 +08:00
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enum ice_status ice_clear_pf_cfg(struct ice_hw *hw);
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2018-03-20 22:58:09 +08:00
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enum ice_status
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2018-08-09 21:29:51 +08:00
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ice_aq_set_phy_cfg(struct ice_hw *hw, u8 lport,
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struct ice_aqc_set_phy_cfg_data *cfg, struct ice_sq_cd *cd);
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enum ice_status
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ice_set_fc(struct ice_port_info *pi, u8 *aq_failures,
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bool ena_auto_link_update);
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2018-03-20 22:58:16 +08:00
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enum ice_status
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ice_aq_set_link_restart_an(struct ice_port_info *pi, bool ena_link,
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struct ice_sq_cd *cd);
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2019-02-27 08:35:23 +08:00
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enum ice_status
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ice_aq_get_link_info(struct ice_port_info *pi, bool ena_lse,
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struct ice_link_status *link, struct ice_sq_cd *cd);
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enum ice_status
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ice_aq_set_event_mask(struct ice_hw *hw, u8 port_num, u16 mask,
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struct ice_sq_cd *cd);
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2018-03-20 22:58:16 +08:00
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enum ice_status
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2018-12-20 02:03:23 +08:00
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ice_aq_set_port_id_led(struct ice_port_info *pi, bool is_orig_mode,
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struct ice_sq_cd *cd);
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enum ice_status
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2018-03-20 22:58:13 +08:00
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ice_dis_vsi_txq(struct ice_port_info *pi, u8 num_queues, u16 *q_ids,
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2018-09-20 08:42:55 +08:00
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u32 *q_teids, enum ice_disq_rst_src rst_src, u16 vmvf_num,
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struct ice_sq_cd *cmd_details);
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2018-03-20 22:58:13 +08:00
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_cfg_vsi_lan(struct ice_port_info *pi, u16 vsi_handle, u8 tc_bitmap,
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2018-03-20 22:58:17 +08:00
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u16 *max_lanqs);
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enum ice_status
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2018-09-20 08:23:13 +08:00
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ice_ena_vsi_txq(struct ice_port_info *pi, u16 vsi_handle, u8 tc, u8 num_qgrps,
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2018-03-20 22:58:13 +08:00
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struct ice_aqc_add_tx_qgrp *buf, u16 buf_size,
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struct ice_sq_cd *cd);
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ice: Implement VSI replay framework
Currently, switch filters get replayed after reset. In addition to
filters, other VSI attributes (like RSS configuration, Tx scheduler
configuration, etc.) also need to be replayed after reset.
Thus, instead of replaying based on functional blocks (i.e. replay
all filters for all VSIs, followed by RSS configuration replay for
all VSIs, and so on), it makes more sense to have the replay centered
around a VSI. In other words, replay all configurations for a VSI before
moving on to rebuilding the next VSI.
To that effect, this patch introduces a VSI replay framework in a new
function ice_vsi_replay_all. Currently it only replays switch filters,
but it will be expanded in the future to replay additional VSI attributes.
Signed-off-by: Anirudh Venkataramanan <anirudh.venkataramanan@intel.com>
Tested-by: Andrew Bowers <andrewx.bowers@intel.com>
Signed-off-by: Jeff Kirsher <jeffrey.t.kirsher@intel.com>
2018-09-20 08:23:14 +08:00
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enum ice_status ice_replay_vsi(struct ice_hw *hw, u16 vsi_handle);
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void ice_replay_post(struct ice_hw *hw);
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2018-08-09 21:29:55 +08:00
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void ice_output_fw_log(struct ice_hw *hw, struct ice_aq_desc *desc, void *buf);
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2019-02-27 08:35:11 +08:00
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void
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ice_stat_update40(struct ice_hw *hw, u32 hireg, u32 loreg,
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bool prev_stat_loaded, u64 *prev_stat, u64 *cur_stat);
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void
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ice_stat_update32(struct ice_hw *hw, u32 reg, bool prev_stat_loaded,
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u64 *prev_stat, u64 *cur_stat);
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2018-03-20 22:58:06 +08:00
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#endif /* _ICE_COMMON_H_ */
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