Commit Graph

6328 Commits

Author SHA1 Message Date
Anson Huang 2e2b928a04 clk: imx7ulp: Correct DDR clock mux options
In the latest reference manual Rev.0,06/2019, the DDR clock mux
is extended to 2 bits, and the clock options are also changed,
correct them accordingly.

Fixes: b1260067ac ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-26 16:17:22 +08:00
Anson Huang 96ac93a7c4 clk: imx7ulp: Correct system clock source option #7
In the latest reference manual Rev.0,06/2019, the SCS's option #7
is no longer from upll, it is reserved, update clock driver accordingly.

Fixes: b1260067ac ("clk: imx: add imx7ulp clk driver")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Fabio Estevam <festevam@gmail.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-26 16:15:52 +08:00
Marek Szyprowski e9323b664c clk: samsung: exynos5420: Preserve PLL configuration during suspend/resume
Properly save and restore all top PLL related configuration registers
during suspend/resume cycle. So far driver only handled EPLL and RPLL
clocks, all other were reset to default values after suspend/resume cycle.
This caused for example lower G3D (MALI Panfrost) performance after system
resume, even if performance governor has been selected.

Reported-by: Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>
Fixes: 773424326b ("clk: samsung: exynos5420: add more registers to restore list")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-25 11:20:00 +02:00
Peng Fan 7858d31bef clk: imx: imx8mq: mark sys1/2_pll as fixed clock
According Architecture definition guide, SYS1_PLL is fixed at
800MHz, SYS2_PLL is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:07:08 +08:00
Peng Fan 3f44344868 clk: imx: imx8mn: mark sys_pll1/2 as fixed clock
According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:07:05 +08:00
Peng Fan c332481f62 clk: imx: imx8mm: mark sys_pll1/2 as fixed clock
According Architecture definition guide, SYS_PLL1 is fixed at
800MHz, SYS_PLL2 is fixed at 1000MHz, so let's use imx_clk_fixed
to register the clocks and drop code that could change the rate.

Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:06:47 +08:00
Leonard Crestez e8688fe8df clk: imx8mn: Define gates for pll1/2 fixed dividers
On imx8mn there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:03:19 +08:00
Leonard Crestez 3e4947acad clk: imx8mm: Define gates for pll1/2 fixed dividers
On imx8mm there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate. Only one of these gates (the one "dividing" by
one) is currently defined and it's incorrectly set as the parent of all
the fixed-factor dividers.

Add the other 8 gates to the clock tree between sys_pll1/2_bypass and
the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:03:16 +08:00
Leonard Crestez b04383b6a5 clk: imx8mq: Define gates for pll1/2 fixed dividers
On imx8mq there are 9 fixed-factor dividers for SYS_PLL1 and SYS_PLL2
each with their own gate but these gates are not currently defined in
the clock tree.

Add them between sys1/2_pll_out and the fixed dividers.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-25 17:03:00 +08:00
Marek Szyprowski c9f7567aff clk: samsung: exynos542x: Move G3D subsystem clocks to its sub-CMU
G3D clocks require special handling of their parent bus clock during power
domain on/off sequences. Those clocks were not initially added to the
sub-CMU handler, because that time there was no open-source driver for the
G3D (MALI Panfrost) hardware module and it was not possible to test it.

This patch fixes this issue. Parent clock for G3D hardware block is now
properly preserved during G3D power domain on/off sequence. This restores
proper MALI Panfrost performance broken by commit 8686764fc0
("ARM: dts: exynos: Add G3D power domain to Exynos542x").

Reported-by: Marian Mihailescu <mihailescu2m@gmail.com>
Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Marian Mihailescu <mihailescu2m@gmail.com>
Acked-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-23 18:26:21 +02:00
Marek Szyprowski faac3604d0 clk: samsung: exynos5433: Fix error paths
Add checking the value returned by samsung_clk_alloc_reg_dump() and
devm_kcalloc(). While fixing this, also release all gathered clocks.

Fixes: 523d3de41f ("clk: samsung: exynos5433: Add support for runtime PM")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Reviewed-by: Krzysztof Kozlowski <krzk@kernel.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
[s.nawrocki: squashed patch from K. Kozlowski adding missing slab.h header]
Reported-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-10-23 18:23:28 +02:00
Olof Johansson a4e86630a1 ARM: Marvell MMP SoC patches for v5.5
This tag includes initial support for the Marvell MMP3 processor.
 MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet
 and Dell Wyse 3020/Tx0D thin clients.
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Merge tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp into arm/soc

ARM: Marvell MMP SoC patches for v5.5

This tag includes initial support for the Marvell MMP3 processor.
MMP3 is used in OLPC XO-4 laptops, Panasonic Toughpad FZ-A1 tablet
and Dell Wyse 3020/Tx0D thin clients.

* tag 'mmp-soc-for-v5.5-2' of git://git.kernel.org/pub/scm/linux/kernel/git/lkundrak/linux-mmp:
  MAINTAINERS: mmp: add Git repository
  ARM: mmp: remove MMP3 USB PHY registers from regs-usb.h
  ARM: mmp: move cputype.h to include/linux/soc/
  ARM: mmp: add SMP support
  ARM: mmp: add support for MMP3 SoC
  ARM: mmp: define MMP_CHIPID by the means of CIU_REG()
  ARM: mmp: DT: convert timer driver to use TIMER_OF_DECLARE
  ARM: mmp: map the PGU as well
  ARM: mmp: don't select CACHE_TAUROS2 on all ARCH_MMP
  ARM: l2c: add definition for FWA in PL310 aux register

Link: https://lore.kernel.org/r/3a035bed90f9d8acc49b2d11d20089b546062aea.camel@v3.sk
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-21 15:28:39 -07:00
Geert Uytterhoeven 362c79f75c clk: renesas: rcar-gen3: Switch SD clocks to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the SD clocks on R-Car Gen3 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

This includes implementing range checking.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190830134515.11925-9-geert+renesas@glider.be
2019-10-21 09:53:54 +02:00
Geert Uytterhoeven df98719f03 clk: renesas: rcar-gen3: Switch Z clocks to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the Z clocks on R-Car Gen3 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

This includes implementing range checking.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190830134515.11925-8-geert+renesas@glider.be
2019-10-21 09:53:50 +02:00
Geert Uytterhoeven 7aee839ed2 clk: renesas: rcar-gen2: Switch Z clock to .determine_rate()
As the .round_rate() callback returns a long clock rate, it cannot
return clock rates that do not fit in signed long, but do fit in
unsigned long.  Hence switch the Z clock on R-Car Gen2 from the old
.round_rate() callback to the newer .determine_rate() callback, which
does not suffer from this limitation.

This includes implementing range checking.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Link: https://lore.kernel.org/r/20190830134515.11925-7-geert+renesas@glider.be
2019-10-21 09:53:43 +02:00
Lubomir Rintel a9372a5fb2 ARM: mmp: add support for MMP3 SoC
Similar to MMP2, which this patch is based on. Known differencies from MMP2
are:

* Two PJ4B cores instead of one PJ4
* Tauros 3 L2 cache controller instead of Tauros 2
* A GIC interrupt controller optionally used instead of the MMP one
* A TWD local timer
* Different USB2 PHY
* A USB3 SS controller
* More interrupt muxes

Hard to tell what else is different, because documentation is not
available.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
2019-10-17 16:36:11 +02:00
Baolin Wang 793ee798cc clk: sprd: Change to use devm_platform_ioremap_resource()
Use the new helper that wraps the calls to platform_get_resource()
and devm_ioremap_resource() together, which can simpify the code.

Signed-off-by: Baolin Wang <baolin.wang@linaro.org>
Link: https://lkml.kernel.org/r/841d26a2adb4bf3b4423f82a41dd3f1346413db6.1570520268.git.baolin.wang@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:18:30 -07:00
YueHaibing 56a5732139 clk: s3c2410: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015142424.25944-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:52 -07:00
YueHaibing 21ec8679c2 clk: axs10x: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015142259.17216-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:50 -07:00
YueHaibing 0b17159de2 clk: mediatek: mt6797: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015124728.25072-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:46 -07:00
YueHaibing aa136002ae clk: mediatek: mt7629: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015124226.25792-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:44 -07:00
YueHaibing ed4e1bbb44 clk: mediatek: mt7622: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121735.26228-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:42 -07:00
YueHaibing 067de0a647 clk: mediatek: mt8183: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121421.26144-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:40 -07:00
YueHaibing 71ae814181 clk: mediatek: mt6779: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015121035.24736-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:37 -07:00
YueHaibing 73c3bf70b3 clk: mediatek: mt2712: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015112644.19816-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:32 -07:00
YueHaibing 1f8f3c6b35 clk: davinci: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191014144407.23264-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:14 -07:00
YueHaibing 75cc0a123c clk: hisilicon: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191014144014.20644-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:17:06 -07:00
YueHaibing 4d3a369510 clk: bcm2835: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191014143642.24552-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 16:16:50 -07:00
Stephen Boyd 3d883e8969 First round of amlogic clock fixes for v5.4.
This fixes the clock rate propagation for the g12a cpu clocks and
 the gxbb adc clock.
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Merge tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull first round of amlogic clock fixes from Jerome Brunet:

 - This fixes the clock rate propagation for the g12a cpu and gxbb adc clocks.

* tag 'clk-meson-fixes-v5.4-1' of https://github.com/BayLibre/clk-meson:
  clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
  clk: meson: g12a: fix cpu clock rate setting
  clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
2019-10-16 14:01:19 -07:00
Peng Fan 727e12cde9 clk: imx: imx8mn: drop unused pll enum
The PLL enum definition is not used, so drop it.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1571122989-29361-1-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 13:08:06 -07:00
YueHaibing b8cb1ef95b clk: ast2600: remove unused variable 'eclk_parent_names'
drivers/clk/clk-ast2600.c:119:27: warning:
 eclk_parent_names defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20191015115117.23504-1-yuehaibing@huawei.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-16 13:05:19 -07:00
YueHaibing 50bf025b75 clk: meson: axg-audio: use devm_platform_ioremap_resource() to simplify code
Use devm_platform_ioremap_resource() to simplify the code a bit.
This is detected by coccinelle.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-14 17:06:27 +02:00
YueHaibing 8f2d3c1759 clk: imx: clk-pll14xx: Make two variables static
Fix sparse warnings:

drivers/clk/imx/clk-pll14xx.c:44:37:
 warning: symbol 'imx_pll1416x_tbl' was not declared. Should it be static?
drivers/clk/imx/clk-pll14xx.c:57:37:
 warning: symbol 'imx_pll1443x_tbl' was not declared. Should it be static?

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Reviewed-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-14 21:22:20 +08:00
Laurentiu Palcu f0b1d7f2e7 clk: imx8mq: Add VIDEO2_PLL clock
This clock is needed by DCSS when high resolutions are used.

Signed-off-by: Laurentiu Palcu <laurentiu.palcu@nxp.com>
CC: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-14 19:27:23 +08:00
Jerome Brunet be4fe445a6 clk: meson: axg_audio: add sm1 support
Add sm1 support the axg audio clock controllers. This new version is
indeed derived from the previous generation, as always, adding a few
new clocks to the mix.

The number of gates now exceeds 32 and do not fit in a single register.
Unfortunately, designers chose to introduce the new gate register
immediately after the original one, at the beginning of the register
space, shifting all the master clock register offsets.

The sm1 also introduce a few mux and divider on the top clock path,
possibly to lower the peripheral clocks of the audio blocks if
necessary.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08 09:29:23 +02:00
Jerome Brunet cf52db456f clk: meson: axg-audio: provide clk top signal name
The peripheral clock on the sm1 goes through some muxes
and dividers before reaching the audio gates. To model that,
without repeating our self too much, the "top" clock signal
is introduced and will serve as a the parent of the gates.

On the axg and g12a, the top clock is just a pass-through to
the audio peripheral clock provided by the main controller.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08 09:29:23 +02:00
Jerome Brunet 8ff93f2832 clk: meson: axg-audio: prepare sm1 addition
Rearrange the macro definition of the clocks of the axg-audio
controller. Also, the sm1 variant will feature tiny modification
of different blocks in this controller. Because of that, we need
to fallback to the old way of defining parent for some of the
clocks, using signal name.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08 09:29:22 +02:00
Jerome Brunet 255cab9d27 clk: meson: axg-audio: fix regmap last register
Since the addition of the g12a, the last register is
AUDIO_CLK_SPDIFOUT_B_CTRL.

Fixes: 075001385c ("clk: meson: axg-audio: add g12a support")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08 09:29:21 +02:00
Jerome Brunet 38340cb2ac clk: meson: axg-audio: remove useless defines
Defining the number of each input type is no longer necessary since
we are not using the clk-input hack anymore

Fixes: 282420eed2 ("clk: meson: axg-audio: migrate to the new parent description method")
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-08 09:29:21 +02:00
Biju Das 56278c8fcb clk: renesas: r8a774b1: Add TMU clock
This patch adds the TMU clocks to the R8A774B1 SoC.

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1569249688-15821-1-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-07 14:29:53 +02:00
Anson Huang 0ae4fbc63c clk: imx8mn: Use common 1443X/1416X PLL clock structure
Use common 1413X/1416X PLL clock structure to save a lot
of duplicated code on i.MX8MN clock driver.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-06 10:13:30 +08:00
Anson Huang 43cdaa1567 clk: imx8mm: Move 1443X/1416X PLL clock structure to common place
Many i.MX8M SoCs use same 1443X/1416X PLL, such as i.MX8MM,
i.MX8MN and later i.MX8M SoCs, moving these PLL definitions
to pll14xx driver can save a lot of duplicated code on each
platform.

Meanwhile, no need to define PLL clock structure for every
module which uses same type of PLL, e.g., audio/video/dram use
1443X PLL, arm/gpu/vpu/sys use 1416X PLL, define 2 PLL clock
structure for each group is enough.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-06 10:13:01 +08:00
Leonard Crestez 094234fcf4 clk: imx: pll14xx: Fix quick switch of S/K parameter
The PLL14xx on imx8m can change the S and K parameter without requiring
a reset and relock of the whole PLL.

Fix clk_pll144xx_mp_change register reading and use it for pll1443 as
well since no reset+relock is required on K changes either.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Fixes: 8646d4dcc7 ("clk: imx: Add PLLs driver for imx8mm soc")
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-10-06 09:04:15 +08:00
Miquel Raynal e7ea59b6dc clk: mvebu: armada-37xx-periph: change suspend/resume time
Armada 3700 PCIe IP relies on the PCIe clock managed by this
driver. For reasons related to the PCI core's organization when
suspending/resuming, PCI host controller drivers must reconfigure
their registers at suspend_noirq()/resume_noirq() which happens after
suspend()/suspend_late() and before resume_early()/resume().

Device link support in the clock framework enforce that the clock
driver's resume() callback will be called before the PCIe
driver's. But, any resume_noirq() callback will be called before all
the registered resume() callbacks.

The solution to support PCIe resume operation is to change the
"priority" of this clock driver PM callbacks to "_noirq()".

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190627125245.26788-3-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 14:00:20 -07:00
Miquel Raynal 4d8fb49484 clk: mvebu: armada-37xx-periph: add PCIe gated clock
The PCIe clock is a gated clock which has the same source as GbE0
(both IPs share a set of registers). This source clock is called
'gbe_core' in the driver.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190627125245.26788-2-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 14:00:20 -07:00
Eugen Hristev 2200ab6a74 clk: at91: sam9x60: fix programmable clock
The prescaler mask for sam9x60 must be 0xff (8 bits).
Being set to 0, means that we cannot set any prescaler, thus the
programmable clocks do not work (except the case with prescaler 0)
Set the mask accordingly in layout struct.

Fixes: 01e2113de9 ("clk: at91: add sam9x60 pmc driver")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1569321191-27606-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 13:59:07 -07:00
Ben Dooks 9999157111 clk: hisilicon: fix sparse warnings in clk-hi3660.c
Fix sparse warnings of a 0 being used for a pointer by removing it from
the initialiser.

drivers/clk/hisilicon/clk-hi3660.c:336:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:338:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:340:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:342:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:344:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:346:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:348:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:350:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:352:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:354:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:356:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:358:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:360:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:362:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:364:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:366:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:368:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:370:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:372:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:374:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:376:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:378:71: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:423:68: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:425:68: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:427:68: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:429:68: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:449:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:451:71: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:453:71: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3660.c:455:71: warning: Using plain integer as NULL pointer

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Link: https://lkml.kernel.org/r/20190925112347.14141-2-ben.dooks@codethink.co.uk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 13:31:33 -07:00
Ben Dooks 9c2b87a6c2 clk: hisilicon: fix sparse warnings in clk-hi3670.c
Fix the following warnings from sparse by removing the 0 initialiser
that is actually a pointer.

drivers/clk/hisilicon/clk-hi3670.c:298:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:300:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:302:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:304:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:306:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:308:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:310:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:312:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:314:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:316:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:318:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:320:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:322:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:324:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:326:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:328:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:330:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:332:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:334:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:336:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:338:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:340:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:342:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:344:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:346:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:348:65: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:350:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:352:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:488:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:490:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:492:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:494:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:496:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:498:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:500:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:502:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:504:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:506:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:508:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:510:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:512:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:514:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:516:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:518:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:520:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:522:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:524:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:526:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:528:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:530:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:532:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:534:71: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:536:71: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:538:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:611:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:614:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:616:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:653:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:655:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:657:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:659:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:661:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:663:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:665:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:735:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:737:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:739:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:741:63: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:743:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:745:64: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:802:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:804:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:806:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:808:69: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:810:70: warning: Using plain integer as NULL pointer
drivers/clk/hisilicon/clk-hi3670.c:812:69: warning: Using plain integer as NULL pointer

Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Link: https://lkml.kernel.org/r/20190925112347.14141-1-ben.dooks@codethink.co.uk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 13:31:33 -07:00
Guido Günther 8ad1193eae clk: bd718x7: Add MODULE_ALIAS()
This fixes device probing when built as a module.

Signed-off-by: Guido Günther <agx@sigxcpu.org>
Link: https://lkml.kernel.org/r/e1d01b68cdf7dbff9bdd03bab953f828431ad292.1569875042.git.agx@sigxcpu.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-10-03 10:51:11 -07:00
Olof Johansson bcec1221c9 Fixes for omaps for v5.4-rc cycle
Here are fixes for omaps to deal with few regressions, and to fix
 more boot time errors and warnings:
 
 - The recent ti-sysc interconnect target module driver changes had
   incorrect clock bits for both clocks and dts that cause warnings
 
 - For omap3-gta04, gpio changes caused the LCD to break a while back,
   and after discussing things the right fix is to set spi-cs-high
 
 - Recent omapdrm changes to use generic panels caused tfp410 to be
   disabled as we now must enable the generic support for it in
   defconfig
 
 - Recent omapdrm and backlight changes also finally made droid4 LCD
   to work, so let's enable it in the defconfig it can be used out
   of the box. This is not strictly a fix, but we still also have the
   older CONFIG_MFD_TI_LMU options available so this cuts down the
   confusion for trying to guess which display and which backlight
   is needed
 
 - Recent ti-sysc interconnect target module changes need the gpio
   module disabled on some boards, but this now needs to happen at
   the module level, not at the gpio driver level
 
 - Recent changes to probe system timers with ti-sysc caused warnings
   about mismatch in syconfig registers, so let's configure the option
   for RESET_STATUS as available in the TRMs
 
 - Recent changes to probe LCDC with ti-sysc caused warnings about
   mismatch in sysconfig registers, so let's configure the missing
   idlemodes for both platform data and dts as documented in TRMs
 
 - Since we moved mach-omap2 to probe with device tree, we've been
   getting voltage controller warnings. Turns out this code is no
   longer needed, so let's just remove omap2_set_init_voltage() to
   get rid of the pointless warnings
 
 - Configure am4372 dispc memory bandwidth to avoid underflow errors
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Merge tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/fixes

Fixes for omaps for v5.4-rc cycle

Here are fixes for omaps to deal with few regressions, and to fix
more boot time errors and warnings:

- The recent ti-sysc interconnect target module driver changes had
  incorrect clock bits for both clocks and dts that cause warnings

- For omap3-gta04, gpio changes caused the LCD to break a while back,
  and after discussing things the right fix is to set spi-cs-high

- Recent omapdrm changes to use generic panels caused tfp410 to be
  disabled as we now must enable the generic support for it in
  defconfig

- Recent omapdrm and backlight changes also finally made droid4 LCD
  to work, so let's enable it in the defconfig it can be used out
  of the box. This is not strictly a fix, but we still also have the
  older CONFIG_MFD_TI_LMU options available so this cuts down the
  confusion for trying to guess which display and which backlight
  is needed

- Recent ti-sysc interconnect target module changes need the gpio
  module disabled on some boards, but this now needs to happen at
  the module level, not at the gpio driver level

- Recent changes to probe system timers with ti-sysc caused warnings
  about mismatch in syconfig registers, so let's configure the option
  for RESET_STATUS as available in the TRMs

- Recent changes to probe LCDC with ti-sysc caused warnings about
  mismatch in sysconfig registers, so let's configure the missing
  idlemodes for both platform data and dts as documented in TRMs

- Since we moved mach-omap2 to probe with device tree, we've been
  getting voltage controller warnings. Turns out this code is no
  longer needed, so let's just remove omap2_set_init_voltage() to
  get rid of the pointless warnings

- Configure am4372 dispc memory bandwidth to avoid underflow errors

* tag 'omap-for-v5.4/fixes-rc1-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: am4372: Set memory bandwidth limit for DISPC
  ARM: OMAP2+: Fix warnings with broken omap2_set_init_voltage()
  ARM: OMAP2+: Add missing LCDC midlemode for am335x
  ARM: OMAP2+: Fix missing reset done flag for am3 and am43
  ARM: dts: Fix gpio0 flags for am335x-icev2
  ARM: omap2plus_defconfig: Enable more droid4 devices as loadable modules
  ARM: omap2plus_defconfig: Enable DRM_TI_TFP410
  DTS: ARM: gta04: introduce legacy spi-cs-high to make display work again
  ARM: dts: Fix wrong clocks for dra7 mcasp
  clk: ti: dra7: Fix mcasp8 clock bits

Link: https://lore.kernel.org/r/pull-1570040410-308159@atomide.com
Signed-off-by: Olof Johansson <olof@lixom.net>
2019-10-03 09:15:19 -07:00
Jernej Skrabec 834f65e18c
clk: sunxi-ng: h6: Allow GPU to change parent rate
GPU PLL was designed with dynamic frequency switching in mind so driver
can adjust rate based on the GPU load.

Allow GPU clock to change parent rate (GPU PLL is the only possible
parent of GPU clock).

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-10-02 08:05:40 +02:00
Neil Armstrong 90b171f603 clk: meson: g12a: set CLK_MUX_ROUND_CLOSEST on the cpu clock muxes
When setting the 100MHz, 500MHz, 666MHz and 1GHz rate for CPU clocks,
CCF will use the SYS_PLL to handle these frequencies, but:
- using FIXED_PLL derived FCLK_DIV2/DIV3 clocks is more precise
- the Amlogic G12A/G12B/SM1 Suspend handling in firmware doesn't
  handle entering suspend using SYS_PLL for these frequencies

Adding CLK_MUX_ROUND_CLOSEST on all the muxes of the non-SYS_PLL
cpu clock tree helps CCF always selecting the FCLK_DIV2/DIV3 as source
for these frequencies.

Fixes: ffae8475b9 ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01 14:51:15 +02:00
Neil Armstrong 4a079643fc clk: meson: g12a: fix cpu clock rate setting
CLK_SET_RATE_NO_REPARENT is wrongly set on the g12a cpu premux0 clocks
flags, and CLK_SET_RATE_PARENT is required for the g12a cpu premux0 clock
and the g12b cpub premux0 clock, otherwise CCF always selects the SYS_PLL
clock to feed the cpu cluster.

Fixes: ffae8475b9 ("clk: meson: g12a: add notifiers to handle cpu clock change")
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01 14:51:07 +02:00
Martin Blumenstingl 44b09b11b8 clk: meson: gxbb: let sar_adc_clk_div set the parent clock rate
The meson-saradc driver manually sets the input clock for
sar_adc_clk_sel. Update the GXBB clock driver (which is used on GXBB,
GXL and GXM) so the rate settings on sar_adc_clk_div are propagated up
to sar_adc_clk_sel which will let the common clock framework select the
best matching parent clock if we want that.

This makes sar_adc_clk_div consistent with the axg-aoclk and g12a-aoclk
drivers, which both also specify CLK_SET_RATE_PARENT.

Fixes: 33d0fcdfe0 ("clk: gxbb: add the SAR ADC clocks and expose them")
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-10-01 14:46:30 +02:00
Biju Das 0b9f1c2c2f clk: renesas: cpg-mssr: Add r8a774b1 support
Add RZ/G2N (R8A774B1) Clock Pulse Generator / Module Standby and Software
Reset support.

Based on the Table 8.4d of "RZ/G Series, 2nd Generation User's Manual:
Hardware (Rev. 0.80, May 2019)".

Signed-off-by: Biju Das <biju.das@bp.renesas.com>
Link: https://lore.kernel.org/r/1568881036-4404-7-git-send-email-biju.das@bp.renesas.com
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01 10:24:38 +02:00
Geert Uytterhoeven 8a6d97a46d clk: renesas: rcar-gen3: Loop to find best rate in cpg_sd_clock_round_rate()
cpg_sd_clock_round_rate() really needs the best rate, not the best
divider.  Hence change the iteration to find the former, and get rid of
the final division.

Add an out-of-range rate check while at it.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-6-geert+renesas@glider.be
2019-10-01 10:24:55 +02:00
Geert Uytterhoeven f1195d4ec7 clk: renesas: rcar-gen3: Absorb cpg_sd_clock_calc_div()
cpg_sd_clock_round_rate() is the sole caller of cpg_sd_clock_calc_div(),
hence absorb the latter into the former.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-5-geert+renesas@glider.be
2019-10-01 10:24:52 +02:00
Geert Uytterhoeven e8adb3a0f7 clk: renesas: rcar-gen3: Avoid double table iteration in SD .set_rate()
The .set_rate() callback for the SD clocks is always called with a valid
clock rate, returned by .round_rate().  Hence there is no need to
iterate through the divider table twice: once to repeat the work done by
.round_rate(), and a second time to find the corresponding divider
entry.

Just iterate once, looking for the divider that matches the passed clock
rate.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-4-geert+renesas@glider.be
2019-10-01 10:24:49 +02:00
Geert Uytterhoeven b5dea62d34 clk: renesas: rcar-gen3: Improve arithmetic divisions
- Use div64_ul() instead of div_u64() if the divisor is unsigned long,
    to avoid truncation to 32-bit on 64-bit platforms,
  - Use div_u64() for 64-by-32 divisions.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-3-geert+renesas@glider.be
2019-10-01 10:24:46 +02:00
Geert Uytterhoeven 3e8c1d4cce clk: renesas: rcar-gen2: Improve arithmetic divisions
- Use div64_ul() instead of div_u64() if the divisor is unsigned long,
    to avoid truncation to 32-bit on 64-bit platforms,
  - Prefer ULL constant suffixes over casts to u64,
  - Prioritize multiplication over division, to increase accuracy.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Niklas Söderlund <niklas.soderlund+renesas@ragnatech.se>
Link: https://lore.kernel.org/r/20190830134515.11925-2-geert+renesas@glider.be
2019-10-01 10:24:43 +02:00
Geert Uytterhoeven 58256143cf clk: renesas: Remove R-Car Gen2 legacy DT clock support
As of commit 362b334b17 ("ARM: dts: r8a7791: Convert to new
CPG/MSSR bindings"), all upstream R-Car Gen2 device tree source files
use the unified "Renesas Clock Pulse Generator / Module Standby and
Software Reset" DT bindings.

Hence remove backward compatibility with old R-Car Gen2 device trees
describing a hierarchical representation of the various CPG and MSTP
clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Link: https://lore.kernel.org/r/20190830133615.11274-1-geert+renesas@glider.be
2019-10-01 10:24:38 +02:00
Markus Elfring ba28236e04 clk: renesas: mstp: Delete unnecessary kfree() in cpg_mstp_clocks_init()
A NULL pointer would be passed to a call of the function kfree()
directly after a call of the function kzalloc() failed at one place.
Remove this superfluous function call.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Link: https://lore.kernel.org/r/e66b822b-026b-29cc-e461-6334aafd1d30@web.de
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-10-01 09:50:28 +02:00
Jernej Skrabec 3ee5f8ab5e
clk: sunxi-ng: h6: Use sigma-delta modulation for audio PLL
Audio devices needs exact clock rates in order to correctly reproduce
the sound. Until now, only integer factors were used to configure H6
audio PLL which resulted in inexact rates. Fix that by adding support
for fractional factors using sigma-delta modulation look-up table. It
contains values for two most commonly used audio base frequencies.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <mripard@kernel.org>
2019-09-30 22:12:27 +02:00
Tony Lindgren dd8882a255 clk: ti: dra7: Fix mcasp8 clock bits
There's a typo for dra7 mcasp clkctrl bit, it should be 22 like the other
macasp instances, and not 24. And in dra7xx_clks[] we have the bits wrong
way around.

Fixes: dffa9051d5 ("clk: ti: dra7: add new clkctrl data")
Cc: linux-clk@vger.kernel.org
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Suman Anna <s-anna@ti.com>
Cc: Tero Kristo <t-kristo@ti.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-09-23 10:32:37 -07:00
Linus Torvalds 5c6bd5de3c Main MIPS changes for v5.4:
- boot_mem_map is removed, providing a nice cleanup made possible by the
   recent removal of bootmem.
 
 - Some fixes to atomics, in general providing compiler barriers for
   smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs or
   MIPS32 systems using cmpxchg64().
 
 - Conversion to the new generic VDSO infrastructure courtesy of Vincenzo
   Frascino.
 
 - Removal of undefined behavior in set_io_port_base(), fixing the
   behavior of some MIPS kernel configurations when built with recent
   clang versions.
 
 - Initial MIPS32 huge page support, functional on at least Ingenic SoCs.
 
 - pte_special() is now supported for some configurations, allowing among
   other things generic fast GUP to be used.
 
 - Miscellaneous fixes & cleanups.
 
 And platform specific changes:
 
 - Major improvements to Ingenic SoC support from Paul Cercueil, mostly
   enabled by the inclusion of the new TCU (timer-counter unit) drivers
   he's spent a very patient year or so working on. Plus some fixes for
   X1000 SoCs from Zhou Yanjie.
 
 - Netgear R6200 v1 systems are now supported by the bcm47xx platform.
 
 - DT updates for BMIPS, Lantiq & Microsemi Ocelot systems.
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Merge tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux

Pull MIPS updates from Paul Burton:
 "Main MIPS changes:

   - boot_mem_map is removed, providing a nice cleanup made possible by
     the recent removal of bootmem.

   - Some fixes to atomics, in general providing compiler barriers for
     smp_mb__{before,after}_atomic plus fixes specific to Loongson CPUs
     or MIPS32 systems using cmpxchg64().

   - Conversion to the new generic VDSO infrastructure courtesy of
     Vincenzo Frascino.

   - Removal of undefined behavior in set_io_port_base(), fixing the
     behavior of some MIPS kernel configurations when built with recent
     clang versions.

   - Initial MIPS32 huge page support, functional on at least Ingenic
     SoCs.

   - pte_special() is now supported for some configurations, allowing
     among other things generic fast GUP to be used.

   - Miscellaneous fixes & cleanups.

  And platform specific changes:

   - Major improvements to Ingenic SoC support from Paul Cercueil,
     mostly enabled by the inclusion of the new TCU (timer-counter unit)
     drivers he's spent a very patient year or so working on. Plus some
     fixes for X1000 SoCs from Zhou Yanjie.

   - Netgear R6200 v1 systems are now supported by the bcm47xx platform.

   - DT updates for BMIPS, Lantiq & Microsemi Ocelot systems"

* tag 'mips_5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/mips/linux: (89 commits)
  MIPS: Detect bad _PFN_SHIFT values
  MIPS: Disable pte_special() for MIPS32 with RiXi
  MIPS: ralink: deactivate PCI support for SOC_MT7621
  mips: compat: vdso: Use legacy syscalls as fallback
  MIPS: Drop Loongson _CACHE_* definitions
  MIPS: tlbex: Remove cpu_has_local_ebase
  MIPS: tlbex: Simplify r3k check
  MIPS: Select R3k-style TLB in Kconfig
  MIPS: PCI: refactor ioc3 special handling
  mips: remove ioremap_cachable
  mips/atomic: Fix smp_mb__{before,after}_atomic()
  mips/atomic: Fix loongson_llsc_mb() wreckage
  mips/atomic: Fix cmpxchg64 barriers
  MIPS: Octeon: remove duplicated include from dma-octeon.c
  firmware: bcm47xx_nvram: Allow COMPILE_TEST
  firmware: bcm47xx_nvram: Correct size_t printf format
  MIPS: Treat Loongson Extensions as ASEs
  MIPS: Remove dev_err() usage after platform_get_irq()
  MIPS: dts: mscc: describe the PTP ready interrupt
  MIPS: dts: mscc: describe the PTP register range
  ...
2019-09-22 09:30:30 -07:00
Linus Torvalds f97c81dc6c ARM: SoC: late updates for v5.4
This is some material that we picked up into our tree late or
 that had complex inter-depondencies. The fact that there are these
 interdependencies tends to meant that these are often actually the most
 interesting new additions:
 
 The new Aspeed AST2600 baseboard management controller is added, this
 is a Cortex-A7 based follow-up to the ARM11 based AST2500 and had some
 dependencies on other device drivers.
 
 After many years, support for the MMP2 based OLPC XO-1.75 finally makes
 it into the kernel.
 
 The Armada 3720 based Turris Mox open source router platform is a late
 addition and it follows some preparatory work across multiple branches.
 
 The OMAP2+ platform had some large-scale cleanup involving driver
 changes and DT changes, here we finish it off, dropping a lot of the
 now-unused platform data.
 
 The TI K3 platform that got added for 5.3 gains a lot more support
 for individual bits on the SoC, this part just came late for the
 merge window.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC late updates from Arnd Bergmann:
 "This is some material that we picked up into our tree late or that had
  complex inter-depondencies. The fact that there are these
  interdependencies tends to meant that these are often actually the
  most interesting new additions:

   - The new Aspeed AST2600 baseboard management controller is added,
     this is a Cortex-A7 based follow-up to the ARM11 based AST2500 and
     had some dependencies on other device drivers.

   - After many years, support for the MMP2 based OLPC XO-1.75 finally
     makes it into the kernel.

   - The Armada 3720 based Turris Mox open source router platform is a
     late addition and it follows some preparatory work across multiple
     branches.

   - The OMAP2+ platform had some large-scale cleanup involving driver
     changes and DT changes, here we finish it off, dropping a lot of
     the now-unused platform data.

   - The TI K3 platform that got added for 5.3 gains a lot more support
     for individual bits on the SoC, this part just came late for the
     merge window"

[ This pull request itself wasn't actually sent late at all by Arnd, but
  I waited on the branches that it used to be pulled first, so it ends
  up being merged much later than the other ARM SoC pull requests this
  merge window     - Linus ]

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (57 commits)
  ARM: dts: dir685: Drop spi-cpol from the display
  ARM: dts: aspeed: Add AST2600 pinmux nodes
  ARM: dts: aspeed: Add AST2600 and EVB
  ARM: exynos: Enable support for ARM architected timers
  ARM: samsung: Fix system restart on S3C6410
  ARM: dts: mmp2: add OLPC XO 1.75 machine
  ARM: dts: mmp2: rename the USB PHY node
  ARM: dts: mmp2: specify reg-shift for the UARTs
  ARM: dts: mmp2: add camera interfaces
  ARM: dts: mmp2: fix the SPI nodes
  ARM: dts: mmp2: trivial whitespace fix
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: ti: k3-j721e-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-am65-main: Fix gic-its node unit-address
  arm64: dts: ti: k3-j721e-main: Add hwspinlock node
  arm64: dts: ti: k3-am65-main: Add hwspinlock node
  arm64: dts: k3-j721e: Add gpio-keys on common processor board
  dt-bindings: pinctrl: k3: Introduce pinmux definitions for J721E
  ...
2019-09-20 15:53:02 -07:00
Linus Torvalds a703d279c5 We have a small collection of core framework updates this time, mostly around
clk registration by clk providers and debugfs "nice to haves" for rate
 constraints. I'll highlight that we're now setting the clk_init_data pointer
 inside struct clk_hw to NULL during clk_register(), which may break some
 drivers that thought they could use that pointer during normal operations. That
 change has been sitting in next for a while now but maybe something is still
 broken. We'l see. Other than that the core framework changes aren't invasive
 and they're fixing bugs, simplifying, and making things better.
 
 On the clk driver side we got the usual addition of new SoC support, new
 features for existing drivers, and bug fixes scattered throughout. The biggest
 diffstat is the Amlogic driver that gained CPU clk support in addition to
 migrating to the new way of specifying clk parents. After that the Qualcomm,
 i.MX, Mediatek, and Rockchip clk drivers got support for various new SoCs and
 clock controllers from those vendors.
 
 Core:
  - Drop NULL checks in clk debugfs
  - Add min/max rates to clk debugfs
  - Set clk_init_data pointer inside clk_hw to NULL after registration
  - Make clk_bulk_get_all() return an 'id' corresponding to clock-names
  - Evict parents from parent cache when they're unregistered
 
 New Drivers:
  - Add clock driver for i.MX8MN SoCs
  - Support aspeed AST2600 SoCs
  - Support for Mediatek MT6779 SoCs
  - Support qcom SM8150 GCC and RPMh clks
  - Support qcom QCS404 WCSS clks
  - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
  - Addition of clock driver for Rockchip rk3308 SoCs
 
 Updates:
  - Add regulator support to the cdce925 clk driver
  - Add support for Raspberry Pi 4 bcm2711 SoCs
  - Add SDIO gate support to aspeed driver
  - Add missing of_node_put() calls in various clk drivers
  - Migrate Amlogic driver to new clock parent description method
  - Add DVFS support to Amlogic Meson g12
  - Add Amlogic Meson g12a reset support to the axg audio clock controller
  - Add sm1 support to the Amlogic Meson g12a clock controller
  - Switch i.MX8MM clock driver to platform driver
  - Add Hifi4 DSP related clocks for i.MX8QXP SoC
  - Fix Audio PLL setting and parent clock for USB
  - Misc i.MX8 clock driver improvements and corrections
  - Set floor ops for Qualcomm SD clks so that rounding works
  - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
  - Enable the Allwinner V3 SoC and fix the i2s clock for H6
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "We have a small collection of core framework updates this time, mostly
  around clk registration by clk providers and debugfs "nice to haves"
  for rate constraints. I'll highlight that we're now setting the
  clk_init_data pointer inside struct clk_hw to NULL during
  clk_register(), which may break some drivers that thought they could
  use that pointer during normal operations. That change has been
  sitting in next for a while now but maybe something is still broken.
  We'l see. Other than that the core framework changes aren't invasive
  and they're fixing bugs, simplifying, and making things better.

  On the clk driver side we got the usual addition of new SoC support,
  new features for existing drivers, and bug fixes scattered throughout.
  The biggest diffstat is the Amlogic driver that gained CPU clk support
  in addition to migrating to the new way of specifying clk parents.
  After that the Qualcomm, i.MX, Mediatek, and Rockchip clk drivers got
  support for various new SoCs and clock controllers from those vendors.

  Core:
   - Drop NULL checks in clk debugfs
   - Add min/max rates to clk debugfs
   - Set clk_init_data pointer inside clk_hw to NULL after registration
   - Make clk_bulk_get_all() return an 'id' corresponding to clock-names
   - Evict parents from parent cache when they're unregistered

  New Drivers:
   - Add clock driver for i.MX8MN SoCs
   - Support aspeed AST2600 SoCs
   - Support for Mediatek MT6779 SoCs
   - Support qcom SM8150 GCC and RPMh clks
   - Support qcom QCS404 WCSS clks
   - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)
   - Addition of clock driver for Rockchip rk3308 SoCs

  Updates:
   - Add regulator support to the cdce925 clk driver
   - Add support for Raspberry Pi 4 bcm2711 SoCs
   - Add SDIO gate support to aspeed driver
   - Add missing of_node_put() calls in various clk drivers
   - Migrate Amlogic driver to new clock parent description method
   - Add DVFS support to Amlogic Meson g12
   - Add Amlogic Meson g12a reset support to the axg audio clock controller
   - Add sm1 support to the Amlogic Meson g12a clock controller
   - Switch i.MX8MM clock driver to platform driver
   - Add Hifi4 DSP related clocks for i.MX8QXP SoC
   - Fix Audio PLL setting and parent clock for USB
   - Misc i.MX8 clock driver improvements and corrections
   - Set floor ops for Qualcomm SD clks so that rounding works
   - Fix "always-on" Clock Domains on Renesas R-Car M1A, RZ/A1, RZ/A2, and RZ/N1
   - Enable the Allwinner V3 SoC and fix the i2s clock for H6"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (137 commits)
  clk: Drop !clk checks in debugfs dumping
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: mvebu: ap80x: add AP807 clock support
  clk: mvebu: ap806: Prepare the introduction of AP807 clock support
  clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
  clk: mvebu: ap806: be more explicit on what SaR is
  clk: mvebu: ap80x-cpu: add AP807 CPU clock support
  clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
  dt-bindings: ap806: Document AP807 clock compatible
  dt-bindings: ap80x: Document AP807 CPU clock compatible
  clk: sprd: add missing kfree
  clk: at91: allow 24 Mhz clock as input for PLL
  clk: Make clk_bulk_get_all() return a valid "id"
  clk: actions: Fix factor clk struct member access
  clk: qcom: rcg: Return failure for RCG update
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  ...
2019-09-20 15:45:07 -07:00
Stephen Boyd ebd47c8434 Merge branches 'clk-bulk-fix', 'clk-at91' and 'clk-sprd' into clk-next
- Make clk_bulk_get_all() return an 'id' corresponding to clock-names

* clk-bulk-fix:
  clk: Make clk_bulk_get_all() return a valid "id"

* clk-at91:
  clk: at91: allow 24 Mhz clock as input for PLL
  clk: at91: select parent if main oscillator or bypass is enabled
  clk: at91: fix update bit maps on CFG_MOR write

* clk-sprd:
  clk: sprd: add missing kfree
2019-09-19 15:31:59 -07:00
Stephen Boyd b6c444de05 Merge branches 'clk-cdce-regulator', 'clk-bcm', 'clk-evict-parent-cache' and 'clk-actions' into clk-next
- Add regulator support to the cdce925 clk driver
 - Add support for Raspberry Pi 4 bcm2711 SoCs
 - Evict parents from parent cache when they're unregistered

* clk-cdce-regulator:
  clk: clk-cdce925: Add regulator support
  dt-bindings: clock: cdce925: Add regulator documentation

* clk-bcm:
  clk: bcm2835: Mark PLLD_PER as CRITICAL
  clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
  clk: bcm2835: Introduce SoC specific clock registration
  dt-bindings: bcm2835-cprman: Add bcm2711 support

* clk-evict-parent-cache:
  clk: Evict unregistered clks from parent caches

* clk-actions:
  clk: actions: Fix factor clk struct member access
2019-09-19 15:31:46 -07:00
Stephen Boyd 91bcbc11d6 Merge branches 'clk-renesas', 'clk-rockchip', 'clk-const' and 'clk-simplify' into clk-next
* clk-renesas:
  clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
  clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
  clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
  dt-bindings: clk: emev2: Rename bindings documentation file
  clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper

* clk-rockchip:
  clk: rockchip: Add clock controller for the rk3308
  clk: rockchip: Add dt-binding header for rk3308
  dt-bindings: Add bindings for rk3308 clock controller
  clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver

* clk-const:
  clk: spear: Make structure i2s_sclk_masks constant

* clk-simplify:
  clk/ti: Use kmemdup rather than duplicating its implementation
  clk: fix devm_platform_ioremap_resource.cocci warnings
2019-09-19 15:31:41 -07:00
Stephen Boyd a1ff1ce300 Merge branches 'clk-init-destroy', 'clk-doc', 'clk-imx' and 'clk-allwinner' into clk-next
- Set clk_init_data pointer inside clk_hw to NULL after registration

* clk-init-destroy:
  clk: Overwrite clk_hw::init with NULL during clk_register()
  clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
  clk: ti: Don't reference clk_init_data after registration
  clk: qcom: Remove error prints from DFS registration
  rtc: sun6i: Don't reference clk_init_data after registration
  clk: zx296718: Don't reference clk_init_data after registration
  clk: milbeaut: Don't reference clk_init_data after registration
  clk: socfpga: deindent code to proper indentation
  phy: ti: am654-serdes: Don't reference clk_init_data after registration
  clk: sprd: Don't reference clk_init_data after registration
  clk: socfpga: Don't reference clk_init_data after registration
  clk: sirf: Don't reference clk_init_data after registration
  clk: qcom: Don't reference clk_init_data after registration
  clk: meson: axg-audio: Don't reference clk_init_data after registration
  clk: lochnagar: Don't reference clk_init_data after registration
  clk: actions: Don't reference clk_init_data after registration

* clk-doc:
  clk: remove extra ---help--- tags in Kconfig
  clk: add include guard to clk-conf.h
  clk: Document of_parse_clkspec() some more
  clk: Remove extraneous 'for' word in comments

* clk-imx: (32 commits)
  clk: imx: imx8mn: fix pll mux bit
  clk: imx: imx8mm: fix pll mux bit
  clk: imx: clk-pll14xx: unbypass PLL by default
  clk: imx: pll14xx: avoid glitch when set rate
  clk: imx: imx8mn: fix audio pll setting
  clk: imx8mn: Add necessary frequency support for ARM PLL table
  clk: imx8mn: Add missing rate_count assignment for each PLL structure
  clk: imx8mn: fix int pll clk gate
  clk: imx8mn: Add GIC clock
  clk: imx8mn: Fix incorrect parents
  clk: imx8mm: Fix incorrect parents
  clk: imx8mq: Fix sys3 pll references
  clk: imx8mq: Unregister clks when of_clk_add_provider failed
  clk: imx8mm: Unregister clks when of_clk_add_provider failed
  clk: imx8mq: Mark AHB clock as critical
  clk: imx8mn: Keep uart clocks on for early console
  clk: imx: Remove unused function statement
  clk: imx7ulp: Make sure earlycon's clock is enabled
  clk: imx8mm: Switch to platform driver
  clk: imx: imx8mm: fix audio pll setting
  ...

* clk-allwinner:
  clk: sunxi-ng: h6: Allow I2S to change parent rate
  clk: sunxi-ng: v3s: add Allwinner V3 support
  clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
  dt-bindings: clk: sunxi-ccu: add compatible string for V3 CCU
  clk: sunxi-ng: v3s: add the missing PLL_DDR1
2019-09-19 15:31:27 -07:00
Stephen Boyd f5c7305db3 Merge branches 'clk-qcom', 'clk-mtk', 'clk-armada', 'clk-ingenic' and 'clk-meson' into clk-next
- Support qcom SM8150 RPMh clks
 - Set floor ops for qcom sd clks
 - Support qcom QCS404 WCSS clks
 - Support for Mediatek MT6779 SoCs
 - Add CPU clock support for Armada 7K/8K (specifically AP806 and AP807)

* clk-qcom:
  clk: qcom: rcg: Return failure for RCG update
  clk: qcom: fix QCS404 TuringCC regmap
  clk: qcom: clk-rpmh: Add support for SM8150
  dt-bindings: clock: Document SM8150 rpmh-clock compatible
  clk: qcom: clk-rpmh: Convert to parent data scheme
  dt-bindings: clock: Document the parent clocks
  clk: qcom: gcc: Use floor ops for SDCC clocks
  clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
  clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
  clk: qcom: define probe by index API as common API
  clk: qcom: Add WCSS gcc clock control for QCS404
  clk: qcom: msm8916: Don't build by default
  clk: qcom: gcc: Add global clock controller driver for SM8150
  dt-bindings: clock: Document gcc bindings for SM8150
  clk: qcom: clk-alpha-pll: Add support for Trion PLLs
  clk: qcom: clk-alpha-pll: Remove post_div_table checks
  clk: qcom: clk-alpha-pll: Remove unnecessary cast

* clk-mtk:
  clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
  clk: mediatek: Register clock gate with device
  clk: mediatek: add pericfg clocks for MT8183
  dt-bindings: clock: mediatek: add pericfg for MT8183
  clk: mediatek: Add MT6779 clock support
  clk: mediatek: Add dt-bindings for MT6779 clocks
  dt-bindings: mediatek: bindings for MT6779 clk
  clk: reset: Modify reset-controller driver

* clk-armada:
  clk: mvebu: ap80x: add AP807 clock support
  clk: mvebu: ap806: Prepare the introduction of AP807 clock support
  clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
  clk: mvebu: ap806: be more explicit on what SaR is
  clk: mvebu: ap80x-cpu: add AP807 CPU clock support
  clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
  dt-bindings: ap806: Document AP807 clock compatible
  dt-bindings: ap80x: Document AP807 CPU clock compatible
  clk: mvebu: ap806: Fix clock name for the cluster
  clk: mvebu: add CPU clock driver for Armada 7K/8K
  clk: mvebu: add helper file for Armada AP and CP clocks
  dt-bindings: ap806: add the cluster clock node in the syscon file

* clk-ingenic:
  clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
  clk: ingenic/jz4740: Fix "pll half" divider not read/written properly

* clk-meson: (23 commits)
  clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
  clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
  clk: meson: g12a: add support for SM1 GP1 PLL
  dt-bindings: clk: meson: add sm1 periph clock controller bindings
  clk: meson: axg-audio: add g12a reset support
  dt-bindings: clock: meson: add resets to the audio clock controller
  clk: meson: g12a: expose CPUB clock ID for G12B
  clk: meson: g12a: add notifiers to handle cpu clock change
  clk: meson: add g12a cpu dynamic divider driver
  clk: core: introduce clk_hw_set_parent()
  clk: meson: remove clk input helper
  clk: meson: remove ee input bypass clocks
  clk: meson: clk-regmap: migrate to new parent description method
  clk: meson: meson8b: migrate to the new parent description method
  clk: meson: axg: migrate to the new parent description method
  clk: meson: gxbb: migrate to the new parent description method
  clk: meson: g12a: migrate to the new parent description method
  clk: meson: remove ao input bypass clocks
  clk: meson: axg-aoclk: migrate to the new parent description method
  clk: meson: gxbb-aoclk: migrate to the new parent description method
  ...
2019-09-19 15:30:59 -07:00
Stephen Boyd cee99529ee Merge branches 'clk-aspeed', 'clk-unused', 'clk-of-node-put', 'clk-const-bulk-data' and 'clk-debugfs' into clk-next
- Add SDIO gate to aspeed driver
 - Support aspeed AST2600 SoC
 - Add missing of_node_put() calls in various clk drivers
 - Drop NULL checks in clk debugfs
 - Add min/max rates to clk debugfs

* clk-aspeed:
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate

* clk-unused:
  clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
  clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
  clk: composite: Drop unused clk.h include
  clk: Si5341/Si5340: remove redundant assignment to n_den
  clk: qoriq: Fix -Wunused-const-variable

* clk-of-node-put:
  clk: ti: dm814x: Add of_node_put() to prevent memory leak
  clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
  clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
  clk: versatile: Add of_node_put() in cm_osc_setup()

* clk-const-bulk-data:
  clk: Constify struct clk_bulk_data * where possible

* clk-debugfs:
  clk: Drop !clk checks in debugfs dumping
  clk: Use seq_puts() in possible_parent_show()
  clk: Assert prepare_lock in clk_core_get_boundaries
  clk: Add clk_min/max_rate entries in debugfs
2019-09-19 15:30:40 -07:00
Stephen Boyd 7f4804665b clk: Drop !clk checks in debugfs dumping
These recursive functions have checks for !clk being passed in, but the
callers are always looping through lists and therefore the pointers
can't be NULL. Drop the checks to simplify the code.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826234729.145593-1-sboyd@kernel.org
2019-09-19 15:26:36 -07:00
Linus Torvalds 6cfae0c26b Char/Misc driver patches for 5.4-rc1
Here is the big char/misc driver pull request for 5.4-rc1.
 
 As has been happening in previous releases, more and more individual
 driver subsystem trees are ending up in here.  Now if that is good or
 bad I can't tell, but hopefully it makes your life easier as it's more
 of an aggregation of trees together to one merge point for you.
 
 Anyway, lots of stuff in here:
 	- habanalabs driver updates
 	- thunderbolt driver updates
 	- misc driver updates
 	- coresight and intel_th hwtracing driver updates
 	- fpga driver updates
 	- extcon driver updates
 	- some dma driver updates
 	- char driver updates
 	- android binder driver updates
 	- nvmem driver updates
 	- phy driver updates
 	- parport driver fixes
 	- pcmcia driver fix
 	- uio driver updates
 	- w1 driver updates
 	- configfs fixes
 	- other assorted driver updates
 
 All of these have been in linux-next for a long time with no reported
 issues.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc

Pull char/misc driver updates from Greg KH:
 "Here is the big char/misc driver pull request for 5.4-rc1.

  As has been happening in previous releases, more and more individual
  driver subsystem trees are ending up in here. Now if that is good or
  bad I can't tell, but hopefully it makes your life easier as it's more
  of an aggregation of trees together to one merge point for you.

  Anyway, lots of stuff in here:
     - habanalabs driver updates
     - thunderbolt driver updates
     - misc driver updates
     - coresight and intel_th hwtracing driver updates
     - fpga driver updates
     - extcon driver updates
     - some dma driver updates
     - char driver updates
     - android binder driver updates
     - nvmem driver updates
     - phy driver updates
     - parport driver fixes
     - pcmcia driver fix
     - uio driver updates
     - w1 driver updates
     - configfs fixes
     - other assorted driver updates

  All of these have been in linux-next for a long time with no reported
  issues"

* tag 'char-misc-5.4-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/char-misc: (200 commits)
  misc: mic: Use PTR_ERR_OR_ZERO rather than its implementation
  habanalabs: correctly cast variable to __le32
  habanalabs: show correct id in error print
  habanalabs: stop using the acronym KMD
  habanalabs: display card name as sensors header
  habanalabs: add uapi to retrieve aggregate H/W events
  habanalabs: add uapi to retrieve device utilization
  habanalabs: Make the Coresight timestamp perpetual
  habanalabs: explicitly set the queue-id enumerated numbers
  habanalabs: print to kernel log when reset is finished
  habanalabs: replace __le32_to_cpu with le32_to_cpu
  habanalabs: replace __cpu_to_le32/64 with cpu_to_le32/64
  habanalabs: Handle HW_IP_INFO if device disabled or in reset
  habanalabs: Expose devices after initialization is done
  habanalabs: improve security in Debug IOCTL
  habanalabs: use default structure for user input in Debug IOCTL
  habanalabs: Add descriptive name to PSOC app status register
  habanalabs: Add descriptive names to PSOC scratch-pad registers
  habanalabs: create two char devices per ASIC
  habanalabs: change device_setup_cdev() to be more generic
  ...
2019-09-18 11:14:31 -07:00
Peng Fan 60a8a148b2 clk: imx: imx8mn: fix pll mux bit
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.

Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-5-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:53:34 -07:00
Peng Fan 67315be33e clk: imx: imx8mm: fix pll mux bit
pll BYPASS bit should be kept inside pll driver for glitchless freq
setting following spec. If exposing the bit, that means pll driver and
clk driver has two paths to touch this bit, which is wrong.

So use EXT_BYPASS bit here.

And drop uneeded set parent, because EXT_BYPASS default is 0.

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Suggested-by: Jacky Bai <ping.bai@nxp.com>
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-4-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:53:34 -07:00
Peng Fan a9aa830607 clk: imx: clk-pll14xx: unbypass PLL by default
When registering the PLL, unbypass the PLL.
The PLL has two bypass control bit, BYPASS and EXT_BYPASS.
we will expose EXT_BYPASS to clk driver for mux usage, and keep
BYPASS inside pll14xx usage. The PLL has a restriction that
when M/P change, need to RESET/BYPASS pll to avoid glitch, so
we could not expose BYPASS.

To make it easy for clk driver usage, unbypass PLL which does
not hurt current function.

Fixes: 8646d4dcc7 ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-3-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:53:34 -07:00
Peng Fan dee1bc9c23 clk: imx: pll14xx: avoid glitch when set rate
According to PLL1443XA and PLL1416X spec,
"When BYPASS is 0 and RESETB is changed from 0 to 1, FOUT starts to
output unstable clock until lock time passes. PLL1416X/PLL1443XA may
generate a glitch at FOUT."

So set BYPASS when RESETB is changed from 0 to 1 to avoid glitch.
In the end of set rate, BYPASS will be cleared.

When prepare clock, also need to take care to avoid glitch. So
we also follow Spec to set BYPASS before RESETB changed from 0 to 1.
And add a check if the RESETB is already 0, directly return 0;

Fixes: 8646d4dcc7 ("clk: imx: Add PLLs driver for imx8mm soc")
Reviewed-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Link: https://lkml.kernel.org/r/1568043491-20680-2-git-send-email-peng.fan@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:53:34 -07:00
Ben Peled c0448dce56 clk: mvebu: ap80x: add AP807 clock support
Add driver support for AP807 clock.

Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-9-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:41 -07:00
Ben Peled be69e55df9 clk: mvebu: ap806: Prepare the introduction of AP807 clock support
Factor out the code that is only useful to AP806 so it will be easier
to support AP807. No functional changes.

Signed-off-by: Ben Peled <bpeled@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-8-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:41 -07:00
Omri Itach 0099dc446b clk: mvebu: ap806: add AP-DCLK (hclk) to system controller driver
Add dynamic AP-DCLK clock (hclk) to system controller driver. AP-DCLK
is half the rate of DDR clock, so its derrived from Sample At Reset
configuration. The clock frequency is required for AP806 AXI monitor
profiling feature.

Signed-off-by: Omri Itach <omrii@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-7-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:41 -07:00
Miquel Raynal cd016cb018 clk: mvebu: ap806: be more explicit on what SaR is
"SaR" means Sample at Reset. DIP switches can be changed on the board,
their states at reset time is available through a register read.

Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-6-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:41 -07:00
Ben Peled 3b14e509ab clk: mvebu: ap80x-cpu: add AP807 CPU clock support
Enhance the ap-cpu-clk driver to support both AP806 and AP807 CPU
clocks.

Signed-off-by: Ben Peled <bpeled@marvell.com>
[<miquel.raynal@bootlin.com>: use device data instead of conditions on
the compatible]
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-5-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:40 -07:00
Christine Gharzuzi a77f45eaa2 clk: mvebu: ap806-cpu: prepare mapping of AP807 CPU clock
This patch allows same flow to be executed on chips with different
register mappings like AP806 and, in the future, AP807.

Note: this patch has no functional effect, and only prepares the
driver for additional chips to be supported by retrieving the right
device data depenging on the compatible property.

Signed-off-by: Christine Gharzuzi <chrisg@marvell.com>
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
Link: https://lkml.kernel.org/r/20190805100310.29048-4-miquel.raynal@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:15:40 -07:00
Chunyan Zhang 5e75ea9c67 clk: sprd: add missing kfree
The number of config registers for different pll clocks probably are not
same, so we have to use malloc, and should free the memory before return.

Fixes: 3e37b00558 ("clk: sprd: add adjustable pll support")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Chunyan Zhang <zhang.lyra@gmail.com>
Link: https://lkml.kernel.org/r/20190905103009.27166-1-zhang.lyra@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:01:02 -07:00
Eugen Hristev 81a6b601f9 clk: at91: allow 24 Mhz clock as input for PLL
The PLL input range needs to be able to allow 24 Mhz crystal as input
Update the range accordingly in plla characteristics struct

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568183622-7858-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Fixes: c561e41ce4d2 ("clk: at91: add sama5d2 PMC driver")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 22:00:31 -07:00
Bjorn Andersson 7f81c24265 clk: Make clk_bulk_get_all() return a valid "id"
The adreno driver expects the "id" field of the returned clk_bulk_data
to be filled in with strings from the clock-names property.

But due to the use of kmalloc_array() in of_clk_bulk_get_all() it
receives a list of bogus pointers instead.

Zero-initialize the "id" field and attempt to populate with strings from
the clock-names property to resolve both these issues.

Fixes: 616e45df7c ("clk: add new APIs to operate on all available clocks")
Fixes: 8e3e791d20 ("drm/msm: Use generic bulk clock function")
Cc: Dong Aisheng <aisheng.dong@nxp.com>
Cc: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190913024029.2640-1-bjorn.andersson@linaro.org
Reviewed-by: Jordan Crouse <jcrouse@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 13:26:31 -07:00
Manivannan Sadhasivam ed309bfb48 clk: actions: Fix factor clk struct member access
Since the helper "owl_factor_helper_round_rate" is shared between factor
and composite clocks, using the factor clk specific helper function
like "hw_to_owl_factor" to access its members will create issues when
called from composite clk specific code. Hence, pass the "factor_hw"
struct pointer directly instead of fetching it using factor clk specific
helpers.

This issue has been observed when a composite clock like "sd0_clk" tried
to call "owl_factor_helper_round_rate" resulting in pointer dereferencing
error.

While we are at it, let's rename the "clk_val_best" function to
"owl_clk_val_best" since this is an owl SoCs specific helper.

Fixes: 4bb78fc974 ("clk: actions: Add factor clock support")
Signed-off-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190916154546.24982-2-manivannan.sadhasivam@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 12:54:44 -07:00
Taniya Das 21ea4b62e1 clk: qcom: rcg: Return failure for RCG update
In case of update config failure, return -EBUSY, so that consumers could
handle the failure gracefully.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/1557339895-21952-2-git-send-email-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 10:29:39 -07:00
Lubomir Rintel 863e53e6ed clk: remove extra ---help--- tags in Kconfig
Sometimes an extraneous "---help---" follows "help". That is probably a
copy&paste error stemming from their inconsistent use. Remove those.

Signed-off-by: Lubomir Rintel <lkundrak@v3.sk>
Link: https://lkml.kernel.org/r/20190822093126.594013-1-lkundrak@v3.sk
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 10:27:57 -07:00
Stephen Boyd bdcf1dc253 clk: Evict unregistered clks from parent caches
We leave a dangling pointer in each clk_core::parents array that has an
unregistered clk as a potential parent when that clk_core pointer is
freed by clk{_hw}_unregister(). It is impossible for the true parent of
a clk to be set with clk_set_parent() once the dangling pointer is left
in the cache because we compare parent pointers in
clk_fetch_parent_index() instead of checking for a matching clk name or
clk_hw pointer.

Before commit ede7785847 ("clk: Remove global clk traversal on fetch
parent index"), we would check clk_hw pointers, which has a higher
chance of being the same between registration and unregistration, but it
can still be allocated and freed by the clk provider. In fact, this has
been a long standing problem since commit da0f0b2c3a ("clk: Correct
lookup logic in clk_fetch_parent_index()") where we stopped trying to
compare clk names and skipped over entries in the cache that weren't
NULL.

There are good (performance) reasons to not do the global tree lookup in
cases where the cache holds dangling pointers to parents that have been
unregistered. Let's take the performance hit on the uncommon
registration path instead. Loop through all the clk_core::parents arrays
when a clk is unregistered and set the entry to NULL when the parent
cache entry and clk being unregistered are the same pointer. This will
fix this problem and avoid the overhead for the "normal" case.

Based on a patch by Bjorn Andersson.

Fixes: da0f0b2c3a ("clk: Correct lookup logic in clk_fetch_parent_index()")
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Tested-by: Sai Prakash Ranjan <saiprakash.ranjan@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190828181959.204401-1-sboyd@kernel.org
2019-09-17 10:24:02 -07:00
Weiyi Lu 327aa74156 clk: mediatek: Runtime PM support for MT8183 mcucfg clock provider
Enable the runtime PM support and forward the struct device pointer for
registration of MT8183 mcucfg clocks.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-3-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 10:22:49 -07:00
Weiyi Lu e4c23e19aa clk: mediatek: Register clock gate with device
Allow those clocks under a power domain to do the runtime pm operation
by forwarding the struct device pointer from clock provider.

Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Link: https://lkml.kernel.org/r/1567414859-3244-2-git-send-email-weiyi.lu@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 10:22:49 -07:00
Chunfeng Yun f9e55ac22c clk: mediatek: add pericfg clocks for MT8183
Add pericfg clocks for MT8183, it's used when support USB
remote wakeup

Cc: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Chunfeng Yun <chunfeng.yun@mediatek.com>
Link: https://lkml.kernel.org/r/1566980533-28282-2-git-send-email-chunfeng.yun@mediatek.com
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-17 10:17:41 -07:00
Stefan Wahren 5c5ba218c6 clk: bcm2835: Mark PLLD_PER as CRITICAL
The VPU firmware assume that the PLLD_PER isn't modified by the ARM core.
Otherwise this could cause firmware lookups. So mark the clock as critical
to avoid this.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-17 09:55:31 -07:00
Stefan Wahren 42de9ad400 clk: bcm2835: Add BCM2711_CLOCK_EMMC2 support
The new BCM2711 supports an additional clock for the emmc2 block.
So add a new compatible and register this clock only for BCM2711.

Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-17 09:55:31 -07:00
Stefan Wahren ee0a5a9013 clk: bcm2835: Introduce SoC specific clock registration
In order to support SoC specific clocks (e.g. emmc2 for BCM2711), we
extend the description with a SoC support flag. This approach avoids long
and mostly redundant lists of clock IDs. Since PLLH is specific to
BCM2835, we register only rest of the clocks as common to all SoC.

Suggested-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Stefan Wahren <wahrenst@gmx.net>
Reviewed-by: Matthias Brugger <mbrugger@suse.com>
Acked-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Eric Anholt <eric@anholt.net>
2019-09-17 09:55:31 -07:00
Linus Torvalds cef7298262 ARM: DT updates for v5.4
This is another huge branch with close to 450 changessets related to
 devicetree files, roughly half of this for 32-bit and 64-bit respectively.
 There are lots of cleanups and additional hardware support for platforms
 we already support based on SoCs from Renesas, ST-Microelectronics,
 Intel/Altera, Rockchips, Allwinner, Broadcom and other manufacturers.
 
 A total of 6 new SoCs and 37 new boards gets added this time, one more
 SoC will come in a follow-up branch. Most of the new boards are for
 64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.
 
 Going more into details for SoC platforms with new hardware support:
 
 The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone platform,
 usually paired with an external 5G modem. So far we only support the
 Qualcomm SM8150 MTP reference platform, but no actual products.
 
 For the slightly older Qualcomm platforms, support for several interesting
 products is getting added: Three laptops based on Snapdragon 835/MSM8998
 (Asus NovaGo, HP Envy X2 and Lenovo Miix 630), one laptop based on
 Snapdragon 850/sdm850 (Lenovo Yoga C630) and several phones based on
 the older Snapdragon 410/MSM8916 (Samsung A3 and A5, Longcheer L8150
 aka Android One 2nd gen "seed" aka Wileyfox Swift).
 
 Mediatek MT7629 is a new wireless network router chip, similar to
 the older MT7623. It gets added together with the reference board
 implementation.
 
 Allwinner V3 is a repackaged version of the existing low-end V3s chip,
 and is used in the tiny Lichee Pi Zero plus, also added here.  There is
 also a new TV set-top box based on Allwinner H6, the Tanix TX6, and the
 eMMC variant of the Olimex A64-Olinuxino development board.
 
 NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC family,
 similar to the i.MX8M Mini. As usual, there is a large number of new
 boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML, SolidRun Hummingboard
 Pulse baseboard and System-on-Module, Boundary Devices i.MX8MQ Nitrogen8M,
 and TechNexion PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit,
 we get the Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
 phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
 Innovations i.MX7 RMU2 board.
 
 In a different NXP product line, the Layerscape LS1046A "Freeway"
 reference board gets added.
 
 Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from their
 set-top-box line and smart speaker with newer CPU and GPU cores compared
 to their predecessors. Both are now also supported by the Khadas VIM3
 development board series, and the dts files for that get reorganized a
 bit to better deal with all variants.  Another board based on SM1 that
 gets added is the SEI Robotics SEI610.
 
 There are a handful of new x86 and Power9 server boards using Aspeed BMC
 chips that are gaining support for running Linux on the BMC through the
 OpenBMC project: Facebook Minipack/Wedge100/Wedge40, Lenovo Hr855xg2,
 and Mihawk. Notably these are still new machines using SoCs based on
 the ARM9 and ARM11 CPU cores, as support for the new Cortex-A7 based
 AST2600 is still ramping up.
 
 There are three new end-user products using 32-bit Rockchips SoCs:
 Mecer Xtreme Mini S6 is an Android "mini PC" box based on the low-end
 RK3229 chip, while the two AOpen products Chromebox Mini (Fievel) and
 Chromebase Mini (Tiger) run ChromeOS and are meant for commercial settings
 (digital signage, PoS, ...).
 
 One more single-board computer based on the popular 64-bit RK3399 is
 added: the Leez RK3399 P710.
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM DT updates from Arnd Bergmann:
 "This is another huge branch with close to 450 changessets related to
  devicetree files, roughly half of this for 32-bit and 64-bit
  respectively. There are lots of cleanups and additional hardware
  support for platforms we already support based on SoCs from Renesas,
  ST-Microelectronics, Intel/Altera, Rockchips, Allwinner, Broadcom and
  other manufacturers.

  A total of 6 new SoCs and 37 new boards gets added this time, one more
  SoC will come in a follow-up branch. Most of the new boards are for
  64-bit ARM SoCs, the others are typically for the 32-bit Cortex-A7.

  Going more into details for SoC platforms with new hardware support:

   - The Snapdragon 855 (SM8150) is Qualcomm's current high-end phone
     platform, usually paired with an external 5G modem. So far we only
     support the Qualcomm SM8150 MTP reference platform, but no actual
     products.

   - For the slightly older Qualcomm platforms, support for several
     interesting products is getting added: Three laptops based on
     Snapdragon 835/MSM8998 (Asus NovaGo, HP Envy X2 and Lenovo Miix
     630), one laptop based on Snapdragon 850/sdm850 (Lenovo Yoga C630)
     and several phones based on the older Snapdragon 410/MSM8916
     (Samsung A3 and A5, Longcheer L8150 aka Android One 2nd gen "seed"
     aka Wileyfox Swift).

   - Mediatek MT7629 is a new wireless network router chip, similar to
     the older MT7623. It gets added together with the reference board
     implementation.

   - Allwinner V3 is a repackaged version of the existing low-end V3s
     chip, and is used in the tiny Lichee Pi Zero plus, also added here.
     There is also a new TV set-top box based on Allwinner H6, the Tanix
     TX6, and the eMMC variant of the Olimex A64-Olinuxino development
     board.

   - NXP i.MX8M Nano is a new member of the ever-expanding i.MX SoC
     family, similar to the i.MX8M Mini. As usual, there is a large
     number of new boards for i.MX SoCs: Einfochips i.MX8QXP AI_ML,
     SolidRun Hummingboard Pulse baseboard and System-on-Module,
     Boundary Devices i.MX8MQ Nitrogen8M, and TechNexion
     PICO-PI-IMX8M-DEV for the 64-bit i.MX8 line. For 32-bit, we get the
     Kontron i.MX6UL N6310 SoM with two baseboards, the PHYTEC
     phyBOARD-Segin SoM with three baseboards, and the Zodiac Inflight
     Innovations i.MX7 RMU2 board.

   - In a different NXP product line, the Layerscape LS1046A "Freeway"
     reference board gets added.

   - Amlogic SM1 (S905X3) and G12B (S922X, A311D) are updated chips from
     their set-top-box line and smart speaker with newer CPU and GPU
     cores compared to their predecessors. Both are now also supported
     by the Khadas VIM3 development board series, and the dts files for
     that get reorganized a bit to better deal with all variants.
     Another board based on SM1 that gets added is the SEI Robotics
     SEI610.

   - There are a handful of new x86 and Power9 server boards using
     Aspeed BMC chips that are gaining support for running Linux on the
     BMC through the OpenBMC project: Facebook
     Minipack/Wedge100/Wedge40, Lenovo Hr855xg2, and Mihawk. Notably
     these are still new machines using SoCs based on the ARM9 and ARM11
     CPU cores, as support for the new Cortex-A7 based AST2600 is still
     ramping up.

   - There are three new end-user products using 32-bit Rockchips SoCs:
     Mecer Xtreme Mini S6 is an Android "mini PC" box based on the
     low-end RK3229 chip, while the two AOpen products Chromebox Mini
     (Fievel) and Chromebase Mini (Tiger) run ChromeOS and are meant for
     commercial settings(digital signage, PoS, ...).

   - One more single-board computer based on the popular 64-bit RK3399
     is added: the Leez RK3399 P710"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (467 commits)
  arm64: dts: qcom: Add Lenovo Yoga C630
  ARM: dts: aspeed-g5: Fixe gpio-ranges upper limit
  ARM; dts: aspeed: mihawk: File should not be executable
  ARM: dts: aspeed: swift: Change power supplies to version 2
  ARM: dts: aspeed: vesnin: Add secondary SPI flash chip
  ARM: dts: aspeed: vesnin: Add wdt2 with alt-boot option
  ARM: dts: aspeed-g4: Add all flash chips
  ARM: dts: exynos: Enable GPU/Mali T604 on Arndale board
  ARM: dts: exynos: Enable GPU/Mali T604 on Chromebook Snow
  ARM: dts: exynos: Add GPU/Mali T604 node to Exynos5250
  ARM: dts: exynos: Fix min/max buck4 for GPU on Arndale board
  ARM: dts: exynos: Mark LDO10 as always-on on Peach Pit/Pi Chromebooks
  ARM: dts: exynos: Remove not accurate secondary ADC compatible
  arm64: dts: rockchip: limit clock rate of MMC controllers for RK3328
  arm64: dts: meson-sm1-sei610: add stdout-path property back
  arm64: dts: meson-sm1-sei610: enable DVFS
  arm64: dts: khadas-vim3: add support for the SM1 based VIM3L
  dt-bindings: arm: amlogic: add Amlogic SM1 based Khadas VIM3L bindings
  arm64: dts: khadas-vim3: move common nodes into meson-khadas-vim3.dtsi
  arm64: dts: meson: g12a: add reset to tdm formatters
  ...
2019-09-16 15:56:22 -07:00
Linus Torvalds 399eb9b6cb ARM: SoC driver updates for v5.4
The branch contains driver changes that are tightly
 connected to SoC specific code. Aside from smaller
 cleanups and bug fixes, here is a list of the notable
 changes.
 
 New device drivers:
 
 - The Turris Mox router has a new "moxtet" bus driver
   for its on-board pluggable extension bus. The
   same platform also gains a firmware driver.
 
 - The Samsung Exynos family gains a new Chipid driver
   exporting using the soc device sysfs interface
 
 - A similar socinfo driver for Qualcomm Snapdragon
   chips.
 
 - A firmware driver for the NXP i.MX DSP IPC protocol
   using shared memory and a mailbox
 
 Other changes:
 
 - The i.MX reset controller driver now supports the
   NXP i.MX8MM chip
 
 - Amlogic SoC specific drivers gain support for
   the S905X3 and A311D chips
 
 - A rework of the TI Davinci framebuffer driver to
   allow important cleanups in the platform code
 
 - A couple of device drivers for removed ARM SoC
   platforms are removed. Most of the removals were
   picked up by other maintainers, this contains
   whatever was left.
 
 Signed-off-by: Arnd Bergmann <arnd@arndb.de>
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Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "This contains driver changes that are tightly connected to SoC
  specific code. Aside from smaller cleanups and bug fixes, here is a
  list of the notable changes.

  New device drivers:

   - The Turris Mox router has a new "moxtet" bus driver for its
     on-board pluggable extension bus. The same platform also gains a
     firmware driver.

   - The Samsung Exynos family gains a new Chipid driver exporting using
     the soc device sysfs interface

   - A similar socinfo driver for Qualcomm Snapdragon chips.

   - A firmware driver for the NXP i.MX DSP IPC protocol using shared
     memory and a mailbox

  Other changes:

   - The i.MX reset controller driver now supports the NXP i.MX8MM chip

   - Amlogic SoC specific drivers gain support for the S905X3 and A311D
     chips

   - A rework of the TI Davinci framebuffer driver to allow important
     cleanups in the platform code

   - A couple of device drivers for removed ARM SoC platforms are
     removed. Most of the removals were picked up by other maintainers,
     this contains whatever was left"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (123 commits)
  bus: uniphier-system-bus: use devm_platform_ioremap_resource()
  soc: ti: ti_sci_pm_domains: Add support for exclusive and shared access
  dt-bindings: ti_sci_pm_domains: Add support for exclusive and shared access
  firmware: ti_sci: Allow for device shared and exclusive requests
  bus: imx-weim: remove incorrect __init annotations
  fbdev: remove w90x900/nuc900 platform drivers
  spi: remove w90x900 driver
  net: remove w90p910-ether driver
  net: remove ks8695 driver
  firmware: turris-mox-rwtm: Add sysfs documentation
  firmware: Add Turris Mox rWTM firmware driver
  dt-bindings: firmware: Document cznic,turris-mox-rwtm binding
  bus: moxtet: fix unsigned comparison to less than zero
  bus: moxtet: remove set but not used variable 'dummy'
  ARM: scoop: Use the right include
  dt-bindings: power: add Amlogic Everything-Else power domains bindings
  soc: amlogic: Add support for Everything-Else power domains controller
  fbdev: da8xx: use resource management for dma
  fbdev: da8xx-fb: drop a redundant if
  fbdev: da8xx-fb: use devm_platform_ioremap_resource()
  ...
2019-09-16 15:52:38 -07:00
Eugen Hristev 69a6bcde7f clk: at91: select parent if main oscillator or bypass is enabled
Selecting the right parent for the main clock is done using only
main oscillator enabled bit.
In case we have this oscillator bypassed by an external signal (no driving
on the XOUT line), we still use external clock, but with BYPASS bit set.
So, in this case we must select the same parent as before.
Create a macro that will select the right parent considering both bits from
the MOR register.
Use this macro when looking for the right parent.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-16 13:15:10 -07:00
Eugen Hristev 263eaf8f17 clk: at91: fix update bit maps on CFG_MOR write
The regmap update bits call was not selecting the proper mask, considering
the bits which was updating.
Update the mask from call to also include OSCBYPASS.
Removed MOSCEN which was not updated.

Fixes: 1bdf02326b ("clk: at91: make use of syscon/regmap internally")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-16 13:15:01 -07:00
Arnd Bergmann 375a7baddb Merge branch 'aspeed/dt-3' into arm/late
* aspeed/dt-3:
  ARM: dts: aspeed: Add AST2600 pinmux nodes
  ARM: dts: aspeed: Add AST2600 and EVB
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate
2019-09-12 12:06:07 +02:00
mtk01761 710774e048 clk: mediatek: Add MT6779 clock support
Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.

Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 09:37:30 -07:00
Jorge Ramirez-Ortiz 3bcff3e45b clk: qcom: fix QCS404 TuringCC regmap
The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).

Fixes: 892df0191b ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 09:05:22 -07:00
Vinod Koul 2243fd4186 clk: qcom: clk-rpmh: Add support for SM8150
Add support for rpmh clocks found in SM8150

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:40:10 -07:00
Vinod Koul a64a9e5172 clk: qcom: clk-rpmh: Convert to parent data scheme
Convert the rpmh clock driver to use the new parent data scheme by
specifying the parent data for board clock.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:40:10 -07:00
Taniya Das 3f905469c8 clk: qcom: gcc: Use floor ops for SDCC clocks
Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:39:12 -07:00
Vinod Koul 593020811c clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.

[1]: https://lore.kernel.org/linux-arm-msm/20190830195142.103564-1-swboyd@chromium.org/

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:38:22 -07:00
Stephen Boyd 5e4b7e82d4 clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.

Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:38:20 -07:00
Joel Stanley d3d04f6c33 clk: Add support for AST2600 SoC
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 15:22:29 -07:00
Joel Stanley c1c4942eeb clk: aspeed: Move structures to header
They will be reused by the ast2600 driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 15:17:02 -07:00
Fuqian Huang 81b94f1477 clk/ti: Use kmemdup rather than duplicating its implementation
kmemdup is introduced to duplicate a region of memory in a neat way.
Rather than kmalloc/kzalloc + memcpy, which the programmer needs to
write the size twice (sometimes lead to mistakes), kmemdup improves
readability, leads to smaller code and also reduce the chances of mistakes.
Suggestion to use kmemdup rather than using kmalloc/kzalloc + memcpy.

Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com>
Link: https://lkml.kernel.org/r/20190703162700.32091-1-huangfq.daxian@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 14:20:15 -07:00
Phil Reid d69d0b4384 clk: clk-cdce925: Add regulator support
The cdce925 power supplies could be controllable on some platforms.
Enable them before communicating with the cdce925.

Signed-off-by: Phil Reid <preid@electromag.com.au>
Link: https://lkml.kernel.org/r/1561691950-42154-3-git-send-email-preid@electromag.com.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:31:16 -07:00
kbuild test robot f9d67cd7bc clk: fix devm_platform_ioremap_resource.cocci warnings
drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs

 Use devm_platform_ioremap_resource helper which wraps
 platform_get_resource() and devm_ioremap_resource() together.

Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci

Fixes: 1c099779c1 ("clk: add BCM63XX gated clock controller driver")
CC: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1908081809160.2995@hadrien
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:30:22 -07:00
Nishka Dasgupta f5c009dbf1 clk: spear: Make structure i2s_sclk_masks constant
Static structure i2s_sclk_masks, having type aux_clk_masks, is only used
when it is passed as the sixth argument to function clk_register_aux().
However, clk_register_aux() is defined with its sixth argument as const.
Hence i2s_sclk_masks is not modified by clk_register_aux, which is also
the only usage of the former. Therefore make i2s_sclk_masks constant as
it is never modified.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190813085714.8079-1-nishkadg.linux@gmail.com
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:27:40 -07:00
YueHaibing 8863a5bf68 clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
drivers/clk/st/clkgen-pll.c:64:37: warning:
 st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:26:58 -07:00
YueHaibing e03a47deaf clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
drivers/clk/st/clkgen-fsyn.c:70:29: warning:
 st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:26:32 -07:00
Stephen Boyd 226fd70209 clk: Document of_parse_clkspec() some more
The return value of of_parse_clkspec() is peculiar. If the function is
called with a NULL argument for 'name' it will return -ENOENT, but if
it's called with a non-NULL argument for 'name' it will return -EINVAL.
This peculiarity is documented by commit 5c56dfe63b ("clk: Add comment
about __of_clk_get_by_name() error values").

Let's further document this function so that it's clear what the return
value is and how to use the arguments to parse clk specifiers.

Cc: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
2019-09-05 11:51:31 -07:00
Finley Xiao ac68dfd3c4 clk: rockchip: Add clock controller for the rk3308
Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-05 12:43:39 +02:00
Arnd Bergmann 49826a68b5 mvebu dt64 for 5.4 (part 2)
Add support for Turris Mox board (Armada 3720 SoC based)
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Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/late

mvebu dt64 for 5.4 (part 2)

Add support for Turris Mox board (Armada 3720 SoC based)

* tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits)
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
  arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
  arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
  arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
  arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
  arm64: dts: marvell: Add CP110 COMPHY clocks
  arm64: dts: marvell: armada-37xx: add mailbox node
  dt-bindings: gpio: Document GPIOs via Moxtet bus
  drivers: gpio: Add support for GPIOs over Moxtet bus
  bus: moxtet: Add sysfs and debugfs documentation
  dt-bindings: bus: Document moxtet bus binding
  bus: Add support for Moxtet bus
  reset: Add support for resets provided by SCMI
  firmware: arm_scmi: Add RESET protocol in SCMI v2.0
  dt-bindings: arm: Extend SCMI to support new reset protocol
  firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
  firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
  ...

Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:28:47 +02:00
Arnd Bergmann 1fb2e59cf5 SoC glue layer changes for SGX on omap variants for v5.4
For a while we've had omap4 sgx glue layer defined in dts and probed
 with ti-sysc driver. This allows idling the sgx module for PM, and
 removes the need for custom platform glue layer code for any further
 driver changes.
 
 We first drop the unused legacy platform data for omap4 sgx. Then for
 omap5, we need add the missing clkctrl clock data so we can configure
 sgx. And we configure sgx for omap34xx, omap36xx and am3517.
 
 For am335x, we still have a dependency for rstctrl reset driver changes,
 so that will be added later on.
 
 Note that this branch is based on earlier ti-sysc branch for omap36xx
 glue layer quirk handling.
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Merge tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

SoC glue layer changes for SGX on omap variants for v5.4

For a while we've had omap4 sgx glue layer defined in dts and probed
with ti-sysc driver. This allows idling the sgx module for PM, and
removes the need for custom platform glue layer code for any further
driver changes.

We first drop the unused legacy platform data for omap4 sgx. Then for
omap5, we need add the missing clkctrl clock data so we can configure
sgx. And we configure sgx for omap34xx, omap36xx and am3517.

For am335x, we still have a dependency for rstctrl reset driver changes,
so that will be added later on.

Note that this branch is based on earlier ti-sysc branch for omap36xx
glue layer quirk handling.

* tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx
  ARM: dts: Configure interconnect target module for omap3 sgx
  ARM: dts: Configure sgx for omap5
  clk: ti: add clkctrl data omap5 sgx
  ARM: OMAP2+: Drop legacy platform data for omap4 gpu

Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-4
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:22:02 +02:00
Greg Kroah-Hartman 4a79ce748f interconnect patches for 5.4
Here are the interconnect driver updates for the 5.4-rc1 merge window.
 
 - New feature is the path tagging support that helps with grouping and
 aggregating the bandwidth requests into separate buckets based on a tag.
 - The first user of the path tagging is the Qualcomm sdm845 driver that
 now implements support for wake/sleep sets. This allows consumer drivers
 to express their bandwidth needs for the different CPU power states.
 - New interconnect driver for the qcs404 platforms and a driver that
 communicates bandwidth requests with remote processor over shared memory.
 - Cleanups and fixes.
 
 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next

Georgi writes:

interconnect patches for 5.4

Here are the interconnect driver updates for the 5.4-rc1 merge window.

- New feature is the path tagging support that helps with grouping and
aggregating the bandwidth requests into separate buckets based on a tag.
- The first user of the path tagging is the Qualcomm sdm845 driver that
now implements support for wake/sleep sets. This allows consumer drivers
to express their bandwidth needs for the different CPU power states.
- New interconnect driver for the qcs404 platforms and a driver that
communicates bandwidth requests with remote processor over shared memory.
- Cleanups and fixes.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

* tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux:
  drivers: qcom: Add BCM vote macro to header
  interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404
  interconnect: qcom: Add QCS404 interconnect provider driver
  interconnect: qcom: Add interconnect RPM over SMD driver
  dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
  interconnect: qcom: Add tagging and wake/sleep support for sdm845
  interconnect: Add pre_aggregate() callback
  interconnect: Add support for path tags
2019-09-03 21:47:37 +02:00
Arnd Bergmann 89e4acf7a3 i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
    device tree support.
  - Add DSP device tree support for i.MX8QXP SoC.
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Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree update with new clocks:
 - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
   device tree support.
 - Add DSP device tree support for i.MX8QXP SoC.

* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8qxp: Add DSP DT node
  arm64: dts: imx8mn: Add cpu-freq support
  arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
  arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
  arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
  arm64: dts: imx8mn: Add gpio-ranges property
  arm64: dts: freescale: Add i.MX8MN dtsi support
  clk: imx8: Add DSP related clocks
  clk: imx: Add support for i.MX8MN clock driver
  clk: imx: Add API for clk unregister when driver probe fail
  clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
  dt-bindings: imx: Add clock binding doc for i.MX8MN

Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 16:06:08 +02:00
Arnd Bergmann 1c92b32649 arm64: dts: Amlogic updates for v5.4
Highlights
 - new SoCs (G12B family): S922X, A311D
 - new SoCs (SM1 family): S905X3
 - new board: SEI Robotics SEI610 (SM1/S905X3)
 - new board: Khadas VIM3 (G12B/A311D)
 - DVFS/CPUfreq support on G12[AB] family
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4

Highlights
- new SoCs (G12B family): S922X, A311D
- new SoCs (SM1 family): S905X3
- new board: SEI Robotics SEI610 (SM1/S905X3)
- new board: Khadas VIM3 (G12B/A311D)
- DVFS/CPUfreq support on G12[AB] family

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits)
  arm64: dts: add support for SM1 based SEI Robotics SEI610
  dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings
  dt-bindings: arm: amlogic: add SM1 bindings
  arm64: dts: meson-g12b-odroid-n2: enable DVFS
  arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
  dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
  arm64: dts: amlogic: g12 CPU timers stop in suspend
  arm64: dts: meson-g12b: support a311d and s922x cpu operating points
  dt-bindings: arm: amlogic: add support for the Khadas VIM3
  dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC
  dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
  arm64: dts: meson: add video decoder entries
  arm64: dts: meson-gx: add video decoder entry
  dt-bindings: media: amlogic,vdec: add default compatible
  arm64: dts: meson: add ethernet fifo sizes
  arm64: dts: meson-g12b: add cpus OPP tables
  arm64: dts: meson-g12a: enable DVFS on G12A boards
  arm64: dts: meson-g12a: add cpus OPP table
  arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux
  arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
  ...

Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:14:54 +02:00
Tony Lindgren fd56837494 clk: ti: add clkctrl data omap5 sgx
Looks like we have sgx clock missing currently so let's add it.

Cc: Adam Ford <aford173@gmail.com>
Cc: Filip Matijević <filip.matijevic.pz@gmail.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: moaz korena <moaz@korena.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Cc: Philipp Rossak <embed3d@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-08-26 08:47:07 -07:00
Neil Armstrong da3ceae4ec clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.

But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.

They are set read-only because the early boot stages sets them to select
the CPU0 input clock.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:04:54 +02:00
Neil Armstrong 2edccd319f clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.

Leave this as read-only since it's set up by the early boot stages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:04:42 +02:00
Neil Armstrong 3dd02b7334 clk: meson: g12a: add support for SM1 GP1 PLL
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.

This also adds a dedicated set of clock and compatible for SM1.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:03:38 +02:00
Peng Fan 760e548e7f clk: imx: imx8mn: fix audio pll setting
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 21:04:27 +02:00
Geert Uytterhoeven f787216f33 clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSSR Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

Note that this only affects RZ/A2 SoCs.  On R-Car Gen2 and Gen3 SoCs,
the R-Car SYSC driver handles Clock Domain creation, and offloads only
device attachment/detachment to the CPG/MSSR driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:57 +02:00
Geert Uytterhoeven 7b8f7a76f2 clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
The RZ/N1 Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:52 +02:00
Geert Uytterhoeven a459a184c9 clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSTP Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

This also gets rid of a boot warning when the Clock Domain contains an
IRQ-safe device, e.g. on RZ/A1:

    sh_mtu2 fcff0000.timer: PM domain cpg_clocks will not be powered off

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:49 +02:00
Jernej Skrabec 65818ad081 clk: sunxi-ng: h6: Allow I2S to change parent rate
I2S doesn't work if parent rate couldn't be change. Difference between
wanted and actual rate is too big.

Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-08-21 17:20:31 +08:00
Jerome Brunet 7cfefab656 clk: meson: axg-audio: add g12a reset support
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.

the axg SoC family does not appear to provide this feature.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-20 11:51:36 +02:00
Jordan Crouse 6311b6521b drivers: qcom: Add BCM vote macro to header
The macro to generate a Bus Controller Manager (BCM) TCS command is used
by the interconnect driver but might also be interesting to other
drivers that need to construct TCS commands for sub processors so move
it out of the sdm845 specific file and into the header.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2019-08-20 10:09:56 +03:00
Anson Huang 613cc5cd74 clk: imx8mn: Add necessary frequency support for ARM PLL table
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 15:38:55 +02:00
Anson Huang 313ccbad73 clk: imx8mn: Add missing rate_count assignment for each PLL structure
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 15:36:58 +02:00
Peng Fan f8cade8310 clk: imx8mn: fix int pll clk gate
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:57:47 +02:00
Leonard Crestez be378b6007 clk: imx8mn: Add GIC clock
This is enabled by default but if it's not explicitly defined and marked
as critical then its parent might get turned off.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:40 +02:00
Leonard Crestez b3d08a4b1e clk: imx8mn: Fix incorrect parents
* Replace to audio_pll2_clk with audio_pll2_out
* Replace sys3_pll2_out with sys_pll3_out
* Replace sys1_pll_40m with sys_pll1_40m
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m

Fixes: 96d6392b54 ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:36 +02:00
Leonard Crestez 3125c9eb01 clk: imx8mm: Fix incorrect parents
* There is no video_pll2 on imx8mm, replace with dummy
* Replace reference to sys_pll3_clk with sys_pll3_out
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:30 +02:00
Leonard Crestez 78f5666c18 clk: imx8mq: Fix sys3 pll references
The "sys3_pll2_out" CLK was removed in refactoring so all references
need to be updated to "sys3_pll_out"

Fixes: e9dda4af68 ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:18 +02:00
Rishi Gupta ef13e55c27 clk: Remove extraneous 'for' word in comments
An extra 'for' word is grammatically incorrect in the comment
'verifying ops for multi-parent clks'. This commit removes
this extra for word.

Signed-off-by: Rishi Gupta <gupt21@gmail.com>
Link: https://lkml.kernel.org/r/1566023759-7880-1-git-send-email-gupt21@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-17 18:13:51 -07:00
Stephen Boyd b0740d71cb clk: composite: Drop unused clk.h include
This include isn't used. Drop it.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815042500.9519-1-sboyd@kernel.org
2019-08-16 10:37:01 -07:00
Martin Blumenstingl 24876f09a7 clk: Fix potential NULL dereference in clk_fetch_parent_index()
Don't compare the parent clock name with a NULL name in the
clk_parent_map. This prevents a kernel crash when passing NULL
core->parents[i].name to strcmp().

An example which triggered this is a mux clock with four parents when
each of them is referenced in the clock driver using
clk_parent_data.fw_name and then calling clk_set_parent(clk, 3rd_parent)
on this mux.
In this case the first parent is also the HW default so
core->parents[i].hw is populated when the clock is registered. Calling
clk_set_parent(clk, 3rd_parent) will then go through all parents and
skip the first parent because it's hw pointer doesn't match. For the
second parent no hw pointer is cached yet and clk_core_get(core, 1)
returns a non-matching pointer (which is correct because we are comparing
the second with the third parent). Comparing the result of
clk_core_get(core, 2) with the requested parent gives a match. However
we don't reach this point because right after the clk_core_get(core, 1)
mismatch the old code tried to !strcmp(parent->name, NULL) (where the
second argument is actually core->parents[i].name, but that was never
populated by the clock driver).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20190815223155.21384-1-martin.blumenstingl@googlemail.com
Fixes: fc0c209c14 ("clk: Allow parents to be specified without string names")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16 10:30:21 -07:00
Stephen Boyd 4f8c6aba37 clk: Fix falling back to legacy parent string matching
Calls to clk_core_get() will return ERR_PTR(-EINVAL) if we've started
migrating a clk driver to use the DT based style of specifying parents
but we haven't made any DT updates yet. This happens when we pass a
non-NULL value as the 'name' argument of of_parse_clkspec(). That
function returns -EINVAL in such a situation, instead of -ENOENT like we
expected. The return value comes back up to clk_core_fill_parent_index()
which proceeds to skip calling clk_core_lookup() because the error
pointer isn't equal to -ENOENT, it's -EINVAL.

Furthermore, we blindly overwrite the error pointer returned by
clk_core_get() with NULL when there isn't a legacy .name member
specified in the parent map. This isn't too bad right now because we
don't really care to differentiate NULL from an error, but in the future
we should only try to do a legacy lookup if we know we might find
something. This way DT lookups that fail don't try to lookup based on
strings when there isn't any string to match, hiding the error from DT
parsing.

Fix both these problems so that clk provider drivers can use the new
style of parent mapping without having to also update their DT at the
same time. This patch is based on an earlier patch from Taniya Das which
checked for -EINVAL in addition to -ENOENT return values from
clk_core_get().

Fixes: 601b6e9330 ("clk: Allow parents to be specified via clkspec index")
Cc: Taniya Das <tdas@codeaurora.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Reported-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190813214147.34394-1-sboyd@kernel.org
Tested-by: Taniya Das <tdas@codeaurora.org>
2019-08-16 10:28:28 -07:00
Stephen Boyd 0214f33c4e clk: Overwrite clk_hw::init with NULL during clk_register()
We don't want clk provider drivers to use the init structure after clk
registration time, but we leave a dangling reference to it by means of
clk_hw::init. Let's overwrite the member with NULL during clk_register()
so that this can't be used anymore after registration time.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-10-sboyd@kernel.org
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-08-16 10:27:29 -07:00
Stephen Boyd a7b85ad25a clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
The implementation of clk_hw_get_name() relies on the clk_core
associated with the clk_hw pointer existing. If of_clk_hw_register()
fails, there isn't a clk_core created yet, so calling clk_hw_get_name()
here fails. Extract the name first so we can print it later.

Fixes: 1d80c14248 ("clk: sunxi-ng: Add common infrastructure")
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16 10:27:29 -07:00
Stephen Boyd e0e04fc866 clk: ti: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815221249.53235-1-sboyd@kernel.org
2019-08-16 10:22:46 -07:00