Commit Graph

6328 Commits

Author SHA1 Message Date
Eugen Hristev 69a6bcde7f clk: at91: select parent if main oscillator or bypass is enabled
Selecting the right parent for the main clock is done using only
main oscillator enabled bit.
In case we have this oscillator bypassed by an external signal (no driving
on the XOUT line), we still use external clock, but with BYPASS bit set.
So, in this case we must select the same parent as before.
Create a macro that will select the right parent considering both bits from
the MOR register.
Use this macro when looking for the right parent.

Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-2-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-16 13:15:10 -07:00
Eugen Hristev 263eaf8f17 clk: at91: fix update bit maps on CFG_MOR write
The regmap update bits call was not selecting the proper mask, considering
the bits which was updating.
Update the mask from call to also include OSCBYPASS.
Removed MOSCEN which was not updated.

Fixes: 1bdf02326b ("clk: at91: make use of syscon/regmap internally")
Signed-off-by: Eugen Hristev <eugen.hristev@microchip.com>
Link: https://lkml.kernel.org/r/1568042692-11784-1-git-send-email-eugen.hristev@microchip.com
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Reviewed-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-16 13:15:01 -07:00
Arnd Bergmann 375a7baddb Merge branch 'aspeed/dt-3' into arm/late
* aspeed/dt-3:
  ARM: dts: aspeed: Add AST2600 pinmux nodes
  ARM: dts: aspeed: Add AST2600 and EVB
  clk: Add support for AST2600 SoC
  clk: aspeed: Move structures to header
  clk: aspeed: Add SDIO gate
2019-09-12 12:06:07 +02:00
mtk01761 710774e048 clk: mediatek: Add MT6779 clock support
Add MT6779 clock support, include topckgen, apmixedsys,
infracfg, and subsystem clocks.

Signed-off-by: mtk01761 <wendell.lin@mediatek.com>
Link: https://lkml.kernel.org/r/1566206502-4347-11-git-send-email-mars.cheng@mediatek.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 09:37:30 -07:00
Jorge Ramirez-Ortiz 3bcff3e45b clk: qcom: fix QCS404 TuringCC regmap
The max register is 0x23004 as per the manual (the current
max_register that this commit is fixing is actually out of bounds).

Fixes: 892df0191b ("clk: qcom: Add QCS404 TuringCC")
Signed-off-by: Jorge Ramirez-Ortiz <jorge.ramirez-ortiz@linaro.org>
Link: https://lkml.kernel.org/r/20190909085430.8700-1-jorge.ramirez-ortiz@linaro.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 09:05:22 -07:00
Vinod Koul 2243fd4186 clk: qcom: clk-rpmh: Add support for SM8150
Add support for rpmh clocks found in SM8150

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-5-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:40:10 -07:00
Vinod Koul a64a9e5172 clk: qcom: clk-rpmh: Convert to parent data scheme
Convert the rpmh clock driver to use the new parent data scheme by
specifying the parent data for board clock.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190826173120.2971-3-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:40:10 -07:00
Taniya Das 3f905469c8 clk: qcom: gcc: Use floor ops for SDCC clocks
Update global clock controller SDCC2/4 clocks to use the floor rcg ops,
so as to use the rounded down clock rates for these clocks.

Signed-off-by: Taniya Das <tdas@codeaurora.org>
Link: https://lkml.kernel.org/r/20190909074410.18977-1-tdas@codeaurora.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:39:12 -07:00
Vinod Koul 593020811c clk: qcom: gcc-qcs404: Use floor ops for sdcc clks
Update the gcc qcs404 clock driver to use floor ops for sdcc clocks. As
disuccsed in [1] it is good idea to use floor ops for sdcc clocks as we
dont want the clock rates to do round up.

[1]: https://lore.kernel.org/linux-arm-msm/20190830195142.103564-1-swboyd@chromium.org/

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190906045659.20621-1-vkoul@kernel.org
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:38:22 -07:00
Stephen Boyd 5e4b7e82d4 clk: qcom: gcc-sdm845: Use floor ops for sdcc clks
Some MMC cards fail to enumerate properly when inserted into an MMC slot
on sdm845 devices. This is because the clk ops for qcom clks round the
frequency up to the nearest rate instead of down to the nearest rate.
For example, the MMC driver requests a frequency of 52MHz from
clk_set_rate() but the qcom implementation for these clks rounds 52MHz
up to the next supported frequency of 100MHz. The MMC driver could be
modified to request clk rate ranges but for now we can fix this in the
clk driver by changing the rounding policy for this clk to be round down
instead of round up.

Fixes: 06391eddb6 ("clk: qcom: Add Global Clock controller (GCC) driver for SDM845")
Reported-by: Douglas Anderson <dianders@chromium.org>
Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <swboyd@chromium.org>
Link: https://lkml.kernel.org/r/20190830195142.103564-1-swboyd@chromium.org
Reviewed-by: Douglas Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-09 04:38:20 -07:00
Joel Stanley d3d04f6c33 clk: Add support for AST2600 SoC
The ast2600 is a new BMC SoC from ASPEED. It contains many more clocks
than the previous iterations, so support is broken out into it's own
driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-3-joel@jms.id.au
[sboyd@kernel.org: Mark arrays const]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 15:22:29 -07:00
Joel Stanley c1c4942eeb clk: aspeed: Move structures to header
They will be reused by the ast2600 driver.

Signed-off-by: Joel Stanley <joel@jms.id.au>
Link: https://lkml.kernel.org/r/20190825141848.17346-2-joel@jms.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 15:17:02 -07:00
Fuqian Huang 81b94f1477 clk/ti: Use kmemdup rather than duplicating its implementation
kmemdup is introduced to duplicate a region of memory in a neat way.
Rather than kmalloc/kzalloc + memcpy, which the programmer needs to
write the size twice (sometimes lead to mistakes), kmemdup improves
readability, leads to smaller code and also reduce the chances of mistakes.
Suggestion to use kmemdup rather than using kmalloc/kzalloc + memcpy.

Signed-off-by: Fuqian Huang <huangfq.daxian@gmail.com>
Link: https://lkml.kernel.org/r/20190703162700.32091-1-huangfq.daxian@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 14:20:15 -07:00
Phil Reid d69d0b4384 clk: clk-cdce925: Add regulator support
The cdce925 power supplies could be controllable on some platforms.
Enable them before communicating with the cdce925.

Signed-off-by: Phil Reid <preid@electromag.com.au>
Link: https://lkml.kernel.org/r/1561691950-42154-3-git-send-email-preid@electromag.com.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:31:16 -07:00
kbuild test robot f9d67cd7bc clk: fix devm_platform_ioremap_resource.cocci warnings
drivers/clk/bcm/clk-bcm63xx-gate.c:174:1-9: WARNING: Use devm_platform_ioremap_resource for hw -> regs

 Use devm_platform_ioremap_resource helper which wraps
 platform_get_resource() and devm_ioremap_resource() together.

Generated by: scripts/coccinelle/api/devm_platform_ioremap_resource.cocci

Fixes: 1c099779c1 ("clk: add BCM63XX gated clock controller driver")
CC: Jonas Gorski <jonas.gorski@gmail.com>
Signed-off-by: kbuild test robot <lkp@intel.com>
Signed-off-by: Julia Lawall <julia.lawall@lip6.fr>
Link: https://lkml.kernel.org/r/alpine.DEB.2.21.1908081809160.2995@hadrien
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:30:22 -07:00
Nishka Dasgupta f5c009dbf1 clk: spear: Make structure i2s_sclk_masks constant
Static structure i2s_sclk_masks, having type aux_clk_masks, is only used
when it is passed as the sixth argument to function clk_register_aux().
However, clk_register_aux() is defined with its sixth argument as const.
Hence i2s_sclk_masks is not modified by clk_register_aux, which is also
the only usage of the former. Therefore make i2s_sclk_masks constant as
it is never modified.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190813085714.8079-1-nishkadg.linux@gmail.com
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:27:40 -07:00
YueHaibing 8863a5bf68 clk: st: clkgen-pll: remove unused variable 'st_pll3200c32_407_a0'
drivers/clk/st/clkgen-pll.c:64:37: warning:
 st_pll3200c32_407_a0 defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135523.73520-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:26:58 -07:00
YueHaibing e03a47deaf clk: st: clkgen-fsyn: remove unused variable 'st_quadfs_fs660c32_ops'
drivers/clk/st/clkgen-fsyn.c:70:29: warning:
 st_quadfs_fs660c32_ops defined but not used [-Wunused-const-variable=]

It is never used, so can be removed.

Reported-by: Hulk Robot <hulkci@huawei.com>
Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Link: https://lkml.kernel.org/r/20190816135341.52248-1-yuehaibing@huawei.com
Acked-by: Gabriel Fernandez <gabriel.fernandez@st.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-09-06 10:26:32 -07:00
Stephen Boyd 226fd70209 clk: Document of_parse_clkspec() some more
The return value of of_parse_clkspec() is peculiar. If the function is
called with a NULL argument for 'name' it will return -ENOENT, but if
it's called with a non-NULL argument for 'name' it will return -EINVAL.
This peculiarity is documented by commit 5c56dfe63b ("clk: Add comment
about __of_clk_get_by_name() error values").

Let's further document this function so that it's clear what the return
value is and how to use the arguments to parse clk specifiers.

Cc: Phil Edworthy <phil.edworthy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190826212042.48642-1-sboyd@kernel.org
Reviewed-by: Phil Edworthy <phil.edworthy@renesas.com>
2019-09-05 11:51:31 -07:00
Finley Xiao ac68dfd3c4 clk: rockchip: Add clock controller for the rk3308
Add the clock tree definition for the new RK3308 SoC.

Signed-off-by: Finley Xiao <finley.xiao@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-09-05 12:43:39 +02:00
Arnd Bergmann 49826a68b5 mvebu dt64 for 5.4 (part 2)
Add support for Turris Mox board (Armada 3720 SoC based)
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Merge tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu into arm/late

mvebu dt64 for 5.4 (part 2)

Add support for Turris Mox board (Armada 3720 SoC based)

* tag 'mvebu-dt64-5.4-2' of git://git.infradead.org/linux-mvebu: (53 commits)
  arm64: dts: marvell: add DTS for Turris Mox
  dt-bindings: marvell: document Turris Mox compatible
  arm64: dts: marvell: armada-37xx: add SPI CS1 pinctrl
  arm64: dts: marvell: Add cpu clock node on Armada 7K/8K
  arm64: dts: marvell: Convert 7k/8k usb-phy properties to phy-supply
  arm64: dts: marvell: Add 7k/8k PHYs in PCIe nodes
  arm64: dts: marvell: Add 7k/8k PHYs in USB3 nodes
  arm64: dts: marvell: Add 7k/8k per-port PHYs in SATA nodes
  arm64: dts: marvell: Add CP110 COMPHY clocks
  arm64: dts: marvell: armada-37xx: add mailbox node
  dt-bindings: gpio: Document GPIOs via Moxtet bus
  drivers: gpio: Add support for GPIOs over Moxtet bus
  bus: moxtet: Add sysfs and debugfs documentation
  dt-bindings: bus: Document moxtet bus binding
  bus: Add support for Moxtet bus
  reset: Add support for resets provided by SCMI
  firmware: arm_scmi: Add RESET protocol in SCMI v2.0
  dt-bindings: arm: Extend SCMI to support new reset protocol
  firmware: arm_scmi: Make use SCMI v2.0 fastchannel for performance protocol
  firmware: arm_scmi: Add discovery of SCMI v2.0 performance fastchannels
  ...

Link: https://lore.kernel.org/r/87h85two0r.fsf@FE-laptop
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:28:47 +02:00
Arnd Bergmann 1fb2e59cf5 SoC glue layer changes for SGX on omap variants for v5.4
For a while we've had omap4 sgx glue layer defined in dts and probed
 with ti-sysc driver. This allows idling the sgx module for PM, and
 removes the need for custom platform glue layer code for any further
 driver changes.
 
 We first drop the unused legacy platform data for omap4 sgx. Then for
 omap5, we need add the missing clkctrl clock data so we can configure
 sgx. And we configure sgx for omap34xx, omap36xx and am3517.
 
 For am335x, we still have a dependency for rstctrl reset driver changes,
 so that will be added later on.
 
 Note that this branch is based on earlier ti-sysc branch for omap36xx
 glue layer quirk handling.
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Merge tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into arm/late

SoC glue layer changes for SGX on omap variants for v5.4

For a while we've had omap4 sgx glue layer defined in dts and probed
with ti-sysc driver. This allows idling the sgx module for PM, and
removes the need for custom platform glue layer code for any further
driver changes.

We first drop the unused legacy platform data for omap4 sgx. Then for
omap5, we need add the missing clkctrl clock data so we can configure
sgx. And we configure sgx for omap34xx, omap36xx and am3517.

For am335x, we still have a dependency for rstctrl reset driver changes,
so that will be added later on.

Note that this branch is based on earlier ti-sysc branch for omap36xx
glue layer quirk handling.

* tag 'omap-for-v5.4/ti-sysc-sgx-signed' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
  ARM: dts: ARM: dts: Configure interconnect target module for am3517sgx
  ARM: dts: Configure interconnect target module for omap3 sgx
  ARM: dts: Configure sgx for omap5
  clk: ti: add clkctrl data omap5 sgx
  ARM: OMAP2+: Drop legacy platform data for omap4 gpu

Link: https://lore.kernel.org/r/pull-1567016893-318461@atomide.com-4
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-04 17:22:02 +02:00
Greg Kroah-Hartman 4a79ce748f interconnect patches for 5.4
Here are the interconnect driver updates for the 5.4-rc1 merge window.
 
 - New feature is the path tagging support that helps with grouping and
 aggregating the bandwidth requests into separate buckets based on a tag.
 - The first user of the path tagging is the Qualcomm sdm845 driver that
 now implements support for wake/sleep sets. This allows consumer drivers
 to express their bandwidth needs for the different CPU power states.
 - New interconnect driver for the qcs404 platforms and a driver that
 communicates bandwidth requests with remote processor over shared memory.
 - Cleanups and fixes.
 
 Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
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Merge tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux into char-misc-next

Georgi writes:

interconnect patches for 5.4

Here are the interconnect driver updates for the 5.4-rc1 merge window.

- New feature is the path tagging support that helps with grouping and
aggregating the bandwidth requests into separate buckets based on a tag.
- The first user of the path tagging is the Qualcomm sdm845 driver that
now implements support for wake/sleep sets. This allows consumer drivers
to express their bandwidth needs for the different CPU power states.
- New interconnect driver for the qcs404 platforms and a driver that
communicates bandwidth requests with remote processor over shared memory.
- Cleanups and fixes.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>

* tag 'icc-5.4-rc1' of https://git.linaro.org/people/georgi.djakov/linux:
  drivers: qcom: Add BCM vote macro to header
  interconnect: qcom: remove COMPILE_TEST from CONFIG_INTERCONNECT_QCOM_QCS404
  interconnect: qcom: Add QCS404 interconnect provider driver
  interconnect: qcom: Add interconnect RPM over SMD driver
  dt-bindings: interconnect: Add Qualcomm QCS404 DT bindings
  interconnect: qcom: Add tagging and wake/sleep support for sdm845
  interconnect: Add pre_aggregate() callback
  interconnect: Add support for path tags
2019-09-03 21:47:37 +02:00
Arnd Bergmann 89e4acf7a3 i.MX device tree update with new clocks:
- A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
    device tree support.
  - Add DSP device tree support for i.MX8QXP SoC.
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Merge tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into arm/dt

i.MX device tree update with new clocks:
 - A series from Anson Huang to add i.MX8MN SoC and DDR4 EVK board
   device tree support.
 - Add DSP device tree support for i.MX8QXP SoC.

* tag 'imx-dt-clkdep-5.4' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: imx8qxp: Add DSP DT node
  arm64: dts: imx8mn: Add cpu-freq support
  arm64: dts: imx8mn-ddr4-evk: Add rohm,bd71847 PMIC support
  arm64: dts: imx8mn-ddr4-evk: Add i2c1 support
  arm64: dts: freescale: Add i.MX8MN DDR4 EVK board support
  arm64: dts: imx8mn: Add gpio-ranges property
  arm64: dts: freescale: Add i.MX8MN dtsi support
  clk: imx8: Add DSP related clocks
  clk: imx: Add support for i.MX8MN clock driver
  clk: imx: Add API for clk unregister when driver probe fail
  clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
  dt-bindings: imx: Add clock binding doc for i.MX8MN

Link: https://lore.kernel.org/r/20190825153237.28829-4-shawnguo@kernel.org
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 16:06:08 +02:00
Arnd Bergmann 1c92b32649 arm64: dts: Amlogic updates for v5.4
Highlights
 - new SoCs (G12B family): S922X, A311D
 - new SoCs (SM1 family): S905X3
 - new board: SEI Robotics SEI610 (SM1/S905X3)
 - new board: Khadas VIM3 (G12B/A311D)
 - DVFS/CPUfreq support on G12[AB] family
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Merge tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic into arm/dt

arm64: dts: Amlogic updates for v5.4

Highlights
- new SoCs (G12B family): S922X, A311D
- new SoCs (SM1 family): S905X3
- new board: SEI Robotics SEI610 (SM1/S905X3)
- new board: Khadas VIM3 (G12B/A311D)
- DVFS/CPUfreq support on G12[AB] family

* tag 'amlogic-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/khilman/linux-amlogic: (40 commits)
  arm64: dts: add support for SM1 based SEI Robotics SEI610
  dt-bindings: arm: amlogic: add SEI Robotics SEI610 bindings
  dt-bindings: arm: amlogic: add SM1 bindings
  arm64: dts: meson-g12b-odroid-n2: enable DVFS
  arm64: dts: meson-g12b-khadas-vim3: add initial device-tree
  dt-bindings: arm: amlogic: fix x96-max/sei510 section in amlogic.yaml
  arm64: dts: amlogic: g12 CPU timers stop in suspend
  arm64: dts: meson-g12b: support a311d and s922x cpu operating points
  dt-bindings: arm: amlogic: add support for the Khadas VIM3
  dt-bindings: arm: amlogic: add bindings for the Amlogic G12B based A311D SoC
  dt-bindings: arm: amlogic: add bindings for G12B based S922X SoC
  arm64: dts: meson: add video decoder entries
  arm64: dts: meson-gx: add video decoder entry
  dt-bindings: media: amlogic,vdec: add default compatible
  arm64: dts: meson: add ethernet fifo sizes
  arm64: dts: meson-g12b: add cpus OPP tables
  arm64: dts: meson-g12a: enable DVFS on G12A boards
  arm64: dts: meson-g12a: add cpus OPP table
  arm64: dts: meson-g12-common: add pwm_a on GPIOE_2 pinmux
  arm64: dts: move common G12A & G12B modes to meson-g12-common.dtsi
  ...

Link: https://lore.kernel.org/r/7hr25fbi4v.fsf@baylibre.com
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2019-09-03 15:14:54 +02:00
Tony Lindgren fd56837494 clk: ti: add clkctrl data omap5 sgx
Looks like we have sgx clock missing currently so let's add it.

Cc: Adam Ford <aford173@gmail.com>
Cc: Filip Matijević <filip.matijevic.pz@gmail.com>
Cc: "H. Nikolaus Schaller" <hns@goldelico.com>
Cc: Ivaylo Dimitrov <ivo.g.dimitrov.75@gmail.com>
Cc: moaz korena <moaz@korena.xyz>
Cc: Merlijn Wajer <merlijn@wizzup.org>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Paweł Chmiel <pawel.mikolaj.chmiel@gmail.com>
Cc: Philipp Rossak <embed3d@gmail.com>
Cc: Stephen Boyd <sboyd@kernel.org>
Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tomi Valkeinen <tomi.valkeinen@ti.com>
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
2019-08-26 08:47:07 -07:00
Neil Armstrong da3ceae4ec clk: meson: g12a: add support for SM1 CPU 1, 2 & 3 clocks
The Amlogic SM1 can set a dedicated clock frequency for each CPU core by
having a dedicate tree for each core similar to the CPU0 tree.
Like the DSU tree, a supplementaty mux has been added to use the CPU0
frequency instead.

But since the cluster only has a single power rail and shares a single PLL,
it's not worth adding 3 unsused clock tree, so we add only the mux to
select the CPU0 clock frequency for each CPU1, CPU2 and CPU3 cores.

They are set read-only because the early boot stages sets them to select
the CPU0 input clock.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:04:54 +02:00
Neil Armstrong 2edccd319f clk: meson: g12a: add support for SM1 DynamIQ Shared Unit clock
The Amlogic SM1 DynamIQ Shared Unit has a dedicated clock tree similar to
the CPU clock tree with a supplementaty mux to select the CPU0 clock
instead.

Leave this as read-only since it's set up by the early boot stages.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:04:42 +02:00
Neil Armstrong 3dd02b7334 clk: meson: g12a: add support for SM1 GP1 PLL
Add the new GP1 PLL for the Amlogic SM1 SoC, used to feed the new
DynamIQ Shared Unit of the ARM Cores Complex.

This also adds a dedicated set of clock and compatible for SM1.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-26 11:03:38 +02:00
Peng Fan 760e548e7f clk: imx: imx8mn: fix audio pll setting
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Shengjiu Wang <shengjiu.wang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-24 21:04:27 +02:00
Geert Uytterhoeven f787216f33 clk: renesas: cpg-mssr: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSSR Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

Note that this only affects RZ/A2 SoCs.  On R-Car Gen2 and Gen3 SoCs,
the R-Car SYSC driver handles Clock Domain creation, and offloads only
device attachment/detachment to the CPG/MSSR driver.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:57 +02:00
Geert Uytterhoeven 7b8f7a76f2 clk: renesas: r9a06g032: Set GENPD_FLAG_ALWAYS_ON for clock domain
The RZ/N1 Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:52 +02:00
Geert Uytterhoeven a459a184c9 clk: renesas: mstp: Set GENPD_FLAG_ALWAYS_ON for clock domain
The CPG/MSTP Clock Domain driver does not implement the
generic_pm_domain.power_{on,off}() callbacks, as the domain itself
cannot be powered down.  Hence the domain should be marked as always-on
by setting the GENPD_FLAG_ALWAYS_ON flag, to prevent the core PM Domain
code from considering it for power-off, and doing unnessary processing.

This also gets rid of a boot warning when the Clock Domain contains an
IRQ-safe device, e.g. on RZ/A1:

    sh_mtu2 fcff0000.timer: PM domain cpg_clocks will not be powered off

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
2019-08-23 11:09:49 +02:00
Jernej Skrabec 65818ad081 clk: sunxi-ng: h6: Allow I2S to change parent rate
I2S doesn't work if parent rate couldn't be change. Difference between
wanted and actual rate is too big.

Fix this by adding CLK_SET_RATE_PARENT flag to I2S clocks.

Signed-off-by: Jernej Skrabec <jernej.skrabec@siol.net>
Signed-off-by: Marcus Cooper <codekipper@gmail.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-08-21 17:20:31 +08:00
Jerome Brunet 7cfefab656 clk: meson: axg-audio: add g12a reset support
On the g12a, the register space dedicated to the audio clock also
provides some resets. Let the clock controller register a reset
provider as well for this SoC family.

the axg SoC family does not appear to provide this feature.

Reviewed-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-20 11:51:36 +02:00
Jordan Crouse 6311b6521b drivers: qcom: Add BCM vote macro to header
The macro to generate a Bus Controller Manager (BCM) TCS command is used
by the interconnect driver but might also be interesting to other
drivers that need to construct TCS commands for sub processors so move
it out of the sdm845 specific file and into the header.

Signed-off-by: Jordan Crouse <jcrouse@codeaurora.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
2019-08-20 10:09:56 +03:00
Anson Huang 613cc5cd74 clk: imx8mn: Add necessary frequency support for ARM PLL table
i.MX8MN supports CPU running at 1.5GHz/1.4GHz/1.2GHz, add missing
frequency for ARM PLL table.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 15:38:55 +02:00
Anson Huang 313ccbad73 clk: imx8mn: Add missing rate_count assignment for each PLL structure
Add .rate_count assignment which is necessary for searching required
PLL rate from the each PLL table.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 15:36:58 +02:00
Peng Fan f8cade8310 clk: imx8mn: fix int pll clk gate
To Frac pll, the gate shift is 13, however to Int PLL the gate shift
is 11.

Signed-off-by: Peng Fan <peng.fan@nxp.com>
Reviewed-by: Jacky Bai <ping.bai@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:57:47 +02:00
Leonard Crestez be378b6007 clk: imx8mn: Add GIC clock
This is enabled by default but if it's not explicitly defined and marked
as critical then its parent might get turned off.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:40 +02:00
Leonard Crestez b3d08a4b1e clk: imx8mn: Fix incorrect parents
* Replace to audio_pll2_clk with audio_pll2_out
* Replace sys3_pll2_out with sys_pll3_out
* Replace sys1_pll_40m with sys_pll1_40m
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m

Fixes: 96d6392b54 ("clk: imx: Add support for i.MX8MN clock driver")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:36 +02:00
Leonard Crestez 3125c9eb01 clk: imx8mm: Fix incorrect parents
* There is no video_pll2 on imx8mm, replace with dummy
* Replace reference to sys_pll3_clk with sys_pll3_out
* qspi parent[2] is sys_pll2_333m not sys_pll1_800m

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:30 +02:00
Leonard Crestez 78f5666c18 clk: imx8mq: Fix sys3 pll references
The "sys3_pll2_out" CLK was removed in refactoring so all references
need to be updated to "sys3_pll_out"

Fixes: e9dda4af68 ("clk: imx: Refactor entire sccg pll clk")
Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-19 13:54:18 +02:00
Rishi Gupta ef13e55c27 clk: Remove extraneous 'for' word in comments
An extra 'for' word is grammatically incorrect in the comment
'verifying ops for multi-parent clks'. This commit removes
this extra for word.

Signed-off-by: Rishi Gupta <gupt21@gmail.com>
Link: https://lkml.kernel.org/r/1566023759-7880-1-git-send-email-gupt21@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-17 18:13:51 -07:00
Stephen Boyd b0740d71cb clk: composite: Drop unused clk.h include
This include isn't used. Drop it.

Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815042500.9519-1-sboyd@kernel.org
2019-08-16 10:37:01 -07:00
Martin Blumenstingl 24876f09a7 clk: Fix potential NULL dereference in clk_fetch_parent_index()
Don't compare the parent clock name with a NULL name in the
clk_parent_map. This prevents a kernel crash when passing NULL
core->parents[i].name to strcmp().

An example which triggered this is a mux clock with four parents when
each of them is referenced in the clock driver using
clk_parent_data.fw_name and then calling clk_set_parent(clk, 3rd_parent)
on this mux.
In this case the first parent is also the HW default so
core->parents[i].hw is populated when the clock is registered. Calling
clk_set_parent(clk, 3rd_parent) will then go through all parents and
skip the first parent because it's hw pointer doesn't match. For the
second parent no hw pointer is cached yet and clk_core_get(core, 1)
returns a non-matching pointer (which is correct because we are comparing
the second with the third parent). Comparing the result of
clk_core_get(core, 2) with the requested parent gives a match. However
we don't reach this point because right after the clk_core_get(core, 1)
mismatch the old code tried to !strcmp(parent->name, NULL) (where the
second argument is actually core->parents[i].name, but that was never
populated by the clock driver).

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Link: https://lkml.kernel.org/r/20190815223155.21384-1-martin.blumenstingl@googlemail.com
Fixes: fc0c209c14 ("clk: Allow parents to be specified without string names")
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16 10:30:21 -07:00
Stephen Boyd 4f8c6aba37 clk: Fix falling back to legacy parent string matching
Calls to clk_core_get() will return ERR_PTR(-EINVAL) if we've started
migrating a clk driver to use the DT based style of specifying parents
but we haven't made any DT updates yet. This happens when we pass a
non-NULL value as the 'name' argument of of_parse_clkspec(). That
function returns -EINVAL in such a situation, instead of -ENOENT like we
expected. The return value comes back up to clk_core_fill_parent_index()
which proceeds to skip calling clk_core_lookup() because the error
pointer isn't equal to -ENOENT, it's -EINVAL.

Furthermore, we blindly overwrite the error pointer returned by
clk_core_get() with NULL when there isn't a legacy .name member
specified in the parent map. This isn't too bad right now because we
don't really care to differentiate NULL from an error, but in the future
we should only try to do a legacy lookup if we know we might find
something. This way DT lookups that fail don't try to lookup based on
strings when there isn't any string to match, hiding the error from DT
parsing.

Fix both these problems so that clk provider drivers can use the new
style of parent mapping without having to also update their DT at the
same time. This patch is based on an earlier patch from Taniya Das which
checked for -EINVAL in addition to -ENOENT return values from
clk_core_get().

Fixes: 601b6e9330 ("clk: Allow parents to be specified via clkspec index")
Cc: Taniya Das <tdas@codeaurora.org>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Reported-by: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190813214147.34394-1-sboyd@kernel.org
Tested-by: Taniya Das <tdas@codeaurora.org>
2019-08-16 10:28:28 -07:00
Stephen Boyd 0214f33c4e clk: Overwrite clk_hw::init with NULL during clk_register()
We don't want clk provider drivers to use the init structure after clk
registration time, but we leave a dangling reference to it by means of
clk_hw::init. Let's overwrite the member with NULL during clk_register()
so that this can't be used anymore after registration time.

Cc: Bjorn Andersson <bjorn.andersson@linaro.org>
Cc: Doug Anderson <dianders@chromium.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-10-sboyd@kernel.org
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-08-16 10:27:29 -07:00
Stephen Boyd a7b85ad25a clk: sunxi: Don't call clk_hw_get_name() on a hw that isn't registered
The implementation of clk_hw_get_name() relies on the clk_core
associated with the clk_hw pointer existing. If of_clk_hw_register()
fails, there isn't a clk_core created yet, so calling clk_hw_get_name()
here fails. Extract the name first so we can print it later.

Fixes: 1d80c14248 ("clk: sunxi-ng: Add common infrastructure")
Cc: Maxime Ripard <maxime.ripard@bootlin.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-16 10:27:29 -07:00
Stephen Boyd e0e04fc866 clk: ti: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Reported-by: "kernelci.org bot" <bot@kernelci.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815221249.53235-1-sboyd@kernel.org
2019-08-16 10:22:46 -07:00
Stephen Boyd c42144139a clk: qcom: Remove error prints from DFS registration
These aren't useful and they reference the init structure name. Let's
just drop them.

Cc: Taniya Das <tdas@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-5-sboyd@kernel.org
Acked-by: Taniya Das <tdas@codeaurora.org>
2019-08-16 10:21:50 -07:00
Stephen Boyd 1a4549c150 clk: zx296718: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Jun Nie <jun.nie@linaro.org>
Cc: Shawn Guo <shawnguo@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-3-sboyd@kernel.org
2019-08-16 10:20:15 -07:00
Stephen Boyd c8cec4f4af clk: milbeaut: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Sugaya Taichi <sugaya.taichi@socionext.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190815160020.183334-2-sboyd@kernel.org
2019-08-16 10:20:15 -07:00
Stephen Boyd 1bc5557a3b clk: socfpga: deindent code to proper indentation
This code is indented oddly, causing checkpatch to complain. Indent it
properly.

Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190814002402.18154-1-sboyd@kernel.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-08-16 10:20:07 -07:00
Stephen Boyd f6c90df8e7 clk: sprd: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Chunyan Zhang <zhang.chunyan@linaro.org>
Cc: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-8-sboyd@kernel.org
Acked-by: Baolin Wang <baolin.wang@linaro.org>
Acked-by: Chunyan Zhang <zhang.chunyan@linaro.org>
2019-08-16 10:20:07 -07:00
Stephen Boyd 09d4922d3c clk: socfpga: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-7-sboyd@kernel.org
Acked-by: Dinh Nguyen <dinguyen@kernel.org>
2019-08-16 10:20:07 -07:00
Stephen Boyd af55dadfbc clk: sirf: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Guo Zeng <Guo.Zeng@csr.com>
Cc: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-6-sboyd@kernel.org
2019-08-16 10:20:07 -07:00
Stephen Boyd af884a5dfd clk: qcom: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Taniya Das <tdas@codeaurora.org>
Cc: Andy Gross <agross@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-5-sboyd@kernel.org
Acked-by: Taniya Das <tdas@codeaurora.org>
2019-08-16 10:20:07 -07:00
Stephen Boyd 1610dd79d0 clk: meson: axg-audio: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Neil Armstrong <narmstrong@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-4-sboyd@kernel.org
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
2019-08-16 10:20:07 -07:00
Stephen Boyd d6d251f9bb clk: lochnagar: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Charles Keepax <ckeepax@opensource.cirrus.com>
Cc: Richard Fitzgerald <rf@opensource.cirrus.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-3-sboyd@kernel.org
Acked-by: Charles Keepax <ckeepax@opensource.cirrus.com>
2019-08-16 10:20:07 -07:00
Stephen Boyd cf9ec1fc6d clk: actions: Don't reference clk_init_data after registration
A future patch is going to change semantics of clk_register() so that
clk_hw::init is guaranteed to be NULL after a clk is registered. Avoid
referencing this member here so that we don't run into NULL pointer
exceptions.

Cc: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
Link: https://lkml.kernel.org/r/20190731193517.237136-2-sboyd@kernel.org
[sboyd@kernel.org: Move name to after checking for error or NULL hw]
Acked-by: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
2019-08-16 10:19:49 -07:00
Dinh Nguyen c7ec75ea4d clk: socfpga: stratix10: fix rate caclulationg for cnt_clks
Checking bypass_reg is incorrect for calculating the cnt_clk rates.
Instead we should be checking that there is a proper hardware register
that holds the clock divider.

Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Link: https://lkml.kernel.org/r/20190814153014.12962-1-dinguyen@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-14 09:23:21 -07:00
Paul Cercueil 03d570e1a4 clk: ingenic: Use CLK_OF_DECLARE_DRIVER macro
By using CLK_OF_DECLARE_DRIVER instead of the CLK_OF_DECLARE macro, we
allow the driver to probe also as a platform driver.

While this driver does not have code to probe as a platform driver, this
is still useful for probing children devices in the case where the
device node is compatible with "simple-mfd".

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20190810123620.27238-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-12 10:59:50 -07:00
Anson Huang e8760d8a69 clk: imx8mq: Unregister clks when of_clk_add_provider failed
When of_clk_add_provider failed, all clks should be unregistered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-12 16:15:49 +02:00
Anson Huang ef7e6a1284 clk: imx8mm: Unregister clks when of_clk_add_provider failed
When of_clk_add_provider failed, all clks should be unregistered.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-12 16:15:31 +02:00
Sudeep Holla d0aba11614 firmware: arm_scmi: Drop config flag in clk_ops->rate_set
CLOCK_PROTOCOL_ATTRIBUTES provides attributes to indicate the maximum
number of pending asynchronous clock rate changes supported by the
platform. If it's non-zero, then we should be able to use asynchronous
clock rate set for any clocks until the maximum limit is reached.

In order to add that support, let's drop the config flag passed to
clk_ops->rate_set and handle the asynchronous requests dynamically.

Cc: Stephen Boyd <sboyd@kernel.org>
Cc: linux-clk@vger.kernel.org
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2019-08-12 12:23:01 +01:00
Icenowy Zheng 0ed4c252bf
clk: sunxi-ng: v3s: add Allwinner V3 support
Allwinner V3 has the same main die with V3s, but with more pins wired.
There's a I2S bus on V3 that is not available on V3s.

Add the V3-only peripheral's clocks and reset to the V3s CCU driver,
bound to a new V3 compatible string. The driver name is not changed
because it's part of the device tree binding (the header file name).

Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-12 10:05:48 +02:00
Icenowy Zheng 720099603d
clk: sunxi-ng: v3s: add missing clock slices for MMC2 module clocks
The MMC2 clock slices are currently not defined in V3s CCU driver, which
makes MMC2 not working.

Fix this issue.

Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-08-12 10:05:13 +02:00
Jerome Brunet 1d97657a47 Merge branch 'v5.4/dt' into v5.4/drivers 2019-08-09 12:12:58 +02:00
Neil Armstrong 85ab9d9546 clk: meson: g12a: expose CPUB clock ID for G12B
Expose the CPUB clock id to add DVFS to the second CPU cluster of
the Amlogic G12B SoC.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09 12:12:37 +02:00
Neil Armstrong ffae8475b9 clk: meson: g12a: add notifiers to handle cpu clock change
In order to implement clock switching for the CLKID_CPU_CLK and
CLKID_CPUB_CLK, notifiers are added on specific points of the
clock tree :

cpu_clk / cpub_clk
|   \- cpu_clk_dyn
|      |  \- cpu_clk_premux0
|      |        |- cpu_clk_postmux0
|      |        |    |- cpu_clk_dyn0_div
|      |        |    \- xtal/fclk_div2/fclk_div3
|      |        \- xtal/fclk_div2/fclk_div3
|      \- cpu_clk_premux1
|            |- cpu_clk_postmux1
|            |    |- cpu_clk_dyn1_div
|            |    \- xtal/fclk_div2/fclk_div3
|            \- xtal/fclk_div2/fclk_div3
\ sys_pll / sys1_pll

This for each cluster, a single one for G12A, two for G12B.

Each cpu_clk_premux1 tree is marked as read-only and CLK_SET_RATE_NO_REPARENT,
to be used as "parking" clock in a safe clock frequency.

A notifier is added on each cpu_clk_premux0 to detech when CCF want to
change the frequency of the cpu_clk_dyn tree.
In this notifier, the cpu_clk_premux1 tree is configured to use the xtal
clock and then the cpu_clk_dyn is switch to cpu_clk_premux1 while CCF
updates the cpu_clk_premux0 tree.

A notifier is added on each sys_pll/sys1_pll to detect when CCF wants to
change the PLL clock source of the cpu_clk.
In this notifier, the cpu_clk is switched to cpu_clk_dyn while CCF
updates the sys_pll/sys1_pll frequency.

A third small notifier is added on each cpu_clk / cpub_clk and cpu_clk_dyn,
add a small delay at PRE_RATE_CHANGE/POST_RATE_CHANGE to let the other
notofiers change propagate before changing the cpu_clk_premux0 and sys_pll
clock trees.

This notifier set permits switching the cpu_clk / cpub_clk without any
glitches and using a safe parking clock while switching between sub-GHz
clocks using the cpu_clk_dyn tree.

This setup has been tested and validated on the Amlogic G12A and G12B
SoCs running the arm64 cpuburn at [1] and cycling between all the possible
cpufreq translations of each cluster and checking the final frequency using
the clock-measurer, script at [2].

[1] https://github.com/ssvb/cpuburn-arm/blob/master/cpuburn-a53.S
[2] https://gist.github.com/superna9999/d4de964dbc0f84b7d527e1df2ddea25f

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09 12:10:03 +02:00
Neil Armstrong 26d34431ad clk: meson: add g12a cpu dynamic divider driver
Add a clock driver for the cpu dynamic divider, this divider needs
to have a flag set before setting the divider value then removed
while writing the new value to the register.

This drivers implements this behavior and will be used essentially
on the Amlogic G12A and G12B SoCs for cpu clock trees.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09 12:10:03 +02:00
Neil Armstrong 3567894b69 clk: core: introduce clk_hw_set_parent()
Introduce the clk_hw_set_parent() provider call to change parent of
a clock by using the clk_hw pointers.

This eases the clock reparenting from clock rate notifiers and
implementing DVFS with simpler code avoiding the boilerplates
functions as __clk_lookup(clk_hw_get_name()) then clk_set_parent().

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Acked-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-08-09 12:09:52 +02:00
Paul Cercueil 73dd11dc1a
clk: jz4740: Add TCU clock
Add the missing TCU clock to the list of clocks supplied by the CGU for
the JZ4740 SoC.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
2019-08-08 15:30:08 -07:00
Paul Cercueil 4f89e4b8f1
clk: ingenic: Add driver for the TCU clocks
Add driver to support the clocks provided by the Timer/Counter Unit
(TCU) of the JZ47xx SoCs from Ingenic.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Tested-by: Mathieu Malaterre <malat@debian.org>
Tested-by: Artur Rojek <contact@artur-rojek.eu>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Paul Burton <paul.burton@mips.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: James Hogan <jhogan@kernel.org>
Cc: Jonathan Corbet <corbet@lwn.net>
Cc: Lee Jones <lee.jones@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Daniel Lezcano <daniel.lezcano@linaro.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Michael Turquette <mturquette@baylibre.com>
Cc: Jason Cooper <jason@lakedaemon.net>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Rob Herring <robh+dt@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: devicetree@vger.kernel.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-doc@vger.kernel.org
Cc: linux-mips@vger.kernel.org
Cc: linux-clk@vger.kernel.org
Cc: od@zcrc.me
2019-08-08 15:30:07 -07:00
Marek Szyprowski baf7b79e1a clk: samsung: exynos542x: Move MSCL subsystem clocks to its sub-CMU
M2M scaler clocks require special handling of their parent bus clock during
power domain on/off sequences. MSCL clocks were not initially added to the
sub-CMU handler, because that time there was no driver for the M2M scaler
device and it was not possible to test it.

This patch fixes this issue. Parent clock for M2M scaler devices is now
properly preserved during MSC power domain on/off sequence. This gives M2M
scaler devices proper performance: fullHD XRGB32 image 1000 rotations test
takes 3.17s instead of 45.08s.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Link: https://lkml.kernel.org/r/20190808121839.23892-1-m.szyprowski@samsung.com
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 13:54:38 -07:00
Sylwester Nawrocki b6adeb6bc6 clk: samsung: exynos5800: Move MAU subsystem clocks to MAU sub-CMU
This patch fixes broken sound on Exynos5422/5800 platforms after
system/suspend resume cycle in cases where the audio root clock
is derived from MAU_EPLL_CLK.

In order to preserve state of the USER_MUX_MAU_EPLL_CLK clock mux
during system suspend/resume cycle for Exynos5800 we group the MAU
block input clocks in "MAU" sub-CMU and add the clock mux control
bit to .suspend_regs.  This ensures that user configuration of the mux
is not lost after the PMU block changes the mux setting to OSC_DIV
when switching off the MAU power domain.

Adding the SRC_TOP9 register to exynos5800_clk_regs[] array is not
sufficient as at the time of the syscore_ops suspend call MAU power
domain is already turned off and we already save and subsequently
restore an incorrect register's value.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Reported-by: Jaafar Ali <jaafarkhalaf@gmail.com>
Suggested-by: Marek Szyprowski <m.szyprowski@samsung.com>
Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lkml.kernel.org/r/20190808144929.18685-2-s.nawrocki@samsung.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 13:53:58 -07:00
Sylwester Nawrocki bf32e7dbfc clk: samsung: Change signature of exynos5_subcmus_init() function
In order to make it easier in subsequent patch to create different subcmu
lists for exynos5420 and exynos5800 SoCs the code is rewritten so we pass
an array of pointers to the subcmus initialization function.

Fixes: b06a532bf1 ("clk: samsung: Add Exynos5 sub-CMU clock driver")
Tested-by: Jaafar Ali <jaafarkhalaf@gmail.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Link: https://lkml.kernel.org/r/20190808144929.18685-1-s.nawrocki@samsung.com
Reviewed-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 13:53:42 -07:00
Gregory CLEMENT baf4c10f88 clk: mvebu: ap806: Fix clock name for the cluster
Actually, the clocks exposed for the cluster are not the CPU clocks, but
the PLL clock used as entry clock for the CPU clocks. The CPU clock will
be managed by a driver submitting in the following patches.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lkml.kernel.org/r/20190710134346.30239-5-gregory.clement@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 09:08:09 -07:00
Gregory CLEMENT f756e362d9 clk: mvebu: add CPU clock driver for Armada 7K/8K
The CPU frequency is managed at the AP level for the Armada 7K/8K. The
CPU frequency is modified by cluster: the CPUs of the same cluster have
the same frequency.

This patch adds the clock driver that will be used by CPUFreq, it is
based on the work of Omri Itach <omrii@marvell.com>.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lkml.kernel.org/r/20190710134346.30239-4-gregory.clement@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 09:08:09 -07:00
Gregory CLEMENT 33c0259092 clk: mvebu: add helper file for Armada AP and CP clocks
Clock drivers for Armada AP and Armada CP use the same function to
generate unique clock name. A third drivers is coming with the same
need, so it's time to move this function in a common file.

Signed-off-by: Gregory CLEMENT <gregory.clement@bootlin.com>
Link: https://lkml.kernel.org/r/20190710134346.30239-3-gregory.clement@bootlin.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 09:08:09 -07:00
Govind Singh 75e0a1e301 clk: qcom: define probe by index API as common API
Extend the probe by index API in common code to be used
by other qcom clock controller.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:20:01 -07:00
yong.liang 64ebb57a3d clk: reset: Modify reset-controller driver
Set reset signal by a register and
clear reset signal by another register for 8183.

Signed-off-by: yong.liang <yong.liang@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:19:21 -07:00
Govind Singh 7d0c76bdf2 clk: qcom: Add WCSS gcc clock control for QCS404
Add support for the WCSS QDSP gcc clock control used on qcs404
based devices. This would allow wcss remoteproc driver to control
the required gcc clocks to bring the subsystem out of reset.

Signed-off-by: Govind Singh <govinds@codeaurora.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:10:05 -07:00
Markus Elfring 1ccc0ddf04 clk: Use seq_puts() in possible_parent_show()
A string which did not contain a data format specification should be put
into a sequence. Thus use the corresponding function “seq_puts”.

This issue was detected by using the Coccinelle software.

Signed-off-by: Markus Elfring <elfring@users.sourceforge.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:03:17 -07:00
Leonard Crestez 9f77672260 clk: Assert prepare_lock in clk_core_get_boundaries
This function iterates the clk consumer list on clk_core so it must be
called under prepare_lock. This is already done by all callers but add a
lockdep assert to check anyway.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Link: https://lkml.kernel.org/r/29453ee8e820457d87a8faf9d496390e59c6826f.1562073871.git.leonard.crestez@nxp.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:02:21 -07:00
Leonard Crestez 1bd37a4677 clk: Add clk_min/max_rate entries in debugfs
Add two files to expose min/max clk rates as determined by
clk_core_get_boundaries, taking all consumer requests into account.

This information does not appear to be otherwise exposed to userspace.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Link: https://lkml.kernel.org/r/68e96af2df96512300604d797ade2088d7e6e496.1562073871.git.leonard.crestez@nxp.com
[sboyd@kernel.org: Drop if statements for JSON printing]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-08 08:02:00 -07:00
Geert Uytterhoeven e96a926104 clk: renesas: rcar-usb2-clock-sel: Use devm_platform_ioremap_resource() helper
Use the devm_platform_ioremap_resource() helper instead of open-coding
the same operation.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
2019-08-08 10:22:59 +02:00
Marc Gonzalez 56bf8740ff clk: qcom: msm8916: Don't build by default
QCOM_A53PLL and QCOM_CLK_APCS_MSM8916 stand out as the only options
built by default. Let's bring them back in line with the rest.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Link: https://lkml.kernel.org/r/d654907d-a3a2-a00f-d6f5-3a34ae25ebcf@free.fr
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Acked-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 21:29:48 -07:00
Nishka Dasgupta b684702f6e clk: ti: dm814x: Add of_node_put() to prevent memory leak
In function dm814x_adpll_early_init, variable np takes the value
returned by of_find_node_by_name, which gets a node but does not put it.
If np is not put before return, it may cause a memory leak. Hence put np
before return.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190804163328.6693-1-nishkadg.linux@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:26:39 -07:00
Nishka Dasgupta d432d04560 clk: st: clk-flexgen: Add of_node_put() in st_of_flexgen_setup()
In function st_of_flexgen_setup, variable pnode takes the return value
of of_get_parent, which gets a node but does not put it. If pnode is not
put before the function returns, it may cause a memory leak. Hence put
pnode after its last occurrence.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190804163151.6511-1-nishkadg.linux@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:26:32 -07:00
Nishka Dasgupta d55841ce11 clk: davinci: pll: Add of_node_put() in of_davinci_pll_init()
The variable child in the function of_davinci_pll_init takes the value
of of_get_child_by_name, which gets a node but does not put it. If child
is not put before the function returns it may cause a memory leak. Hence
put child before two return statements.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190804162824.6338-1-nishkadg.linux@gmail.com
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:25:45 -07:00
Nishka Dasgupta 5911dba556 clk: versatile: Add of_node_put() in cm_osc_setup()
In function cm_osc_setup, variable parent takes the value returned by
of_get_parent, which gets a node but does not put it. If parent is not
put before it goes out of scope, it may cause a memory leak.
Hence put parent before the function terminates.
Issue found with Coccinelle.

Signed-off-by: Nishka Dasgupta <nishkadg.linux@gmail.com>
Link: https://lkml.kernel.org/r/20190804163445.6862-1-nishkadg.linux@gmail.com
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:25:25 -07:00
Deepak Katragadda 2a1d7eb854 clk: qcom: gcc: Add global clock controller driver for SM8150
Add the clocks supported in global clock controller which clock the
peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks
to the clock framework for the clients to be able to request for them.

Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and tidy-up
	port to new parent scheme
	Add comments for critical clocks]]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-6-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:12:05 -07:00
Deepak Katragadda 548a909597 clk: qcom: clk-alpha-pll: Add support for Trion PLLs
Add programming sequence support for managing the Trion
PLLs.

Signed-off-by: Deepak Katragadda <dkatraga@codeaurora.org>
Signed-off-by: Taniya Das <tdas@codeaurora.org>
[vkoul: port to upstream and tidy-up
	use upstream way of specifying PLLs]
Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-4-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:12:05 -07:00
Vinod Koul 4c45653b0b clk: qcom: clk-alpha-pll: Remove post_div_table checks
We want users to code properly and fix the post_div_table missing and
not rely on core to check. So remove the post_div_table check.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-3-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:12:05 -07:00
Vinod Koul 46e625b3e3 clk: qcom: clk-alpha-pll: Remove unnecessary cast
Commit 8f9fab480c ("linux/kernel.h: fix overflow for
DIV_ROUND_UP_ULL") fixed the overflow for DIV_ROUND_UP_ULL, so we no
longer need the cast for DIV_ROUND_UP_ULL, so remove the unnecessary
u64 casts.

Signed-off-by: Vinod Koul <vkoul@kernel.org>
Link: https://lkml.kernel.org/r/20190722074348.29582-2-vkoul@kernel.org
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 15:12:05 -07:00
Paul Cercueil 568b9de48d clk: ingenic/jz4740: Fix "pll half" divider not read/written properly
The code was setting the bit 21 of the CPCCR register to use a divider
of 2 for the "pll half" clock, and clearing the bit to use a divider
of 1.

This is the opposite of how this register field works: a cleared bit
means that the /2 divider is used, and a set bit means that the divider
is 1.

Restore the correct behaviour using the newly introduced .div_table
field.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Link: https://lkml.kernel.org/r/20190701113606.4130-1-paul@crapouillou.net
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 14:33:39 -07:00
Colin Ian King e2f2402f3b clk: Si5341/Si5340: remove redundant assignment to n_den
The variable n_den is initialized however that value is never read
as n_den is re-assigned a little later in the two paths of a
following if-statement.  Remove the redundant assignment.

Addresses-Coverity: ("Unused value")
Signed-off-by: Colin Ian King <colin.king@canonical.com>
Link: https://lkml.kernel.org/r/20190701165020.19840-1-colin.king@canonical.com
Acked-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 14:23:24 -07:00
Nathan Huckleberry a95fb581b1 clk: qoriq: Fix -Wunused-const-variable
drivers/clk/clk-qoriq.c:138:38: warning: unused variable
'p5020_cmux_grp1' [-Wunused-const-variable] static const struct
clockgen_muxinfo p5020_cmux_grp1

drivers/clk/clk-qoriq.c:146:38: warning: unused variable
'p5020_cmux_grp2' [-Wunused-const-variable] static const struct
clockgen_muxinfo p5020_cmux_grp2

In the definition of the p5020 chip, the p2041 chip's info was used
instead.  The p5020 and p2041 chips have different info. This is most
likely a typo.

Link: https://github.com/ClangBuiltLinux/linux/issues/525
Cc: clang-built-linux@googlegroups.com
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Link: https://lkml.kernel.org/r/20190627220642.78575-1-nhuck@google.com
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Acked-by: Scott Wood <oss@buserror.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 14:17:49 -07:00
Joel Stanley ebd5f82d32 clk: aspeed: Add SDIO gate
The clock divisor comes with an enable bit (gate). This was not
implemented as we didn't have access to SD hardware when writing the
driver. Now that we can test it, add the gate as a parent to the
divisor.

There is no reason to expose the gate separately, so users will enable
it by turning on the ASPEED_CLK_SDIO divisor.

Signed-off-by: Joel Stanley <joel@jms.id.au>
[aj: Minor style cleanup]
Signed-off-by: Andrew Jeffery <andrew@aj.id.au>
Link: https://lkml.kernel.org/r/20190710141009.20651-1-andrew@aj.id.au
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-08-07 14:15:31 -07:00
Abel Vesa 9b9c60bed5 clk: imx8mq: Mark AHB clock as critical
Initially, the TMU_ROOT clock was marked as critical, which automatically
made the AHB clock to stay always on. Since the TMU_ROOT clock is not
marked as critical anymore, following commit:

"clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT"

all the clocks that derive from ipg_root clock (and implicitly ahb clock)
would also have to enable, along with their own gate, the AHB clock.

But considering that AHB is actually a bus that has to be always on, we mark
it as critical in the clock provider driver and then all the clocks that
derive from it can be controlled through the dedicated per IP gate which
follows after the ipg_root clock.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Tested-by: Daniel Baluta <daniel.baluta@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 17:00:47 +02:00
Anson Huang f7988ba3b2 clk: imx8mn: Keep uart clocks on for early console
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 11:03:48 +02:00
Anson Huang 5133f1f3cc clk: imx: Remove unused function statement
imx_register_uart_clocks_hws() function is NOT implemented
at all, remove it.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 10:56:37 +02:00
Anson Huang b87340998a clk: imx7ulp: Make sure earlycon's clock is enabled
Earlycon's clock could be disabled during kernel boot up,
if earlycon is enabled and its clock is gated, then kernel
boot up will fail. Make sure earlycon's clock is enabled
during kernel boot up.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 10:54:44 +02:00
Abel Vesa af7e7ee0e4 clk: imx8mm: Switch to platform driver
There is no strong reason for this to use CLK_OF_DECLARE instead
of being a platform driver. Plus, this will now be aligned with the
other i.MX8M clock drivers which are platform drivers.

In order to make the clock provider a platform driver
all the data and code needs to be outside of .init section.

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 10:13:27 +02:00
Peng Fan 053a4ffe29 clk: imx: imx8mm: fix audio pll setting
The AUDIO PLL max support 650M, so the original clk settings violate
spec. This patch makes the output 786432000 -> 393216000,
and 722534400 -> 361267200 to aligned with NXP vendor kernel without any
impact on audio functionality and go within 650MHz PLL limit.

Cc: <stable@vger.kernel.org>
Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Peng Fan <peng.fan@nxp.com>
Acked-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:04 +02:00
Anson Huang d4c5792e2a clk: imx8mm: GPT1 clock mux option #5 should be sys_pll1_80m
i.MX8MM's GPT1 clock mux option #5 should be sys_pll1_80m,
NOT sys_pll1_800m, correct it.

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:04 +02:00
Anson Huang d52fb0193f clk: imx8mm: Fix typo of pwm3 clock's mux option #4
i.MX8MM has no sys3_pll2_out clock, PWM3 clock's mux option #4
should be sys_pll3_out, sys3_pll2_out is a typo, fix it.

Fixes: ba5625c3e2 ("clk: imx: Add clock driver support for imx8mm")
Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:03 +02:00
Abel Vesa e50bf7a67c clk: imx: Remove unused clk based API
Now that the i.MX6 and i.MX7 clock drivers have been switched to clk_hw based,
we can remove the clk based API that is not used by any i.MX clock driver.

The following APIs are going away now:
- imx_clk_busy_divider
- imx_clk_busy_mux
- imx_clk_fixup_divider
- imx_clk_fixup_mux
- imx_clk_mux_ldb
- imx_clk_gate_dis_flags
- imx_clk_gate_flags

Signed-off-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:03 +02:00
Li Jun 0d381f4c80 clk: imx8mq: set correct parent for usb ctrl clocks
Per latest imx8mq datasheet of CCM, the parent of usb1_ctrl_root_clk
and usb2_ctrl_root_clk is usb_bus.

Signed-off-by: Li Jun <jun.li@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:03 +02:00
Daniel Baluta 6ad7cb7122 clk: imx8: Add DSP related clocks
i.MX8QXP contains Hifi4 DSP. There are four clocks
associated with DSP:
  * dsp_lpcg_core_clk
  * dsp_lpcg_ipg_clk
  * dsp_lpcg_adb_aclk
  * ocram_lpcg_ipg_clk

Signed-off-by: Daniel Baluta <daniel.baluta@nxp.com>
Reviewed-by: Dong Aisheng <aisheng.dong@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:02 +02:00
Anson Huang 951c1aef96 clk: imx8mq: Remove CLK_IS_CRITICAL flag for IMX8MQ_CLK_TMU_ROOT
IMX8MQ_CLK_TMU_ROOT is ONLY used for thermal module, the driver
should manage this clock, so no need to have CLK_IS_CRITICAL flag
set.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Reviewed-by: Abel Vesa <abel.vesa@nxp.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:02 +02:00
Anson Huang 96d6392b54 clk: imx: Add support for i.MX8MN clock driver
This patch adds i.MX8MN clock driver support.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:02 +02:00
Fancy Fang 0209001674 clk: imx8mm: rename 'share_count_dcss' to 'share_count_disp'
Rename 'share_count_dcss' to 'share_count_disp', since the
DCSS module does not exist on imx8mm platform. So rename it
to avoid any unnecessary confusion.

Signed-off-by: Fancy Fang <chen.fang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:02 +02:00
Li Jun d1b395b36e clk: imx8mm: correct the usb1_ctrl parent to be usb_bus
Per latest imx8mm datasheet of CCM, the parent of usb1_ctrl_root_clk
should be usb_bus.

Signed-off-by: Li Jun <jun.li@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:02 +02:00
Anson Huang fd6ef2857b clk: imx: Add API for clk unregister when driver probe fail
For i.MX clock drivers probe fail case, clks should be unregistered
in the return path, this patch adds a common API for i.MX clock
drivers to unregister clocks when fail.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:01 +02:00
Anson Huang 34af5179d2 clk: imx8mm: Make 1416X/1443X PLL macro definitions common for usage
1416X/1443X PLL are used on i.MX8MM and i.MX8MN and maybe
other i.MX8M series SoC later, the macro definitions of
these PLLs' initialization should be common for usage.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-08-03 09:16:01 +02:00
Alexandre Mergnat e96c761231 clk: meson: remove clk input helper
The clk input function which allows clock controllers to register a bypass
clock from a clock producer is no longer needed anymore since meson clock
controllers have migrated to a new parent allocation method.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:49 +02:00
Alexandre Mergnat b11cfaba5b clk: meson: remove ee input bypass clocks
During probe, bypass clocks (i.e. ee-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of this method are the duplicated clocks, means more string
comparison.

Specify parent directly with device-tree clock name.

Remove the bypass clock registration from the ee probe function.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:49 +02:00
Alexandre Mergnat 3a36044e7f clk: meson: clk-regmap: migrate to new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:49 +02:00
Alexandre Mergnat 4b5b85c0e6 clk: meson: meson8b: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Tested-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:49 +02:00
Alexandre Mergnat cc132d113d clk: meson: axg: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat 0dea3f3599 clk: meson: gxbb: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat 25e682a02d clk: meson: g12a: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (ie. when
all clocks are local to the controller) and use .parent_data otherwise.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat 072a043f5a clk: meson: remove ao input bypass clocks
During probe, bypass clocks (i.e. ao-in-xtal) are made from device-tree
inputs to provide input clocks which can be access through global name.
The cons of this method are the duplicated clocks, means more string
comparison.

Specify parent directly with device-tree clock name.

Function to regiter bypass clocks is removed.

Input parameters from meson aoclk data structure are deprecated and then
deleted since all aoclk files are migrated.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat b90ec1e344 clk: meson: axg-aoclk: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat 6e2bfc352e clk: meson: gxbb-aoclk: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat ba62608110 clk: meson: g12a-aoclk: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Alexandre Mergnat 282420eed2 clk: meson: axg-audio: migrate to the new parent description method
This clock controller use the string comparison method to describe parent
relation between the clocks, which is not optimized. A recent patch [0]
allows parents to be specified without string names or with device-tree
clock name by using a new assignment structure.

Migrate to the new way by using .parent_hws where possible (when parent
clocks are localy declared in the controller) and use .parent_data
otherwise.

Remove clk input helper and all bypass clocks (declared in probe function)
which are no longer used since we are able to use device-tree clock name
directly.

[0] commit fc0c209c14 ("clk: Allow parents to be specified without string names")

Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
[jbrunet@baylibre.com: remove CLK_SET_RATE_PARENT from mst muxes]
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-29 12:42:48 +02:00
Nathan Huckleberry 7114fbdaa2 clk: rockchip: Fix -Wunused-const-variable in rv1108 clk driver
Clang produces the following warning

drivers/clk/rockchip/clk-rv1108.c:125:7: warning: unused variable
'mux_pll_src_3plls_p' [-Wunused-const-variable]
PNAME(mux_pll_src_3plls_p)      = { "apll", "gpll", "dpll" };

Looks like this variable was never used. Deleting it to remove the
warning.

Cc: clang-built-linux@googlegroups.com
Link: https://github.com/ClangBuiltLinux/linux/issues/524
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-07-25 21:00:52 +02:00
Alexandre Mergnat b6297d9e07 clk: meson: g12a: fix hifi typo in mali parent_names
Replace hihi by hifi in the mali parent_names of the g12a SoC family.

Fixes: 085a4ea93d ("clk: meson: g12a: add peripheral clock controller")
Signed-off-by: Alexandre Mergnat <amergnat@baylibre.com>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-07-25 14:52:38 +02:00
Geert Uytterhoeven e1f1ae8002 clk: renesas: cpg-mssr: Fix reset control race condition
The module reset code in the Renesas CPG/MSSR driver uses
read-modify-write (RMW) operations to write to a Software Reset Register
(SRCRn), and simple writes to write to a Software Reset Clearing
Register (SRSTCLRn), as was mandated by the R-Car Gen2 and Gen3 Hardware
User's Manuals.

However, this may cause a race condition when two devices are reset in
parallel: if the reset for device A completes in the middle of the RMW
operation for device B, device A may be reset again, causing subtle
failures (e.g. i2c timeouts):

	thread A			thread B
	--------			--------

	val = SRCRn
	val |= bit A
	SRCRn = val

	delay

					val = SRCRn (bit A is set)

	SRSTCLRn = bit A
	(bit A in SRCRn is cleared)

					val |= bit B
					SRCRn = val (bit A and B are set)

This can be reproduced on e.g. Salvator-XS using:

    $ while true; do i2cdump -f -y 4 0x6A b > /dev/null; done &
    $ while true; do i2cdump -f -y 2 0x10 b > /dev/null; done &

    i2c-rcar e6510000.i2c: error -110 : 40000002
    i2c-rcar e66d8000.i2c: error -110 : 40000002

According to the R-Car Gen3 Hardware Manual Errata for Rev.
0.80 of Feb 28, 2018, reflected in Rev. 1.00 of the R-Car Gen3 Hardware
User's Manual, writes to SRCRn do not require read-modify-write cycles.

Note that the R-Car Gen2 Hardware User's Manual has not been updated
yet, and still says a read-modify-write sequence is required.  According
to the hardware team, the reset hardware block is the same on both R-Car
Gen2 and Gen3, though.

Hence fix the issue by replacing the read-modify-write operations on
SRCRn by simple writes.

Reported-by: Yao Lihua <Lihua.Yao@desay-svautomotive.com>
Fixes: 6197aa65c4 ("clk: renesas: cpg-mssr: Add support for reset control")
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Tested-by: Linh Phung <linh.phung.jy@renesas.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 15:04:54 -07:00
Chunyan Zhang c9a67cbb51 clk: sprd: Select REGMAP_MMIO to avoid compile errors
Make REGMAP_MMIO selected to avoid undefined reference to regmap symbols.

Fixes: d41f59fd92 ("clk: sprd: Add common infrastructure")
Signed-off-by: Chunyan Zhang <chunyan.zhang@unisoc.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 14:54:26 -07:00
Weiyi Lu c93d059a80 clk: mediatek: mt8183: Register 13MHz clock earlier for clocksource
The 13MHz clock should be registered before clocksource driver is
initialized. Use CLK_OF_DECLARE_DRIVER() to guarantee.

Fixes: acddfc2c26 ("clk: mediatek: Add MT8183 clock support")
Cc: <stable@vger.kernel.org>
Signed-off-by: Weiyi Lu <weiyi.lu@mediatek.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 14:32:52 -07:00
Codrin Ciubotariu 1573eebeaa clk: at91: generated: Truncate divisor to GENERATED_MAX_DIV + 1
In clk_generated_determine_rate(), if the divisor is greater than
GENERATED_MAX_DIV + 1, then the wrong best_rate will be returned.
If clk_generated_set_rate() will be called later with this wrong
rate, it will return -EINVAL, so the generated clock won't change
its value. Do no let the divisor be greater than GENERATED_MAX_DIV + 1.

Fixes: 8c7aa63289 ("clk: at91: clk-generated: remove useless divisor loop")
Signed-off-by: Codrin Ciubotariu <codrin.ciubotariu@microchip.com>
Acked-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Acked-by: Ludovic Desroches <ludovic.desroches@microchip.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-22 14:32:08 -07:00
Icenowy Zheng c5ed9475c2
clk: sunxi-ng: v3s: add the missing PLL_DDR1
The user manual of V3/V3s/S3 declares a PLL_DDR1, however it's forgot
when developing the V3s CCU driver.

Add back the missing PLL_DDR1.

Fixes: d0f11d14b0 ("clk: sunxi-ng: add support for V3s CCU")
Signed-off-by: Icenowy Zheng <icenowy@aosc.io>
Signed-off-by: Maxime Ripard <maxime.ripard@bootlin.com>
2019-07-22 08:33:20 +02:00
Linus Torvalds 916f562fb2 This round of clk driver and framework updates is heavy on the driver update
side. The two main highlights in the core framework are the addition of an bulk
 clk_get API that handles optional clks and an extra debugfs file that tells the
 developer about the current parent of a clk.
 
 The driver updates are dominated by i.MX in the diffstat, but that is mostly
 because that SoC has started converting to the clk_hw style of clk
 registration. The next big update is in the Amlogic meson clk driver that
 gained some support for audio, cpu, and temperature clks while fixing some PLL
 issues. Finally, the biggest thing that stands out is the conversion of a large
 part of the Allwinner sunxi-ng driver to the new clk parent scheme that uses
 less strings and more pointer comparisons to match clk parents and children up.
 
 In general, it looks like we have a lot of little fixes and tweaks here and
 there to clk data along with the normal addition of a handful of new drivers
 and a couple new core framework features.
 
 Core:
  - Add a 'clk_parent' file in clk debugfs
  - Add a clk_bulk_get_optional() API (with devm too)
 
 New Drivers:
  - Support gated clk controller on MIPS based BCM63XX SoCs
  - Support SiLabs Si5341 and Si5340 chips
  - Support for CPU clks on Raspberry Pi devices
  - Audsys clock driver for MediaTek MT8516 SoCs
 
 Updates:
  - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
  - Small frequency support for SiLabs Si544 chips
  - Slow clk support for AT91 SAM9X60 SoCs
  - Remove dead code in various clk drivers (-Wunused)
  - Support for Marvell 98DX1135 SoCs
  - Get duty cycle of generic pwm clks
  - Improvement in mmc phase calculation and cleanup of some rate defintions
  - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
  - Add GPIO, SNVS and GIC clocks for i.MX8 drivers
  - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
  - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
  - Add clks for new Exynos5422 Dynamic Memory Controller driver
  - Clock definition for Exynos4412 Mali
  - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
  - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
  - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
  - TI clock probing done from DT by default instead of firmware
  - Fix Amlogic Meson mpll fractional part and spread sprectrum issues
  - Add Amlogic meson8 audio clocks
  - Add Amlogic g12a temperature sensors clocks
  - Add Amlogic g12a and g12b cpu clocks
  - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
  - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
  - Add Clock Domain support on Renesas RZ/N1
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Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk updates from Stephen Boyd:
 "This round of clk driver and framework updates is heavy on the driver
  update side. The two main highlights in the core framework are the
  addition of an bulk clk_get API that handles optional clks and an
  extra debugfs file that tells the developer about the current parent
  of a clk.

  The driver updates are dominated by i.MX in the diffstat, but that is
  mostly because that SoC has started converting to the clk_hw style of
  clk registration. The next big update is in the Amlogic meson clk
  driver that gained some support for audio, cpu, and temperature clks
  while fixing some PLL issues. Finally, the biggest thing that stands
  out is the conversion of a large part of the Allwinner sunxi-ng driver
  to the new clk parent scheme that uses less strings and more pointer
  comparisons to match clk parents and children up.

  In general, it looks like we have a lot of little fixes and tweaks
  here and there to clk data along with the normal addition of a handful
  of new drivers and a couple new core framework features.

  Core:
   - Add a 'clk_parent' file in clk debugfs
   - Add a clk_bulk_get_optional() API (with devm too)

  New Drivers:
   - Support gated clk controller on MIPS based BCM63XX SoCs
   - Support SiLabs Si5341 and Si5340 chips
   - Support for CPU clks on Raspberry Pi devices
   - Audsys clock driver for MediaTek MT8516 SoCs

  Updates:
   - Convert a large portion of the Allwinner sunxi-ng driver to new clk parent scheme
   - Small frequency support for SiLabs Si544 chips
   - Slow clk support for AT91 SAM9X60 SoCs
   - Remove dead code in various clk drivers (-Wunused)
   - Support for Marvell 98DX1135 SoCs
   - Get duty cycle of generic pwm clks
   - Improvement in mmc phase calculation and cleanup of some rate defintions
   - Switch i.MX6 and i.MX7 clock drivers to clk_hw based APIs
   - Add GPIO, SNVS and GIC clocks for i.MX8 drivers
   - Mark imx6sx/ul/ull/sll MMDC_P1_IPG and imx8mm DRAM_APB as critical clock
   - Correct imx7ulp nic1_bus_clk and imx8mm audio_pll2_clk clock setting
   - Add clks for new Exynos5422 Dynamic Memory Controller driver
   - Clock definition for Exynos4412 Mali
   - Add CMM (Color Management Module) clocks on Renesas R-Car H3, M3-N, E3, and D3
   - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas RZ/G2M
   - Support for 32 bit clock IDs in TI's sci-clks for J721e SoCs
   - TI clock probing done from DT by default instead of firmware
   - Fix Amlogic Meson mpll fractional part and spread sprectrum issues
   - Add Amlogic meson8 audio clocks
   - Add Amlogic g12a temperature sensors clocks
   - Add Amlogic g12a and g12b cpu clocks
   - Add TPU (Timer Pulse Unit / PWM) clocks on Renesas R-Car H3, M3-W, and M3-N
   - Add CMM (Color Management Module) clocks on Renesas R-Car M3-W
   - Add Clock Domain support on Renesas RZ/N1"

* tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (190 commits)
  clk: consoldiate the __clk_get_hw() declarations
  clk: sprd: Add check for return value of sprd_clk_regmap_init()
  clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
  clk: Add Si5341/Si5340 driver
  dt-bindings: clock: Add silabs,si5341
  clk: clk-si544: Implement small frequency change support
  clk: add BCM63XX gated clock controller driver
  devicetree: document the BCM63XX gated clock bindings
  clk: at91: sckc: use dedicated functions to unregister clock
  clk: at91: sckc: improve error path for sama5d4 sck registration
  clk: at91: sckc: remove unnecessary line
  clk: at91: sckc: improve error path for sam9x5 sck register
  clk: at91: sckc: add support to free slow clock osclillator
  clk: at91: sckc: add support to free slow rc oscillator
  clk: at91: sckc: add support to free slow oscillator
  clk: rockchip: export HDMIPHY clock on rk3228
  clk: rockchip: add watchdog pclk on rk3328
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  clk: at91: sckc: add support for SAM9X60
  ...
2019-07-17 10:07:48 -07:00
Linus Torvalds 8de262531f - Core Frameworks
- Set 'struct device' fwnode when registering a new device
 
  - New Drivers
    - Add support for ROHM BD70528 PMIC
 
  - New Device Support
    - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC
    - Add support for RK809 and RK817 to Rockchip RK808
    - Add support for Lid Angle to ChromeOS core
    - Add support for CS47L15 CODEC to Madera core
    - Add support for CS47L92 CODEC to Madera core
    - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core
    - Add support for Add Intel Elkhart Lake PCH to Intel LPSS
 
  - New Functionality
    - Provide regulator supply information when registering; madera-core
    - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic
    - Allow over-riding power button press via Device Tree; rohm-bd718x7
    - Differentiate between running processors; cros_ec_dev
 
  - Fix-ups
    - Big header file update; cros_ec_commands.h
    - Split header per-subsystem; rohm-bd718x7
    - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables
    - Trivial; sorting, coding style; intel-lpss-pci
    - Only remove Power Off functionality if set locally; rk808
    - Make use for Power Off Prepare(); rk808
    - Fix spelling mistake in header guards; stmfx
    - Properly free IDA resources
    - SPDX fixups; cs47lXX-tables, madera
    - Error path fixups; hi655x-pmic
 
  - Bug Fixes
    - Add missing break in case() statement
    - Repair undefined behaviour when not initialising variables; arizona-core, madera-core
    - Fix reference to Device Tree documentation; madera
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Merge tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "Core Frameworks:
   - Set 'struct device' fwnode when registering a new device

  New Drivers:
   - Add support for ROHM BD70528 PMIC

  New Device Support:
   - Add support for LP87561 4-Phase Regulator to TI LP87565 PMIC
   - Add support for RK809 and RK817 to Rockchip RK808
   - Add support for Lid Angle to ChromeOS core
   - Add support for CS47L15 CODEC to Madera core
   - Add support for CS47L92 CODEC to Madera core
   - Add support for ChromeOS (legacy) Accelerometers in ChromeOS core
   - Add support for Add Intel Elkhart Lake PCH to Intel LPSS

  New Functionality:
   - Provide regulator supply information when registering; madera-core
   - Additional Device Tree support; lp87565, madera, cros-ec, rohm,bd71837-pmic
   - Allow over-riding power button press via Device Tree; rohm-bd718x7
   - Differentiate between running processors; cros_ec_dev

  Fix-ups:
   - Big header file update; cros_ec_commands.h
   - Split header per-subsystem; rohm-bd718x7
   - Remove superfluous code; menelaus, cs5535-mfd, cs47lXX-tables
   - Trivial; sorting, coding style; intel-lpss-pci
   - Only remove Power Off functionality if set locally; rk808
   - Make use for Power Off Prepare(); rk808
   - Fix spelling mistake in header guards; stmfx
   - Properly free IDA resources
   - SPDX fixups; cs47lXX-tables, madera
   - Error path fixups; hi655x-pmic

  Bug Fixes:
   - Add missing break in case() statement
   - Repair undefined behaviour when not initialising variables; arizona-core, madera-core
   - Fix reference to Device Tree documentation; madera"

* tag 'mfd-next-5.3' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (45 commits)
  mfd: hi655x-pmic: Fix missing return value check for devm_regmap_init_mmio_clk
  mfd: madera: Fixup SPDX headers
  mfd: madera: Remove some unused registers and fix some defaults
  mfd: intel-lpss: Release IDA resources
  mfd: intel-lpss: Add Intel Elkhart Lake PCH PCI IDs
  mfd: cs5535-mfd: Remove ifdef OLPC noise
  mfd: stmfx: Fix macro definition spelling
  dt-bindings: mfd: Add link to ROHM BD71847 Datasheet
  MAINAINERS: Swap words in INTEL PMIC MULTIFUNCTION DEVICE DRIVERS
  mfd: cros_ec_dev: Register cros_ec_accel_legacy driver as a subdevice
  mfd: rk808: Prepare rk805 for poweroff
  mfd: rk808: Check pm_power_off pointer
  mfd: cros_ec: differentiate SCP from EC by feature bit
  dt-bindings: Add binding for cros-ec-rpmsg
  mfd: madera: Add Madera core support for CS47L92
  mfd: madera: Add Madera core support for CS47L15
  mfd: madera: Update DT bindings to add additional CODECs
  mfd: madera: Add supply mapping for MICVDD
  mfd: madera: Fix potential uninitialised use of variable
  mfd: madera: Fix bad reference to pinctrl.txt file
  ...
2019-07-15 20:18:40 -07:00
Stephen Boyd b1511f7a48 Merge branches 'clk-bcm63xx', 'clk-silabs', 'clk-lochnagar' and 'clk-rockchip' into clk-next
- Support gated clk controller on MIPS based BCM63XX SoCs
 - Small frequency support for SiLabs Si544 chips
 - Support SiLabs Si5341 and Si5340 chips

* clk-bcm63xx:
  clk: add BCM63XX gated clock controller driver
  devicetree: document the BCM63XX gated clock bindings

* clk-silabs:
  clk: Add Si5341/Si5340 driver
  dt-bindings: clock: Add silabs,si5341
  clk: clk-si544: Implement small frequency change support

* clk-lochnagar:
  clk: lochnagar: Update DT binding doc to include the primary SPDIF MCLK
  clk: lochnagar: Use new parent_data approach to register clock parents

* clk-rockchip:
  clk: rockchip: export HDMIPHY clock on rk3228
  clk: rockchip: add watchdog pclk on rk3328
  clk: rockchip: add clock id for hdmi_phy special clock on rk3228
  clk: rockchip: add clock id for watchdog pclk on rk3328
  clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
  clk: rockchip: add a type from SGRF-controlled gate clocks
  clk: rockchip: Remove 48 MHz PLL rate from rk3288
  clk: rockchip: add 1.464GHz cpu-clock rate to rk3228
  clk: rockchip: Slightly more accurate math in rockchip_mmc_get_phase()
  clk: rockchip: Don't yell about bad mmc phases when getting
  clk: rockchip: Use clk_hw_get_rate() in MMC phase calculation
2019-07-12 11:11:51 -07:00
Stephen Boyd 47c9e0cef0 Merge branches 'clk-rpi-cpufreq', 'clk-tegra', 'clk-simplify-provider.h', 'clk-sprd' and 'clk-at91' into clk-next
- Support for CPU clks on Raspberry Pi devices
 - Slow clk support for AT91 SAM9X60 SoCs

* clk-rpi-cpufreq:
  clk: raspberrypi: register platform device for raspberrypi-cpufreq
  firmware: raspberrypi: register clk device
  clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
  clk: bcm2835: remove pllb

* clk-tegra:
  clk: tegra: Do not enable PLL_RE_VCO on Tegra210
  clk: tegra: Warn if an enabled PLL is in IDDQ
  clk: tegra: Do not warn unnecessarily
  clk: tegra210: fix PLLU and PLLU_OUT1

* clk-simplify-provider.h:
  clk: consoldiate the __clk_get_hw() declarations
  clk: Unexport __clk_of_table
  clk: Remove ifdef for COMMON_CLK in clk-provider.h

* clk-sprd:
  clk: sprd: Add check for return value of sprd_clk_regmap_init()
  clk: sprd: Check error only for devm_regmap_init_mmio()
  clk: sprd: Switch from of_iomap() to devm_ioremap_resource()

* clk-at91:
  clk: at91: sckc: use dedicated functions to unregister clock
  clk: at91: sckc: improve error path for sama5d4 sck registration
  clk: at91: sckc: remove unnecessary line
  clk: at91: sckc: improve error path for sam9x5 sck register
  clk: at91: sckc: add support to free slow clock osclillator
  clk: at91: sckc: add support to free slow rc oscillator
  clk: at91: sckc: add support to free slow oscillator
  clk: at91: sckc: add support for SAM9X60
  dt-bindings: clk: at91: add bindings for SAM9X60's slow clock controller
  clk: at91: sckc: add support to specify registers bit offsets
  clk: at91: sckc: sama5d4 has no bypass support
2019-07-12 11:11:30 -07:00
Stephen Boyd a993be3724 Merge branches 'clk-debugfs', 'clk-unused', 'clk-refactor' and 'clk-qoriq' into clk-next
- Add a 'clk_parent' file in clk debugfs
 - Remove dead code in various clk drivers

* clk-debugfs:
  clk: Add clk_parent entry in debugfs

* clk-unused:
  clk: qcom: Fix -Wunused-const-variable
  clk: mmp: frac: Remove set but not used variable 'prev_rate'
  clk: ti: Remove unused functions
  clk: mediatek: mt8516: Remove unused variable

* clk-refactor:
  clk: clk-cdce706: simplify getting the adapter of a client
  clk: Simplify clk_core_can_round()

* clk-qoriq:
  clk: qoriq: add support for lx2160a
2019-07-12 11:11:16 -07:00
Stephen Boyd dfe1d3a283 Merge branches 'clk-bulk-optional', 'clk-kirkwood', 'clk-socfpga' and 'clk-docs' into clk-next
- Add a clk_bulk_get_optional() API (with devm too)
 - Support for Marvell 98DX1135 SoCs

* clk-bulk-optional:
  clk: Document some devm_clk_bulk*() APIs
  clk: Add devm_clk_bulk_get_optional() function
  clk: Add clk_bulk_get_optional() function

* clk-kirkwood:
  clk: kirkwood: Add support for MV98DX1135
  dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock

* clk-socfpga:
  clk: socfpga: stratix10: fix divider entry for the emac clocks
  clk: socfpga: stratix10: add additional clocks needed for the NAND IP

* clk-docs:
  clk: Grammar missing "and", Spelling s/statisfied/satisfied/
2019-07-12 11:11:06 -07:00
Stephen Boyd e02cb1f593 Merge branches 'clk-ti', 'clk-samsung', 'clk-imx' and 'clk-allwinner' into clk-next
* clk-ti:
  clk: ti: Use int to check return value from of_property_count_elems_of_size()
  firmware: ti_sci: extend clock identifiers from u8 to u32
  clk: keystone: sci-clk: extend clock IDs to 32 bits
  clk: keystone: sci-clk: probe clocks from DT instead of firmware
  clk: keystone: sci-clk: split out the fw clock parsing to own function
  clk: keystone: sci-clk: cut down the clock name length

* clk-samsung:
  clk: samsung: Add bus clock for GPU/G3D on Exynos4412
  clk: samsung: add new clocks for DMC for Exynos5422 SoC
  clk: samsung: add BPLL rate table for Exynos 5422 SoC
  clk: samsung: add needed IDs for DMC clocks in Exynos5420
  clk: samsung: exynos5433: Use of_clk_get_parent_count()

* clk-imx: (38 commits)
  clk: imx8mq: Keep uart clocks on during system boot
  clk: imx: Remove __init for imx_register_uart_clocks() API
  clk: imx6q: fix section mismatch warning
  clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
  clk: imx8mq: Use imx_check_clocks() API directly
  clk: imx: Remove __init for imx_check_clocks() API
  clk: imx6sll: Switch to clk_hw based API
  clk: imx7d: Switch to clk_hw based API
  clk: imx6ul: Switch to clk_hw based API
  clk: imx6sx: Switch to clk_hw based API
  clk: imx6q: Switch to clk_hw based API
  clk: imx6sl: Switch to clk_hw based API
  clk: imx: Switch wrappers to clk_hw based API
  clk: imx: clk-fixup-mux: Switch to clk_hw based API
  clk: imx: clk-fixup-div: Switch to clk_hw based API
  clk: imx: clk-gate-exclusive: Switch to clk_hw based API
  clk: imx: clk-pfd: Switch to clk_hw based API
  clk: imx: clk-pllv3: Switch to clk_hw based API
  clk: imx: clk-gate2: Switch to clk_hw based API
  clk: imx: clk-cpu: Switch to clk_hw based API
  ...

* clk-allwinner: (29 commits)
  clk: Simplify debugfs printing and add a newline
  clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: gate: Add macros for referencing local clock parents
  clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
  clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
  clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
  ...
2019-07-12 11:10:59 -07:00
Stephen Boyd 1f5d580cab Merge branches 'clk-qcom-gdsc-warn', 'clk-ingenic', 'clk-qcom-qcs404-reset', 'clk-xgene-limit' and 'clk-meson' into clk-next
* clk-qcom-gdsc-warn:
  clk: qcom: gdsc: WARN when failing to toggle

* clk-ingenic:
  MIPS: Remove dead code
  clk: ingenic: Remove unused functions
  MIPS: jz4740: PM: Let CGU driver suspend clocks and set sleep mode
  clk: ingenic: Handle setting the Low-Power Mode bit
  clk: ingenic: Add missing header in cgu.h
  clk: ingenic/jz4725b: Fix "pll half" divider not read/written properly
  clk: ingenic/jz4725b: Fix incorrect dividers for main clocks
  clk: ingenic/jz4770: Fix incorrect dividers for main clocks
  clk: ingenic/jz4740: Fix incorrect dividers for main clocks
  clk: ingenic: Add support for divider tables

* clk-qcom-qcs404-reset:
  clk: gcc-qcs404: Add PCIe resets

* clk-xgene-limit:
  clk: xgene: Don't build COMMON_CLK_XGENE by default

* clk-meson:
  clk: meson: g12a: mark fclk_div3 as critical
  clk: meson: g12a: Add support for G12B CPUB clocks
  dt-bindings: clk: meson: add g12b periph clock controller bindings
  clk: meson-g12a: add temperature sensor clocks
  dt-bindings: clk: g12a-clkc: add Temperature Sensor clock IDs
  clk: meson: meson8b: add the cts_i958 clock
  clk: meson: meson8b: add the cts_mclk_i958 clocks
  clk: meson: meson8b: add the cts_amclk clocks
  dt-bindings: clock: meson8b: add the audio clocks
  clk: meson: g12a: add controller register init
  clk: meson: eeclk: add init regs
  clk: meson: g12a: add mpll register init sequences
  clk: meson: mpll: add init callback and regs
  clk: meson: axg: spread spectrum is on mpll2
  clk: meson: gxbb: no spread spectrum on mpll0
  clk: meson: mpll: properly handle spread spectrum
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
2019-07-12 11:10:52 -07:00
Stephen Boyd b6bb2bc2fd Merge branches 'clk-pwm-duty', 'clk-bcm', 'clk-mtk', 'clk-qcom-msm8998-gpu' and 'clk-renesas' into clk-next
- Add support to get duty cycle of generic pwm clks

* clk-pwm-duty:
  clk: pwm: implement the .get_duty_cycle callback

* clk-bcm:
  clk: bcm: Allow CLK_BCM2835 for ARCH_BRCMSTB
  clk: bcm: Make BCM2835 clock drivers selectable

* clk-mtk:
  clk: mediatek: Remove MT8183 unused clock
  clk: mediatek: add audsys clock driver for MT8516
  dt-bindings: mediatek: audsys: add support for MT8516

* clk-qcom-msm8998-gpu:
  dt-bindings: clock: Document gpucc for msm8998

* clk-renesas:
  clk: renesas: cpg-mssr: Use [] to denote a flexible array member
  clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
  clk: renesas: mstp: Combine group-private and clock array allocation
  clk: renesas: div6: Combine clock-private and parent array allocation
  clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
  clk: renesas: r8a774a1: Add TMU clock
  clk: renesas: r8a77995: Add CMM clocks
  clk: renesas: r8a77990: Add CMM clocks
  clk: renesas: r8a77965: Add CMM clocks
  clk: renesas: r8a7795: Add CMM clocks
  clk: renesas: r9a06g032: Add clock domain support
  dt-bindings: clock: renesas: r9a06g032-sysctrl: Document power Domains
  clk: renesas: mstp: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Remove error messages on out-of-memory conditions
  clk: renesas: cpg-mssr: Use genpd of_node instead of local copy
  clk: renesas: r8a7796: Add CMM clocks
  clk: renesas: r8a779{5|6|65}: Add TPU clock
2019-07-12 11:10:43 -07:00
Chris Paterson 85f946ffd3 scripts/spelling.txt: add spelling fix for prohibited
Misspelling 'prohibited' is quite common in the real world, although
surprisingly not so much in the Linux Kernel.  In addition to fixing the
typo we may as well add it to the spelling checker.

Also adding the present participle (prohibiting).

Link: http://lkml.kernel.org/r/20190514153341.22540-1-chris.paterson2@renesas.com
Fixes: 5bf2fbbef5 ("clk: renesas: cpg-mssr: Add r8a77470 support")
Signed-off-by: Chris Paterson <chris.paterson2@renesas.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2019-07-12 11:05:41 -07:00
Stephen Rothwell 1df3799243 clk: consoldiate the __clk_get_hw() declarations
Without this we were getting errors like:

In file included from drivers/clk/clkdev.c:22:0:
drivers/clk/clk.h:36:23: error: static declaration of '__clk_get_hw' follows non-static declaration
include/linux/clk-provider.h:808:16: note: previous declaration of '__clk_get_hw' was here

Fixes: 59fcdce425 ("clk: Remove ifdef for COMMON_CLK in clk-provider.h")
fixes: 73e0e496af ("clkdev: Always allocate a struct clk and call __clk_get() w/ CCF")
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-07-12 11:00:14 -07:00
Lee Jones 8e23cee84c Merge branches 'ib-mfd-clk-gpio-power-regulator-rtc-5.3', 'ib-mfd-clk-regulator-rtc-5.3', 'ib-mfd-cros-5.3' and 'ib-mfd-regulator-5.3' into ibs-for-mfd-merged 2019-07-02 12:10:53 +01:00
Linus Torvalds 556e2f6020 A handful of clk driver fixes and one core framework fix
- Do a DT/firmware lookup in clk_core_get() even when the DT index is a
    nonsensical value
 
  - Fix some clk data typos in the Amlogic DT headers/code
 
  - Avoid returning junk in the TI clk driver when an invalid clk is
    looked for
 
  - Fix dividers for the emac clks on Stratix10 SoCs
 
  - Fix default HDA rates on Tegra210 to correct distorted audio
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Merge tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

Pull clk fixes from Stephen Boyd:
 "A handful of clk driver fixes and one core framework fix

   - Do a DT/firmware lookup in clk_core_get() even when the DT index is
     a nonsensical value

   - Fix some clk data typos in the Amlogic DT headers/code

   - Avoid returning junk in the TI clk driver when an invalid clk is
     looked for

   - Fix dividers for the emac clks on Stratix10 SoCs

   - Fix default HDA rates on Tegra210 to correct distorted audio"

* tag 'clk-fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux:
  clk: socfpga: stratix10: fix divider entry for the emac clocks
  clk: Do a DT parent lookup even when index < 0
  clk: tegra210: Fix default rates for HDA clocks
  clk: ti: clkctrl: Fix returning uninitialized data
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
2019-06-28 08:50:09 +08:00
Chunyan Zhang c974c48dee clk: sprd: Add check for return value of sprd_clk_regmap_init()
sprd_clk_regmap_init() doesn't always return success, adding check
for its return value should make the code more strong.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
[sboyd@kernel.org: Add a missing int ret]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 15:08:29 -07:00
Mike Looijmans 3044a860fd clk: Add Si5341/Si5340 driver
Adds a driver for the Si5341 and Si5340 chips. The driver does not fully
support all features of these chips, but allows the chip to be used
without any support from the "clockbuilder pro" software.

If the chip is preprogrammed, that is, you bought one with some defaults
burned in, or you programmed the NVM in some way, the driver will just
take over the current settings and only change them on demand. Otherwise
the input must be a fixed XTAL in its most basic configuration (no
predividers, no feedback, etc.).

The driver supports dynamic changes of multisynth, output dividers and
enabling or powering down outputs and multisynths.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
[sboyd@kernel.org: Mark some things static, use BIT_ULL for big bits and
ULL for big constants]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 14:06:47 -07:00
Mike Looijmans dc59c13375 clk: clk-si544: Implement small frequency change support
The Si544 supports changing frequencies "on the fly" when the change is
less than 950 ppm from the current center frequency. The driver now
uses the small adjustment routine for implementing this.

Signed-off-by: Mike Looijmans <mike.looijmans@topic.nl>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 13:45:38 -07:00
Jonas Gorski 1c099779c1 clk: add BCM63XX gated clock controller driver
Add a driver for the gated clock controller found on MIPS based BCM63XX
SoCs.

Signed-off-by: Jonas Gorski <jonas.gorski@gmail.com>
Reviewed-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Philippe Mathieu-Daudé <f4bug@amsat.org>
[sboyd@kernel.org: Remove module.h include and associated things for a
non-modular driver, add static on data tables, drop of_match_ptr()
usage, fix spdx tag to be a C++ style comment]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 13:41:41 -07:00
Claudiu Beznea ecbcc2aa65 clk: at91: sckc: use dedicated functions to unregister clock
Use at91 specific functions to free all resources in case of error.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:21 -07:00
Claudiu Beznea d09e6ca138 clk: at91: sckc: improve error path for sama5d4 sck registration
Improve error path for sama5d4 sck registration.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:20 -07:00
Claudiu Beznea 8c938c2d00 clk: at91: sckc: remove unnecessary line
Remove unnecessary line.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:20 -07:00
Claudiu Beznea 82e25dc8f6 clk: at91: sckc: improve error path for sam9x5 sck register
Improve error path for sam9x5 slow clock registration.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:19 -07:00
Claudiu Beznea 016d22dd10 clk: at91: sckc: add support to free slow clock osclillator
Add support to free slow clock oscillator resources.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:18 -07:00
Claudiu Beznea 036702468c clk: at91: sckc: add support to free slow rc oscillator
Add support to free slow rc oscillator resources.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:17 -07:00
Claudiu Beznea 7fb791d079 clk: at91: sckc: add support to free slow oscillator
Add support to free slow oscillator resources.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Reviewed-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-27 11:18:16 -07:00
Tony Xie 8ed1440197 clk: RK808: Add RK809 and RK817 support.
RK809 and RK817 are power management IC chips for multimedia products.
most of their functions and registers are same, including the clkout
funciton.

Signed-off-by: Tony Xie <tony.xie@rock-chips.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27 14:57:59 +01:00
Matti Vaittinen 0dae7f5857 clk: bd718x7: Support ROHM BD70528 clk block
ROHM BD70528 is an ultra low power PMIC with similar 32K clk as
bd718x7. Only difference (from clk perspective) is register address.
Add support for controlling BD70528 clk using bd718x7 driver.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27 10:57:24 +01:00
Matti Vaittinen 2a6a7aacd4 mfd: regulator: clk: Split rohm-bd718x7.h
Split the bd718x7.h to ROHM common and bd718x7 specific parts
so that we do not need to add same things in every new ROHM
PMIC header. Please note that this change requires changes also
in bd718x7 sub-device drivers for regulators and clk.

Signed-off-by: Matti Vaittinen <matti.vaittinen@fi.rohmeurope.com>
Acked-by: Mark Brown <broonie@kernel.org>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2019-06-27 10:56:27 +01:00
Heiko Stuebner 794e94ca83 clk: rockchip: export HDMIPHY clock on rk3228
Export the hdmiphy clock mux via the newly added clock-id.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Justin Swartz <justin.swartz@risingedge.co.za>
2019-06-27 11:02:28 +02:00
Heiko Stuebner d59fca075c clk: rockchip: add watchdog pclk on rk3328
The watchdog pclk is controlled from the secure GRF but we still
want to mention it explicitly to not use arbitary parent clocks
in the devicetree wdt node, so add a SGRF_GATE for it.

Suggested-by: Leonidas P. Papadakos <papadakospan@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-27 11:02:17 +02:00
Claudiu Beznea 04bcc4275e clk: at91: sckc: add support for SAM9X60
Add support for SAM9X60's slow clock.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:33:55 -07:00
Claudiu Beznea abaceffc88 clk: at91: sckc: add support to specify registers bit offsets
Different IPs uses different bit offsets in registers for the same
functionality, thus adapt the driver to support this.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:32:53 -07:00
Claudiu Beznea 5cf6d876a7 clk: at91: sckc: sama5d4 has no bypass support
The slow clock of SAMA5D4 has no bypass support thus remove it.

Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Acked-by: Alexandre Belloni <alexandre.belloni@bootlin.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:32:11 -07:00
Chunyan Zhang 78f5296951 clk: sprd: Check error only for devm_regmap_init_mmio()
The function devm_regmap_init_mmio() wouldn't return NULL pointer for
now, so only need to ensure the return value is not an error code.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:15:08 -07:00
Chunyan Zhang 69b39d2503 clk: sprd: Switch from of_iomap() to devm_ioremap_resource()
devm_ioremap_resources() automatically requests resources and devm_ wrappers
do better error handling and unmapping of the I/O region when needed,
that would make drivers more clean and simple.

Signed-off-by: Chunyan Zhang <zhang.chunyan@linaro.org>
Reviewed-by: Baolin Wang <baolin.wang@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-26 11:12:50 -07:00
Charles Keepax 055ca54777 clk: lochnagar: Use new parent_data approach to register clock parents
Switch over to the more modern style of registering parents and simplify
the code in the process.

Suggested-by: Stephen Boyd <sboyd@kernel.org>
Signed-off-by: Charles Keepax <ckeepax@opensource.cirrus.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:29:03 -07:00
Thierry Reding e3527dca15 clk: tegra: Do not enable PLL_RE_VCO on Tegra210
It turns out that this PLL is not used on Tegra210, so there's no need
to enable it via the init table. Remove the init table entry for this
PLL to avoid it getting enabled at boot time. If the bootloader enabled
it and forgot to turn it off, the common clock framework will now know
to disable it because it is unused.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:12:55 -07:00
Thierry Reding c1139d2083 clk: tegra: Warn if an enabled PLL is in IDDQ
A PLL in IDDQ doesn't work, whether it's enabled or not. This is not a
configuration that makes sense, so warn about it.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:10:28 -07:00
Thierry Reding 2067507012 clk: tegra: Do not warn unnecessarily
There is no need to warn if the reference PLL is enabled with the
correct defaults. Only warn if the boot values don't match the defaults.

Signed-off-by: Thierry Reding <treding@nvidia.com>
Acked-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:10:21 -07:00
JC Kuo 0d34dfbf30 clk: tegra210: fix PLLU and PLLU_OUT1
Full-speed and low-speed USB devices do not work with Tegra210
platforms because of incorrect PLLU/PLLU_OUT1 clock settings.

When full-speed device is connected:
[   14.059886] usb 1-3: new full-speed USB device number 2 using tegra-xusb
[   14.196295] usb 1-3: device descriptor read/64, error -71
[   14.436311] usb 1-3: device descriptor read/64, error -71
[   14.675749] usb 1-3: new full-speed USB device number 3 using tegra-xusb
[   14.812335] usb 1-3: device descriptor read/64, error -71
[   15.052316] usb 1-3: device descriptor read/64, error -71
[   15.164799] usb usb1-port3: attempt power cycle

When low-speed device is connected:
[   37.610949] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[   38.557376] usb usb1-port3: Cannot enable. Maybe the USB cable is bad?
[   38.564977] usb usb1-port3: attempt power cycle

This commit fixes the issue by:
 1. initializing PLLU_OUT1 before initializing XUSB_FS_SRC clock
    because PLLU_OUT1 is parent of XUSB_FS_SRC.
 2. changing PLLU post-divider to /2 (DIVP=1) according to Technical
    Reference Manual.

Fixes: e745f992cf ("clk: tegra: Rework pll_u")
Signed-off-by: JC Kuo <jckuo@nvidia.com>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:08:23 -07:00
Nicolas Saenz Julienne e2bb18347c clk: raspberrypi: register platform device for raspberrypi-cpufreq
As 'clk-raspberrypi' depends on RPi's firmware interface, which might be
configured as a module, the cpu clock might not be available for the
cpufreq driver during it's init process. So we register the
'raspberrypi-cpufreq' platform device after the probe sequence succeeds.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:04:28 -07:00
Nicolas Saenz Julienne 4e85e535e6 clk: bcm283x: add driver interfacing with Raspberry Pi's firmware
Raspberry Pi's firmware offers an interface though which update it's
clock's frequencies. This is specially useful in order to change the CPU
clock (pllb_arm) which is 'owned' by the firmware and we're unable to
scale using the register interface provided by clk-bcm2835.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:04:23 -07:00
Nicolas Saenz Julienne 2256d89333 clk: bcm2835: remove pllb
Raspberry Pi's firmware controls this pll, we should use the firmware
interface to access it.

Signed-off-by: Nicolas Saenz Julienne <nsaenzjulienne@suse.de>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 16:04:15 -07:00
Vabhav Sharma 78a5ba8f91 clk: qoriq: add support for lx2160a
Add clockgen support and configuration for NXP SoC lx2160a
with compatible property as "fsl,lx2160a-clockgen".

Signed-off-by: Tang Yuantian <andy.tang@nxp.com>
Signed-off-by: Yogesh Gaur <yogeshnarayan.gaur@nxp.com>
Signed-off-by: Vabhav Sharma <vabhav.sharma@nxp.com>
Acked-by: Scott Wood <oss@buserror.net>
Acked-by: Stephen Boyd <sboyd@kernel.org>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:58:18 -07:00
Wolfram Sang df095f996b clk: clk-cdce706: simplify getting the adapter of a client
We have a dedicated pointer for that, so use it. Much easier to read and
less computation involved.

Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:55:39 -07:00
Nathan Huckleberry da642427bd clk: qcom: Fix -Wunused-const-variable
Clang produces the following warning

drivers/clk/qcom/gcc-msm8996.c:133:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map' [-Wunused-const-variable]
static const struct
parent_map gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div_map[] =
{ ^drivers/clk/qcom/gcc-msm8996.c:141:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div' [-Wunused-const-variable] static
const char * const gcc_xo_gpll0_gpll2_gpll3_gpll0_early_div[] = { ^
drivers/clk/qcom/gcc-msm8996.c:187:32: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map'
[-Wunused-const-variable] static const struct parent_map
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div_map[] = { ^
drivers/clk/qcom/gcc-msm8996.c:197:27: warning: unused variable
'gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div'
[-Wunused-const-variable] static const char * const
gcc_xo_gpll0_gpll2_gpll3_gpll1_gpll4_gpll0_early_div[] = {

It looks like these were never used.

Fixes: b1e010c073 ("clk: qcom: Add MSM8996 Global Clock Control (GCC) driver")
Cc: clang-built-linux@googlegroups.com
Link: https://github.com/ClangBuiltLinux/linux/issues/518
Suggested-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Nathan Huckleberry <nhuck@google.com>
Reviewed-by: Nathan Chancellor <natechancellor@gmail.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:49:38 -07:00
Paul Cercueil 9a838844a0 clk: ingenic: Remove unused functions
These functions are not called anywhere anymore, they can safely be
removed.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:43:39 -07:00
Paul Cercueil 2ee93e3c95 clk: ingenic: Handle setting the Low-Power Mode bit
The Low-Power Mode, when enabled, will make the "wait" MIPS instruction
suspend the system.

This is not really clock-related, but this bit happens to be in the
register set of the CGU.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:43:15 -07:00
Paul Cercueil dbc38ad0e7 clk: ingenic: Add missing header in cgu.h
The cgu.h has structures that contain 'clk_onecell_data' and 'clk_hw'
structures (no pointers), so the <linux/clk-provider.h> header should be
included.

Signed-off-by: Paul Cercueil <paul@crapouillou.net>
[sboyd@kernel.org: Drop removal of includes in drivers]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 15:41:48 -07:00
Leonard Crestez e5e89247a7 clk: Add clk_parent entry in debugfs
This allows to easily determine the parent in shell scripts without
parsing more complex files.

Add the clk_parent file for all clks which can have a parent, not just
muxes. This way it can be used to determine the clk tree structure
without parsing more complex files.

Signed-off-by: Leonard Crestez <leonard.crestez@nxp.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:53:10 -07:00
Geert Uytterhoeven 65e2218d10 clk: Grammar missing "and", Spelling s/statisfied/satisfied/
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:51:35 -07:00
Geert Uytterhoeven eef1f1b6cf clk: Simplify clk_core_can_round()
A boolean expression already evaluates to true or false, so there is no
need to check the result and return true or false explicitly.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Jerome Brunet <jbrunet@baylibre.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:50:45 -07:00
Dinh Nguyen 16e3c572cd clk: socfpga: stratix10: fix divider entry for the emac clocks
The fixed dividers for the emac clocks should be 2 not 4.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:39:51 -07:00
Dinh Nguyen 3b5015c4d8 clk: socfpga: stratix10: add additional clocks needed for the NAND IP
The nand_clk is actually called the nand_x_clk and the parent is the
l4_mp_clk, not the l4_main_clk. The nand_clk is a child of the
nand_x_clk and has a fixed divider of 4. The same is true for the
nand_ecc_clk.

Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:36:56 -07:00
Chris Packham 88aa7af9c1 clk: kirkwood: Add support for MV98DX1135
The 98DX1135 is a switch chip with an integrated CPU. This is similar to
the 98DX4122 except that the core clock speed is fixed to 166Mhz.

Signed-off-by: Chris Packham <chris.packham@alliedtelesis.co.nz>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:35:21 -07:00
Sylwester Nawrocki 9bd5ef0bd8 clk: Add devm_clk_bulk_get_optional() function
Add managed version of the clk_bulk_get_optional() helper function.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
[sboyd@kernel.org: Mark __devm_clk_bulk_get() static]
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:28:01 -07:00
Sylwester Nawrocki 2f25528e4e clk: Add clk_bulk_get_optional() function
clk_bulk_get_optional() allows to get a group of clocks where one
or more is optional.  For a not available clock, e.g. not specifed
in the clock consumer node in DT, its respective struct clk pointer
will be NULL.  This allows for operating on a group of returned
clocks (struct clk_bulk_data array) with existing clk_bulk* APIs.

Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 14:28:01 -07:00
Dinh Nguyen 74684cce5e clk: socfpga: stratix10: fix divider entry for the emac clocks
The fixed dividers for the emac clocks should be 2 not 4.

Cc: stable@vger.kernel.org
Signed-off-by: Dinh Nguyen <dinguyen@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 13:40:05 -07:00
Stephen Boyd 11f6c2307c clk: Simplify debugfs printing and add a newline
The possible parent printing function duplicates a bunch of if
conditions. Pull that into another function so we can print an extra
character at the end, either a space or a newline. This way we can add
the required newline that got lost here and also shorten the code.

Fixes: 2d156b78ce ("clk: Fix debugfs clk_possible_parents for clks without parent string names")
Cc: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-25 11:56:04 -07:00
Stephen Boyd f925a054f0 Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2
The first part of ongoing work to convert the sunxi-ng clk driver from
 using global clock name strings to describe clk parenting, to having
 direct struct clk_hw pointers, or local names based on clock-names from
 the device tree binding.
 
 This is based on Stephen Boyd's recent work allowing clk drivers to
 specify clk parents using struct clk_hw * or parsing DT phandles in the
 clk node.
 
 This series can be split into a few major parts:
 
 1) The first patch is a small fix for clk debugfs representation.
 
 2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
    situations I encountered, or assume I will encounter, such as single
    internal (struct clk_hw *) parent, single DT (struct clk_parent_data
    .fw_name), multiple internal parents, and multiple mixed (internal +
    DT) parents. A special variant for just an internal single parent is
    added, CLK_HW_INIT_HWS, which lets the driver share the singular
    list, instead of having the compiler create a compound literal every
    time. It might even make sense to only keep this variant.
 
 3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
    is the same as the single parent CLK_HW_INIT_* helpers.
 
 4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
    either struct clk_hw * or DT .fw_name types, whichever the hardware
    requires.
 
 5) The beginning of SUNXI_CCU_GATE conversion to local parent
    references. This part is not done. They are included as justification
    and examples for the shared list of clk parents case.
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Merge tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux into clk-allwinner

Pull Allwinner sunxi-ng clk driver parent relation rewrite part 1 - take 2
from Chen-Yu Tsai:

"The first part of ongoing work to convert the sunxi-ng clk driver from
using global clock name strings to describe clk parenting, to having
direct struct clk_hw pointers, or local names based on clock-names from
the device tree binding.

This is based on Stephen Boyd's recent work allowing clk drivers to
specify clk parents using struct clk_hw * or parsing DT phandles in the
clk node.

This series can be split into a few major parts:

1) The first patch is a small fix for clk debugfs representation.

2) A bunch of CLK_HW_INIT_* helper macros are added. These cover the
   situations I encountered, or assume I will encounter, such as single
   internal (struct clk_hw *) parent, single DT (struct clk_parent_data
   .fw_name), multiple internal parents, and multiple mixed (internal +
   DT) parents. A special variant for just an internal single parent is
   added, CLK_HW_INIT_HWS, which lets the driver share the singular
   list, instead of having the compiler create a compound literal every
   time. It might even make sense to only keep this variant.

3) A bunch of CLK_FIXED_FACTOR_* helper macros are added. The rationale
   is the same as the single parent CLK_HW_INIT_* helpers.

4) Bulk conversion of CLK_FIXED_FACTOR to use local parent references,
   either struct clk_hw * or DT .fw_name types, whichever the hardware
   requires.

5) The beginning of SUNXI_CCU_GATE conversion to local parent
   references. This part is not done. They are included as justification
   and examples for the shared list of clk parents case."

* tag 'sunxi-ng-parent-rewrite-part-1-take-2' of https://git.kernel.org/pub/scm/linux/kernel/git/sunxi/linux: (25 commits)
  clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
  clk: sunxi-ng: gate: Add macros for referencing local clock parents
  clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
  clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
  clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
  clk: fixed-factor: Add CLK_FIXED_FACTOR_FW_NAME for DT clock-names parent
  clk: fixed-factor: Add CLK_FIXED_FACTOR_HWS which takes list of struct clk_hw *
  ...
2019-06-24 18:28:31 -07:00
Anson Huang 15c64ff762 clk: imx8mq: Keep uart clocks on during system boot
Call imx_register_uart_clocks() API to keep uart clocks enabled
when earlyprintk or earlycon is active.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-24 09:43:40 +08:00
Anson Huang e5190586a9 clk: imx: Remove __init for imx_register_uart_clocks() API
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_register_uart_clocks() API, so
imx_register_uart_clocks() API should NOT be in .init section.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-24 09:43:29 +08:00
Chen-Yu Tsai 89f27fb2dd clk: sunxi-ng: sun8i-r: Use local parent references for SUNXI_CCU_GATE
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.

Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_HWS
as the parent clock is internal to this clock unit.

To avoid duplication of clock definitions, we fix up the parent
reference for A83T in the A83T init function.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai 4b88915184 clk: sunxi-ng: a80-usb: Use local parent references for SUNXI_CCU_GATE
With the new clk parenting code and SUNXI_CCU_GATE macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.

Convert existing SUNXI_CCU_GATE definitions to SUNXI_CCU_GATE_DATA to
specify the parent clock.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai 4b751ffae7 clk: sunxi-ng: gate: Add macros for referencing local clock parents
With the new clk parenting code, clk_init_data was expanded to include
.parent_hws, for clk drivers to directly reference parents by clk_hw,
and .parent_data, for clk drivers to specify parents using a combination
of device tree clock-names, pointers to struct clk_hw, device tree clocks,
and/or fallback global clock names.

Add four new macros:

  - SUNXI_CCU_GATE_HW, that can take a struct clk_hw pointer, instead
    of a string, as its parent.

  - SUNXI_CCU_GATE_FW that takes a string to match a clock-names entry
    in the device tree to specify the clock parent.

  - SUNXI_CCU_GATE_HWS that takes an array of struct clk_hw * as its
    parent. This allows the array to be shared with other clk
    declarations.

  - SUNXI_CCU_GATE_DATA that takes an array of struct clk_parent_data *
    as its parent. This allows the array to be shared with other clk
    declarations.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai 22ce173f76 clk: sunxi-ng: h6-r: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai 8916d3fc3a clk: sunxi-ng: h6: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

A forward declaration for struct clk_fixed_factor pll_periph0_4x_clk
is added as the definitions of the fixed factor clocks appear much later
in the file. The position of fixed factor clock definitions will be
moved for all drivers at a later time, before the conversion of all
other clock types.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai ecd73c04b3 clk: sunxi-ng: a64: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Chen-Yu Tsai 4d34497ee4 clk: sunxi-ng: f1c100s: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-22 10:13:16 +08:00
Geert Uytterhoeven ec2b827be3 clk: renesas: cpg-mssr: Use [] to denote a flexible array member
Flexible array members should be denoted using [] instead of [0], else
gcc will not warn when they are no longer at the end of the structure.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20 11:37:16 +02:00
Geert Uytterhoeven 8f5e20b6b8 clk: renesas: cpg-mssr: Combine driver-private and clock array allocation
Make cpg_mssr_priv.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the driver-private
structure and array of available clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20 11:37:00 +02:00
Geert Uytterhoeven a79f5836bd clk: renesas: mstp: Combine group-private and clock array allocation
Make mstp_clock_group.clks[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the group-private
structure and array of module clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20 11:36:44 +02:00
Geert Uytterhoeven ba0386111c clk: renesas: div6: Combine clock-private and parent array allocation
Make div6_clock.parents[] a flexible array member, and use the new
struct_size() helper, to combine the allocation of the clock-private
structure and array of parent clocks.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20 11:36:29 +02:00
Geert Uytterhoeven d2e4cb45af clk: renesas: cpg-mssr: Update kerneldoc for struct cpg_mssr_priv
New fields were added, but kerneldoc was forgotten, or inserted at the
wrong place.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
2019-06-20 11:36:16 +02:00
Thomas Gleixner d2912cb15b treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 500
Based on 2 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation #

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 4122 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Kate Stewart <kstewart@linuxfoundation.org>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081206.933168790@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:55 +02:00
Thomas Gleixner acee2e8d66 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 460
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation http www opensource org
  licenses gpl license html http www gnu org copyleft gpl html

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 3 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081201.897982733@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:09 +02:00
Thomas Gleixner cb849fc5f0 treewide: Replace GPLv2 boilerplate/reference with SPDX - rule 459
Based on 1 normalized pattern(s):

  this program is free software you can redistribute it and or modify
  it under the terms of the gnu general public license version 2 as
  published by the free software foundation the gpl this program is
  distributed in the hope that it will be useful but without any
  warranty without even the implied warranty of merchantability or
  fitness for a particular purpose see the gnu general public license
  version 2 gplv2 for more details you should have received a copy of
  the gnu general public license version 2 gplv2 along with this
  source code

extracted by the scancode license scanner the SPDX license identifier

  GPL-2.0-only

has been chosen to replace the boilerplate/reference in 16 file(s).

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Enrico Weigelt <info@metux.net>
Reviewed-by: Allison Randal <allison@lohutok.net>
Cc: linux-spdx@vger.kernel.org
Link: https://lkml.kernel.org/r/20190604081201.771169395@linutronix.de
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
2019-06-19 17:09:09 +02:00
Krzysztof Kozlowski 7ef91224c4 clk: samsung: Add bus clock for GPU/G3D on Exynos4412
Add ID and gate for bus clock for GPU (Mali 400) on Exynos4412.

Signed-off-by: Krzysztof Kozlowski <krzk@kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2019-06-19 10:50:51 +02:00
Arnd Bergmann 0e12248c68 clk: imx6q: fix section mismatch warning
The imx6q_obtain_fixed_clk_hw lacks an __init marker, which
leads to this otherwise harmless warning:

WARNING: vmlinux.o(.text+0x495358): Section mismatch in reference from the function imx6q_obtain_fixed_clk_hw() to the function .init.text:imx_obtain_fixed_clock_hw()
The function imx6q_obtain_fixed_clk_hw() references
the function __init imx_obtain_fixed_clock_hw().
This is often because imx6q_obtain_fixed_clk_hw lacks a __init
annotation or the annotation of imx_obtain_fixed_clock_hw is wrong.

Fixes: 992b703b5b ("clk: imx6q: Switch to clk_hw based API")
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18 21:17:07 +08:00
Chen-Yu Tsai 45d0706ebf clk: sunxi-ng: sun8i-r: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:03 +08:00
Chen-Yu Tsai 707f601373 clk: sunxi-ng: v3s: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:03 +08:00
Chen-Yu Tsai 3fccf2ed6f clk: sunxi-ng: r40: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:03 +08:00
Chen-Yu Tsai b28e3eb632 clk: sunxi-ng: h3: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:02 +08:00
Chen-Yu Tsai cdaf8388ea clk: sunxi-ng: a33: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:01 +08:00
Chen-Yu Tsai 7a40e3d869 clk: sunxi-ng: a23: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:01 +08:00
Chen-Yu Tsai 8b1dd564b9 clk: sunxi-ng: a31: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:01 +08:00
Chen-Yu Tsai 260311bfb3 clk: sunxi-ng: sun5i: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:01 +08:00
Chen-Yu Tsai d1c924732b clk: sunxi-ng: a10: Use local parent references for CLK_FIXED_FACTOR
With the new clk parenting code and CLK_FIXED_FACTOR_{HW,FW_NAME}
macros, we can reference parents locally via pointers to struct clk_hw
or DT clock-names.

Convert existing CLK_FIXED_FACTOR definitions to either the _HW or
_FW_NAME variant based on whether the parent clock is internal or
external to the CCU.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:00 +08:00
Chen-Yu Tsai 6873d20726 clk: sunxi-ng: sun8i-r: Use local parent references for CLK_HW_INIT_*
With the new clk parenting code and CLK_HW_INIT_* macros, we can
reference parents locally via pointers to struct clk_hw or DT
clock-names.

Convert existing CLK_HW_INIT_* definitions to describe parents using
either struct clk_hw pointers or clock-names from the device tree
binding.

For the AR100, this also allows us to merge the generic AR100 and the
A83T specific one, which only differed in the global clock names for
their parent clocks. The device tree bindings used the same name
specifiers.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:00 +08:00
Chen-Yu Tsai 9309448335 clk: sunxi-ng: switch to of_clk_hw_register() for registering clks
Commit 89a5ddcc79 ("clk: Add of_clk_hw_register() API for early clk
drivers") introduces a new API for registering clks, which allows the
user to directly specify a device node, even if there is no struct
device attached to it. The device node is used for local DT clock-names
matching.

Switch to of_clk_hw_register() so that local DT clock-names matching
works.

Acked-by: Maxime Ripard <maxime.ripard@bootlin.com>
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:39:00 +08:00
Chen-Yu Tsai 2d156b78ce clk: Fix debugfs clk_possible_parents for clks without parent string names
Following the commit fc0c209c14 ("clk: Allow parents to be specified
without string names"), the parent name string is not always populated.

Instead, fetch the parents clk_core struct using the appropriate helper,
and read its name directly. If that fails, go through the possible
sources of parent names. The order in which they are used is different
from how parents are looked up, with the global name having precedence
over local fw_name and indices. This makes more sense as a) the
parent_maps structure does not differentiate between legacy global names
and fallback global names, and b) global names likely provide more
information than local fw_names.

Fixes: fc0c209c14 ("clk: Allow parents to be specified without string names")
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
2019-06-18 19:38:59 +08:00
Fabrizio Castro c1324171a9 clk: renesas: r8a774a1: Add TMU clock
This patch adds the TMU clocks to the R8A774A1 SoC.

Signed-off-by: Fabrizio Castro <fabrizio.castro@bp.renesas.com>
Reviewed-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18 11:02:51 +02:00
Jacopo Mondi fa59290e3d clk: renesas: r8a77995: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car D3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18 11:03:03 +02:00
Jacopo Mondi 08911c4a8e clk: renesas: r8a77990: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car E3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18 11:02:56 +02:00
Jacopo Mondi 140444003c clk: renesas: r8a77965: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car M3-N.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18 11:02:54 +02:00
Jacopo Mondi 00c7cd3f13 clk: renesas: r8a7795: Add CMM clocks
Add clock definitions for CMM units on Renesas R-Car H3.

Signed-off-by: Jacopo Mondi <jacopo+renesas@jmondi.org>
Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2019-06-18 11:02:51 +02:00
Anson Huang 1aa6af5f18 clk: imx8mq: Use devm_platform_ioremap_resource() instead of of_iomap()
i.MX8MQ clock driver uses platform driver model, better to use
devm_platform_ioremap_resource() instead of of_iomap() to get
IO base.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18 14:52:08 +08:00
Anson Huang 883cd3c962 clk: imx8mq: Use imx_check_clocks() API directly
Use imx_check_clocks() API to check clocks directly.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18 14:51:01 +08:00
Anson Huang c63fe28bf1 clk: imx: Remove __init for imx_check_clocks() API
Some of i.MX SoCs' clock driver use platform driver model,
and they need to call imx_check_clocks() API, so
imx_check_clocks() API should NOT be in .init section.

Signed-off-by: Anson Huang <Anson.Huang@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2019-06-18 14:50:47 +08:00
Stephen Boyd c8edb316b9 clk: Do a DT parent lookup even when index < 0
We want to allow the parent lookup to happen even if the index is some
value less than 0. This may be the case if a clk provider only specifies
the .name member to match a string in the "clock-names" DT property. We
shouldn't require that the index be >= 0 to make this use case work.

Fixes: 601b6e9330 ("clk: Allow parents to be specified via clkspec index")
Reported-by: Alexandre Mergnat <amergnat@baylibre.com>
Cc: Jerome Brunet <jbrunet@baylibre.com>
Cc: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-17 07:13:54 -07:00
Heiko Stuebner e4488e45e2 clk: rockchip: convert pclk_wdt boilerplat to new SGRF_GATE macro
Convert the boilerplate code for manual addition of the watchdog clock
to the new SGRF_GATE macro for all affected socs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-15 15:54:24 +02:00
Jon Hunter 9caec6620f clk: tegra210: Fix default rates for HDA clocks
Currently the default clock rates for the HDA and HDA2CODEC_2X clocks
are both 19.2MHz. However, the default rates for these clocks should
actually be 51MHz and 48MHz, respectively. The current clock settings
results in a distorted output during audio playback. Correct the default
clock rates for these clocks by specifying them in the clock init table
for Tegra210.

Cc: stable@vger.kernel.org
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-14 10:43:38 -07:00
Heiko Stuebner b3b723d8c4 clk: rockchip: add a type from SGRF-controlled gate clocks
Some clk gates on Rockchip SoCs are part of the SGRF (secure general
register files) and thus only controllable from secure mode, with the
most prominent example being the watchdog.

In most cases we still want to define this as a real clock though,
to have complete clock tree and not reference the generic base-clock
from the devicetree.

So far we've just defined this as factor-1-1 clocks in the clock init,
so define a special clock-type for it so that this definition can be
part of the general tree-definition and save some boilerplate code.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2019-06-14 18:56:07 +02:00
Stephen Boyd f18d43046a MPLL50M DT bindings typo fix
Meson9 VPU typo fixes
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Merge tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson into clk-fixes

Pull Meson clk driver fixes from Jerome Brunet:

 - MPLL50M DT bindings typo fix
 - Meson9 VPU typo fixes

* tag 'clk-meson-5.2-1-fixes' of https://github.com/BayLibre/clk-meson:
  clk: meson: meson8b: fix a typo in the VPU parent names array variable
  clk: meson: fix MPLL 50M binding id typo
2019-06-12 15:58:11 -07:00
Marc Gonzalez ce9a104643 clk: xgene: Don't build COMMON_CLK_XGENE by default
Building COMMON_CLK_XGENE is pointless, unless we're building for
an XGENE system.

Signed-off-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-12 08:45:31 -07:00
Neil Armstrong eda91833f0 clk: meson: g12a: mark fclk_div3 as critical
On Amlogic Meson G12b platform, the fclk_div3 seems to be necessary for
the system to operate correctly.

Disabling it cause the entire system to freeze, including peripherals.

Let's mark this clock as critical, fixing boot on G12b platforms.

Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11 11:28:44 +02:00
Neil Armstrong d43628e9bc clk: meson: g12a: Add support for G12B CPUB clocks
Update the Meson G12A Clock driver to support the Amlogic G12B SoC.

G12B clock driver is very close, the main differences are :
- the clock tree is duplicated for the both clusters, and the
  SYS_PLL are swapped between the clusters
- G12B has additional clocks like for CSI an other components

Here only the cpu clock tree is handled.

Reviewed-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Neil Armstrong <narmstrong@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11 11:27:43 +02:00
Guillaume La Roque ad517d5298 clk: meson-g12a: add temperature sensor clocks
Add the TS clocks used by two temperature sensors

Reviewed-by: Martin Blumenstingl<martin.blumenstingl@googlemail.com>
Signed-off-by: Guillaume La Roque <glaroque@baylibre.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com> [fixed commit description]
2019-06-11 11:23:21 +02:00
Martin Blumenstingl 174806aa9a clk: meson: meson8b: add the cts_i958 clock
Add the cts_i958 clock to control the clock source of the spdif output
block. It is used to select whether the clock source of the spdif output
is cts_amclk (when data are taken from i2s buffer) or the cts_mclk_i958
(when data are taken from the spdif buffer). The setup for this clock is
identical to GXBB, so this ports commit 7eaa44f620 ("clk: meson:
gxbb: add cts_i958 clock") to the Meson8/Meson8b/Meson8m2 clock driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11 11:02:04 +02:00
Martin Blumenstingl c39c24c1ca clk: meson: meson8b: add the cts_mclk_i958 clocks
Add the SPDIF master clock also referred as cts_mclk_i958. The setup for
this clock is identical to GXBB, so this ports commit 3c277c247e
("clk: meson: gxbb: add cts_mclk_i958") to the Meson8/Meson8b/Meson8m2
clock driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11 11:02:04 +02:00
Martin Blumenstingl f278f05e74 clk: meson: meson8b: add the cts_amclk clocks
Add the I2S master clock also referred as cts_amclk. The setup for this
clock is identical to GXBB, so this ports commit 4087bd4b21 ("clk:
meson: gxbb: add cts_amclk") to the Meson8/Meson8b/Meson8m2 clock
driver.

Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
2019-06-11 11:02:04 +02:00
Bjorn Andersson e5bbbff5b7 clk: gcc-qcs404: Add PCIe resets
Enabling PCIe requires several of the PCIe related resets from GCC, so
add them all.

Reviewed-by: Niklas Cassel <niklas.cassel@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Vinod Koul <vkoul@kernel.org>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07 14:30:33 -07:00
Bjorn Andersson f02fba3aa8 clk: qcom: gdsc: WARN when failing to toggle
Failing to toggle a GDSC as the driver core is attaching the
power-domain to a device will cause a silent probe deferral. Provide an
explicit warning to the developer, in order to reduce the amount of time
it takes to debug this.

Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Reviewed-by: Jeffrey Hugo <jhugo@codeaurora.org>
Tested-by: Jeffrey Hugo <jhugo@codeaurora.org>
Reviewed-by: Marc Gonzalez <marc.w.gonzalez@free.fr>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07 13:19:30 -07:00
YueHaibing be41141127 clk: mmp: frac: Remove set but not used variable 'prev_rate'
Fixes gcc '-Wunused-but-set-variable' warning:

drivers/clk/mmp/clk-frac.c: In function clk_factor_set_rate:
drivers/clk/mmp/clk-frac.c:81:16: warning: variable prev_rate set but not used [-Wunused-but-set-variable]

It's never used and can be removed.

Signed-off-by: YueHaibing <yuehaibing@huawei.com>
Signed-off-by: Stephen Boyd <sboyd@kernel.org>
2019-06-07 11:54:48 -07:00