Commit Graph

1979 Commits

Author SHA1 Message Date
Chanwoo Choi 5785d6e61f clk: samsung: exynos5433: Add clocks for CMU_BUS{0|1|2} domains
This patch adds the mux/divider/gate clocks for CMU_BUS{0|1|2} domains
which contain global data buses clocked at up the 400MHz. These blocks
transfer data between DRAM and various sub-blocks. These clock domains
also contain global peripheral buses clocked at 67/111/200/222/266/333/400
MHz and used for register accesses.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:13 +01:00
Chanwoo Choi 2e997c0359 clk: samsung: exynos5433: Add clocks for CMU_AUD domain
This patch adds the mux/divider/gate clocks for CMU_AUD domain which
includes the clocks of Cortex-A5/Bus/Audio clocks.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:13 +01:00
Chanwoo Choi 2a1808a6c0 clk: samsung: exynos5433: Add clocks for CMU_DISP domain
This patch adds the the mux/divider/gate clocks for CMU_DISP domain
which includes clocks of the display IPs (DECON/HDMI/DSIM/MIXER).

Also, CMU_DISP requires 'sclk_hdmi_spdif_disp' source clock from CMU_TOP
domain. This patch adds the clocks of CMU_TOP related to HDMI.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:12 +01:00
Chanwoo Choi 06d2f9dfa6 clk: samsung: exynos5433: Add clocks for CMU_MIF domain
This patch adds the mux/divider/gate clocks of CMU_MIF domain which includes
the clocks for DMC(DRAM memory controller) and CCI(Cache Coherent Interconnect).
The CMU_MIF domain provides the source clocks for CMU_DISP/CMU_BUS2.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:11 +01:00
Chanwoo Choi a29308dad5 clk: samsung: exynos5433: Add clocks for CMU_G2D domain
This patch adds ths mux/divider/gate clocks of CMU_G2D domain which
includes G2D/MDMA IPs. The CMU_G2D requires its parent defined in
the CMU_TOP domain. Hence this patch adds G2D related clocks to the
CMU_TOP domain.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:11 +01:00
Chanwoo Choi 56bcf3f3ea clk: samsung: exynos5433: Add clocks for CMU_PERIS domain
This patch adds missing gate clocks of CMU_PERIS domain
which includes TMU/TZPC/SECKEY/CHIPID/TOPRTC/EFUSE IPs.
The special clocks of CMU_PERIS use oscclk source clock directly.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:10 +01:00
Chanwoo Choi d0f5de6677 clk: samsung: exynos5433: Add clocks for CMU_PERIC domain
This patch adds missing divider/gate clocks of CMU_PERIC domain
which includes I2S/PCM/SPDIF/PWM/SLIMBUS IPs. The SPI/I2S may use
external input clock which has 'ioclk_*' prefix.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
[ideal.song: Change clk flags of to pclk_gpio_* clk, pclk_gpio_* should be always on]
Signed-off-by: Inha Song <ideal.song@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:09 +01:00
Chanwoo Choi 232364969d clk: samsung: exynos5433: Add MUX clocks of CMU_TOP domain
This patch adds the MUX (multiplexer) clocks for CMU_TOP domain of Exynos5433.
CMU_TOP domain provides source clocks to other CMU domains.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:58:09 +01:00
Chanwoo Choi 96bd6224f0 clk: samsung: exynos5433: Add clocks using common clock framework
This patch adds support for the CMU (Clock Management Units) of Exynos5433
which is an Octa-core 64bit SoC. This patch supports necessary clocks
(PLL/MMC/UART/MCT/I2C/SPI) for kernel boot and includes binding documentation
for Exynos5433 clock controller.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Inki Dae <inki.dae@samsung.com>
[s.nawrocki@samsung.com: whitespace cleanup in dt-bindings/clock/exynos5433.h]
[                        added U suffix to first arguments of PLL_35XX_RATE()]
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-02-04 18:56:25 +01:00
Stefan Wahren 039e597075 clk: mxs: Fix invalid 32-bit access to frac registers
According to i.MX23 and i.MX28 reference manual [1],[2] the fractional
clock control register is 32-bit wide, but is separated in 4 parts.
So write instructions must not apply to more than 1 part at once.

The clk init for the i.MX28 violates this restriction and all the other
accesses on that register suggest that there isn't such a restriction.

This patch restricts the access to this register to byte instructions and
extends the comment in the init functions.

Btw the imx23 init now uses a R-M-W sequence just like imx28 init
to avoid any clock glitches.

The changes has been tested with a i.MX23 and a i.MX28 board.

[1] - http://cache.freescale.com/files/dsp/doc/ref_manual/IMX23RM.pdf
[2] - http://cache.freescale.com/files/dsp/doc/ref_manual/MCIMX28RM.pdf

Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Reviewed-by: Marek Vasut <marex@denx.de>
Reviewed-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03 13:08:05 -08:00
Arnd Bergmann 6793a30a06 clk: omap: compile legacy omap3 clocks conditionally
The 'ARM: OMAP3: legacy clock data move under clk driver' patch series
causes build errors when CONFIG_OMAP3 is not set:

drivers/clk/ti/dpll.c: In function 'ti_clk_register_dpll':
drivers/clk/ti/dpll.c:199:31: error: 'omap3_dpll_ck_ops' undeclared (first use in this function)
  const struct clk_ops *ops = &omap3_dpll_ck_ops;
                               ^
drivers/clk/ti/dpll.c:199:31: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/ti/dpll.c:259:10: error: 'omap3_dpll_per_ck_ops' undeclared (first use in this function)
   ops = &omap3_dpll_per_ck_ops;
          ^

drivers/built-in.o: In function `ti_clk_register_gate':
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_omap3430es2_dss_usbhost_wait'
drivers/clk/ti/gate.c:179: undefined reference to `clkhwops_am35xx_ipss_module_wait'
-in.o: In function `ti_clk_register_interface':
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_hsotgusb_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_dss_usbhost_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_omap3430es2_iclk_ssi_wait'
drivers/clk/ti/interface.c💯 undefined reference to `clkhwops_am35xx_ipss_wait'
drivers/built-in.o: In function `ti_clk_register_composite':
:(.text+0x3da768): undefined reference to `ti_clk_build_component_gate'

In order to fix that problem, this patch makes the omap3 legacy code
compiled only when both CONFIG_OMAP3 and CONFIG_ATAGS are set.

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-03 11:06:11 -08:00
Michael Turquette f85c6edfae Tegra clock fixes for 3.20
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUz5H9AAoJEFFb18rurjwTwssP/1luchJTB3qo+tqAIYYADgA4
 9QLQqfgIqZuJzzCNYgauELwN5M8S02ZABRzY9OOHnUY6BvoHPMpcOEey7i33ZYTJ
 9l4TFBOQyZE6W8tcyVL47pc9cjZydz9KKMO+/T5M16YyYoNZ1rXeGUli5j5sl2j7
 KoNurjC6C9Hw0M8+6CBTk4tYcMtxXeIacSGhV4VM03qKWj3e7485z0tYTG9yKfVD
 ol3KKGwjg1eZ9FSavMVYYnWajXZ7zlbB1PFqWO6V9h7DKmJMINbXGf/qr+/8eYSq
 zefWEYs1uGKunFtDv3C8wGRnl8ronBHehS2/xPpVEni0Eu2kJo1v8wDmftZ5ZyFW
 86ZdS4JTWD1/A2buEbJ3Ct30reNasGFUGNxIrYROglY4dK6DEPCMEFx5ZNiOhxlJ
 +BMjcsDzTt1gUWHbpxHrIZFErtHKcxtHeVckcZJgh87bnHVQKTAJ3cL9OJSWatqO
 lBDIsFxSOLap4gMKcMNddOEI8JNL1VZh+I/GdTh6VE2rhcurMNHvxmWL1TJ94/w8
 tRHRU5kRdYmxPzL98nDSR0h8WXShdWmnYNr+m2fk8iiPsI4umh/RS014kPVUYKq9
 a16cHkq88x3mKlEcyARG9tJK9oOCC5MuNuMPsPKf1dETOgHbAixlJVK5FHzHLjNr
 fERakm8nBM3rMSlgBbUL
 =k023
 -----END PGP SIGNATURE-----

Merge tag 'tegra-clk-3.20' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next

Tegra clock fixes for 3.20
2015-02-02 15:01:10 -08:00
Michael Turquette b530e7d210 Exynos 3250, 4415 drivers cleanup by using common code
and addition of clock definitions for DVFS on Exynos4.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABCAAGBQJUyPwjAAoJEE1bIKeAnHqLbcQP/RQoZLdRJqhToiWxMKzQjaEh
 KPOAEBNGMOvPeVrf3Ct6r2a6elgLg6pKdYZcekupu9Vqrc0OXdHVKEM/YC7x5MEB
 Wzs/cuVZyYb8lhnWa0dmUTEQp/JvYX1Ifgp2xlKFc6ZPstuxIsp2HizQIS8+xsqW
 NxUIwkz1X0xyO4oLmVG7cO7co4FgSBfY3YI/PnUgDuixoX0X6eY0uNMLMS5J/5gP
 wOmwDmgJop/qi7tMfghDwDemF3/WJBY8V2D/dIvCoSsFu0bGAPqPnemEuaeBCbEo
 1sVrvEz60kXaJSx7A44Or2KX8cvaSPExcVmG66idYLlOW+gGXgjCRZ11A2FmzBDb
 sWXMkwSNeZ3QxL6fmJuRkXYDbwHNWlKdZIjlM6+iYPjA78twUEN5tD1U1YTh0cy/
 MCFmoUWJh2vpbQJiY3carcvq1NiNhALFUWrJK5zCoMybvIWrQhYBBCnZh7U1fDzo
 nmxLcDr1IG6eRjOfn6Q2XVmCXjhZX3kojAh/ePEHQGl5jyspZcMm4Top93sTO9l6
 SBimh5wrafK8nTQN8NeNGNr3s3CfYVURu9GdEiJJwecHnWoeFFc/Y/w7qaWorNtM
 tsg7Gjk+95OgM+m8Cb8Nu8WXUyK7AYznbgldzypx7FVMQRpDW7/UjpB0lKjT7qeG
 c0ScBKIXZd6RNyzHM2TJ
 =rFdT
 -----END PGP SIGNATURE-----

Merge tag 'v3.20-exynos-clk' of git://linuxtv.org/snawrocki/samsung into clk-next

Exynos 3250, 4415 drivers cleanup by using common code
and addition of clock definitions for DVFS on Exynos4.
2015-02-02 14:51:16 -08:00
Tomeu Vizoso a251361ac4 clkdev: Export clk_register_clkdev
So it can be used from modules such as clk-test.ko.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-02 14:23:43 -08:00
Tomeu Vizoso 1c8e600440 clk: Add rate constraints to clocks
Adds a way for clock consumers to set maximum and minimum rates. This
can be used for thermal drivers to set minimum rates, or by misc.
drivers to set maximum rates to assure a minimum performance level.

Changes the signature of the determine_rate callback by adding the
parameters min_rate and max_rate.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
[sboyd@codeaurora.org: set req_rate in __clk_init]
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: min/max rate for sun6i_ahb1_clk_determine_rate
                        migrated clk-private.h changes to clk.c]
2015-02-02 14:23:42 -08:00
Michael Turquette b09d6d9910 clk: remove clk-private.h
Private clock framework data structures should be private, surprisingly.

Now that all platforms and drivers have been updated to remove static
initializations of struct clk and struct clk_core objects and all
references to clk-private.h have been removed we can move the
definitions of these structures into drivers/clk/clk.c and delete the
header.

Additionally the ugly DEFINE_CLK macros have been removed. Those were
used for static definitions of struct clk objects. That practice is no
longer allowed.

Finally __clk_init is staticized as it is no longer declared in any
header.

Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-02-02 14:23:41 -08:00
Michael Turquette fe76756052 Merge branch 'clk-omap-legacy' into clk-next
Conflicts:
	arch/arm/mach-omap2/cclock3xxx_data.c
2015-02-02 14:23:33 -08:00
Tomeu Vizoso 035a61c314 clk: Make clk API return per-user struct clk instances
Moves clock state to struct clk_core, but takes care to change as little API as
possible.

struct clk_hw still has a pointer to a struct clk, which is the
implementation's per-user clk instance, for backwards compatibility.

The struct clk that clk_get_parent() returns isn't owned by the caller, but by
the clock implementation, so the former shouldn't call clk_put() on it.

Because some boards in mach-omap2 still register clocks statically, their clock
registration had to be updated to take into account that the clock information
is stored in struct clk_core now.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: adapted clk_has_parent to struct clk_core
                        applied OMAP3+ DPLL fix from Tero & Tony]
2015-02-02 14:22:19 -08:00
Mark Zhang b270491eb9 clk: tegra: Define PLLD_DSI and remove dsia(b)_mux
PLLD is the only parent for DSIA & DSIB on Tegra124 and
Tegra132. Besides, BIT 30 in PLLD_MISC register controls
the output of DSI clock.

So this patch removes "dsia_mux" & "dsib_mux", and create
a new clock "plld_dsi" to represent the DSI clock enable
control.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mark Zhang <markz@nvidia.com>
2015-02-02 16:22:34 +02:00
Paul Walmsley 08acae34e8 clk: tegra: Add support for the Tegra132 CAR IP block
Tegra132 CAR supports almost the same clocks as Tegra124 CAR. This
patch mostly deals with the small differences.

Since Tegra132 contains many of the same PLL clock sources used on
Tegra114 and Tegra124, enable them in drivers/clk/tegra/clk-pll.c when
the kernel is configured to include Tegra132 support.

This patch is based on several patches from others:

1. a  patch from Peter De Schrijver:

http://lkml.iu.edu/hypermail/linux/kernel/1407.1/06094.html

2. a patch from Bill Huang ("clk: tegra: enable cclk_g at boot on
Tegra132"), and

3. a patch from Allen Martin ("clk: Enable tegra clock driver for
tegra132").

Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Peter De Schrijver <pdeschrijver@nvidia.com>
Cc: Allen Martin <amartin@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: Bill Huang <bilhuang@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
2015-02-02 15:47:53 +02:00
Peter De Schrijver d0a57bd5b5 clk: tegra: make tegra_clocks_apply_init_table() arch_initcall
tegra_clocks_apply_init_table() needs to be called after the udelay
loop has been calibrated (see commit
441f199a37 ("clk: tegra: defer
application of init table") for why that is).  On existing Tegra SoCs
this was done by calling tegra_clocks_apply_init_table() from
tegra_dt_init(). To make this also work on ARM64, we need to change
this into an initcall. tegra_dt_init() is called from
customize_machine which is an arch_initcall. Therefore this should
also work on existing 32bit Tegra SoCs.

Tested on Tegra20 (ventana), Tegra30 (beaverboard), Tegra124 (jetson TK1) and
Tegra132.

Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
[paul@pwsan.com: tweaked the commit message]
Signed-off-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Paul Walmsley <pwalmsley@nvidia.com>
Cc: Thierry Reding <treding@nvidia.com>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
2015-02-02 15:47:28 +02:00
Tomeu Vizoso ca036b261c clk: tegra: Fix order of arguments in WARN
As previously the names of the present clock and its parent were swapped.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:47:04 +02:00
Sean Paul f892f24b37 clk: tegra124: Add init data for dsi lp clocks
Set the parent of the dsi lp clocks to pll_p and the rate
to 68MHz. The default parent is clk_m and rate is 12MHz, this
is too slow to receive data from the peripheral.

Per NVidia HW engineers, the optimal rate is 70MHz, but 68MHz
will suffice.

Signed-off-by: Sean Paul <seanpaul@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:46:34 +02:00
Andrew Bresticker 18abd16376 clk: tegra: SDMMC controllers are on APB
Since the SDMMC controller registers are accessed via the APB,
the APB must be flushed before gating the SDMMC clocks to prevent
register accesses to the SDMMC controllers after their clocks are
gated.

Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
2015-02-02 15:46:14 +02:00
Tero Kristo 74807dffcd clk: ti: add omap3 legacy clock data
Introduces omap3 legacy clock data under clock driver. The clock data
is also in new format, which makes it possible to get rid of the
clk-private.h header. This patch also introduces SoC specific init
functions that shall be called from the low level init.

The data format used in this file has two possible evolution paths;
it can either be removed completely once no longer needed, or it will
be possible to retain the format and modify the TI clock driver to be
a loadable module at some point. The actual path to be followed
will be decided later.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:19 -08:00
Tero Kristo b26bcf9be6 clk: ti: composite: add support for legacy composite clock init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:15 -08:00
Tero Kristo ed405a2350 clk: ti: dpll: add support for legacy DPLL init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:09 -08:00
Tero Kristo d96f774b25 clk: ti: divider: add support for legacy divider init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:05 -08:00
Tero Kristo 06524fa428 clk: ti: interface: add support for legacy interface clock init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this. The interface clock descriptor
itself is overloading the gate clock descriptor, thus it needs to
be called from the gate setup.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:55:00 -08:00
Tero Kristo f187616b36 clk: ti: gate: add support for legacy gate init
Legacy clock data is initialialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:54:54 -08:00
Tero Kristo 7c18a65cb5 clk: ti: mux: add support for legacy mux init
Legacy clock data is initialized slightly differently compared to
DT clocks, thus add support for this.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:54:49 -08:00
Tero Kristo c82f8957b4 clk: ti: add core support for initializing legacy clocks
Legacy clock data for OMAP3 is being moved under clock driver, thus
base support for this is needed. This patch adds basic definitions for
clock init descriptors and core infrastructure for initialization,
which will be called from the OMAP3 clock init.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-30 10:50:09 -08:00
Javier Martinez Canillas 8856010029 clk: exynos5420: Add IDs for clocks used in DISP1 power domain
When a power domain is powered off on Exynos5420 SoC, the input clocks of
the devices attached to this power domain are re-parented to oscclk and
restored to the original parent after powering on the power domain.

So a reference to the input and parent clocks for the devices attached to
a power domain are needed to be able to do the re-parenting. The DISP1 pd
includes modules which uses the following clocks:

ACLK_200_DISP1 (MIXER and HDMILINK)
ACLK_300_DISP1 (FIMD1)
ACLK_400_DISP1 (Internal Buses)

Each of these clocks are generated as the output of a clock mux so add an
ID for all of these clock muxes and their parents to be referenced in the
DISP1 power domain device node.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene@kernel.org>
2015-01-29 08:52:22 +09:00
Tomeu Vizoso af0f349b29 clk: Remove __clk_register
As it has never been used.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:40:18 -08:00
Tomeu Vizoso c440525cb9 clk: Remove unneeded NULL checks
As clk_unprepare_unused_subtree and clk_disable_unused_subtree are
always called with a valid struct clk.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:40:18 -08:00
Emil Medve c88b2b662a clk: qoriq: Use pr_fmt()
Currently a mix of clk-qoriq/qoriq-clk and no prefix is used

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:40 -08:00
Emil Medve 6ef1ccac50 clk: qoriq: Replace kzalloc() with kmalloc()
Where the memset() is not necessary

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:40 -08:00
Emil Medve 334680dd51 clk: qoriq: Make local symbol 'static'
drivers/clk/clk-qoriq.c:59:22: warning: symbol 'cmux_ops' was not declared. Should it be static?

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 8002cab6ba clk: qoriq: Fix checkpatch type OOM_MESSAGE
WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!parent_names) {
+               pr_err("%s: could not allocate parent_names\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!cmux_clk) {
+               pr_err("%s: could not allocate cmux_clk\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!subclks) {
+               pr_err("%s: could not allocate subclks\n", __func__);

WARNING:OOM_MESSAGE: Possible unnecessary 'out of memory' message
+       if (!onecell_data) {
+               pr_err("%s: could not allocate onecell_data\n", __func__);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 13c25f57d4 clk: qoriq: Fix checkpatch type ALLOC_SIZEOF_STRUCT
CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*cmux_clk)...) over kzalloc(sizeof(struct cmux_clk)...)
+       cmux_clk = kzalloc(sizeof(struct cmux_clk), GFP_KERNEL);

CHECK:ALLOC_SIZEOF_STRUCT: Prefer kzalloc(sizeof(*onecell_data)...) over kzalloc(sizeof(struct clk_onecell_data)...)
+       onecell_data = kzalloc(sizeof(struct clk_onecell_data), GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve a924722597 clk: qoriq: Fix checkpatch type ALLOC_WITH_MULTIPLY
WARNING:ALLOC_WITH_MULTIPLY: Prefer kcalloc over kzalloc with multiply
+       subclks = kzalloc(sizeof(struct clk *) * count, GFP_KERNEL);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:39 -08:00
Emil Medve 78f4a63e64 clk: qoriq: Fix checkpatch type PARENTHESIS_ALIGNMENT
CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+       rc = of_property_read_string_index(np, "clock-output-names",
+                       0, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clock provider for node:%s\n",
+                        np->name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               rc = of_property_read_string_index(np, "clock-output-names",
+                               i, &clk_name);

CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
+               pr_err("Could not register clk provider for node:%s\n",
+                        np->name);

Signed-off-by: Emil Medve <Emilian.Medve@Freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-28 10:11:38 -08:00
Chanwoo Choi e64fb42da4 clk: samsung: exynos4: Add divider clock id for memory bus frequency
This patch adds the divider clock id for Exynos4 memory bus frequency.
The clock id is used for DVFS (Dynamic Voltage/Frequency Scaling)
feature of the exynos memory bus.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-28 15:51:17 +01:00
Robert Jarzmik 9bbb8a338f clk: pxa: add pxa3xx clock driver
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
 - convert to new clock framework legacy clocks
 - provide clocks as before for platform data based boards
 - provide clocks through devicetree with clk-pxa-dt

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 17:03:52 -08:00
Soren Brinkmann 3dccfecdb8 clk: zynq: Force CPU_2X clock to be ungated
The CPU_2X clock does not have a classical in-kernel user, but is,
amongst other things, required for OCM and debug access. Make sure this
clock is not mistakenly disabled during boot up by enabling it in the
platform's clock driver.

Cc: stable@vger.kernel.org # 3.11+
Fixes: 0ee52b157b 'clk: zynq: Add clock controller driver'
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 17:00:24 -08:00
David S. Miller 95f873f2ff Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	arch/arm/boot/dts/imx6sx-sdb.dts
	net/sched/cls_bpf.c

Two simple sets of overlapping changes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2015-01-27 16:59:56 -08:00
Michael Turquette 8f101aa027 Allwinner clock changes for 3.20
The set of clock changes for the 3.20 merge window, with mostly:
   - Some PLL fixes for the A80 and A31
   - The MMC custom phase functions are removed, and moved over to the generic
     phase API.
   - Add the A80 MMC clocks
 
 Some DT changes slipped here as well, to preserve bisectability.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUxSZeAAoJEBx+YmzsjxAgXeAP/0aIFOuvCQ00JrXoIiKogery
 S66HZpVclU9nvhFh99fhVBB0AP0TcH5qZPYCeughCO07SdtnbKVEb2A+2aMP4uzN
 dRlL6smk8F9/bUq0yhUzX4e1NbDGVeWaXw2JWxvZ7WGwavjQ9ejS1Pb1BMAwUnVY
 ZUebVkbw7XlVkYr3/GROVWTtNswYu8L/8aY438OoK+VnaVWo5N/+8kX8i+I85bxW
 4G8WvNO36neEh3Oc4aBbetW29ZQbXlt6IJ89tkEaxtC4Z29VNSeXJfpadYLZRrP+
 8+IUA5YVau/9VJePdF5a4BM55Uee7M4aMqVENGiUHMFLMGSJNyR2G9+qu658Twyn
 vP//imP34mTVI5D8oo9cOdKgQh2Prf9K8MmYuAvQxVaTEpt4wx2v7jVi1G/m9etX
 mxn95h0G7wIFMwPQiZfbvCgw8QOSXWYa59A4d1209SDB0vGYWgG2HJQvJnBPJmhq
 9Ifczv9Ia7M6CuTZfdhf0TrABML56IC8JCtCJ1Zk6mUKc+lE+m4IdM68drfM0WC9
 +KOC07QJiB0tEHyauppbVvaY6Jon2bYhUyEzGl6gpfYg4VuoBavzS2vVSc8E0n9Z
 iYPXtXE8soygRZVgvQ58YN8yKWZI+Ylpz9EAJ1a82fCAG8r3iJ8FNixpfB93nRxU
 6GcGqhSQayZY74mRnBqb
 =m8K6
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clocks-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner clock changes for 3.20

The set of clock changes for the 3.20 merge window, with mostly:
  - Some PLL fixes for the A80 and A31
  - The MMC custom phase functions are removed, and moved over to the generic
    phase API.
  - Add the A80 MMC clocks

Some DT changes slipped here as well, to preserve bisectability.
2015-01-27 16:33:45 -08:00
Michael Turquette b80418f3c0 The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
 very strange place, but the watchdog driver needs to read the clock
 rate from it and the setting of rk3288 plls to slow mode upon suspend.
 
 Other than that some more exported clocks and a CLK_SET_RATE_PARENT
 flag for the uart clocks.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUwT2NAAoJEPOmecmc0R2BjmsH/1Mp2vS9E9RBREhL/uuwtVlE
 6FhINcpzVkDrwXGfupVbrWmzHTxKcyUbnluVPsLs0BCRqhhKSU0t+TT5j+mRMOpu
 oNq/d3cp//fuBaiLr4G0jrgd/a9Gq4SsshPP6kH41r5CBN87jTt9wazX2GjNBf4C
 LYsNNWj/qpXxeA/rFuMsI15ntPiFvap8Ag/5+IDCHuT9nwCLy7iI3G0MRGZ1kfGT
 byOJd/FOqfAk3UJXuEgGOu27ZAOcbGLk7EL7YUdq7C70wAlUTu/8smTLqJFbXc9T
 Xgum3FnYcuPZqNQSxQMXFpgyzE0q7KLyufv5gU1A4s2Ac69cD3nDVh9k1LAcu4s=
 =arKA
 -----END PGP SIGNATURE-----

Merge tag 'v3.20-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

The two big changes are the additional of the watchdog clock, which
we currently only "fake" as the clock gate control is living in a
very strange place, but the watchdog driver needs to read the clock
rate from it and the setting of rk3288 plls to slow mode upon suspend.

Other than that some more exported clocks and a CLK_SET_RATE_PARENT
flag for the uart clocks.
2015-01-27 16:26:12 -08:00
Stephen Boyd e387088a03 clk: ti: Drop use of clk-private.h
These modules don't need to include clk-private.h. Replace the
include with clk.h because these modules are clock consumers and
also include clk-provider.h in clk/ti.h because struct
clk_hw_omap has a struct clk_hw embedded in it.

Cc: Tero Kristo <t-kristo@ti.com>
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Paul Walmsley <paul@pwsan.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:58:54 -08:00
Stephen Boyd 3a5c111f5d clk: ux500: Drop use of clk-private.h
These drivers don't need to include clk-private.h. Remove the
include.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:56:33 -08:00
Maxime Ripard 9767b04fe6 clk: Export phase functions
The phase setter and getter were not exported until now, which was causing
build breakages when callers were compiled as module. Export these two
functions.

Reported-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:52:43 -08:00
Stephen Boyd b82875ee07 clk: qcom: Add MSM8960/APQ8064 LPASS clock controller (LCC) driver
Add an LCC driver for MSM8960/APQ8064 that supports the i2s,
slimbus, and pcm clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:49:34 -08:00
Rajendra Nayak c99e515a92 clk: qcom: Add IPQ806X LPASS clock controller (LCC) driver
Add an LCC driver for IPQ806x that supports the i2s, S/PDIF, and
pcm clocks.

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
[sboyd@codeaurora.org: Reworded commit text, added Kconfig
select, fleshed out Kconfig description a bit more, added pll4
configuration and reworked probe for it, added muxes, split out
dt-binding file]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:49:19 -08:00
Stephen Boyd b3ee3eff57 clk: qcom: Add simple regmap based muxes
Add support for muxes that use regmap instead of readl/writel
directly. We don't support as many features as clk-mux.c, but
this is good enough to support getting and setting parents.
Adding a table based lookup can be added in the future if needed.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:49:09 -08:00
Josh Cartwright 4116076e8c clk: qcom: Add support for regmap divider clocks
Add support for dividers that use regmap instead of readl/writel.

Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
[sboyd@codeaurora.org: Switch to using generic divider code, drop
enable/disable, reword commit text]
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:49:00 -08:00
Stephen Boyd bca9690b94 clk: divider: Make generic for usage elsewhere
Some devices don't use mmio to interact with dividers. Split out the
logic from the register read/write parts so that we can reuse the
division logic elsewhere.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:48:52 -08:00
Stephen Boyd 15a02c1f6d clk: Add __clk_mux_determine_rate_closest
Some clock drivers want to find the closest rate on the input of
a mux instead of a rate that's less than or equal to the desired
rate. Add a generic mux function to support this.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Tested-by: Kenneth Westfield <kwestfie@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:48:39 -08:00
Srinivas Kandagatla 52bba9809a clk: Fix debugfs clk removal before inited
Some of the clks can be registered & unregistered before the clk related debugfs
entries are initialized at late_initcall. In the unregister path checking for only
dentry before clk_debug_init() would lead dangling pointers in the debug clk list,
because the list is already populated in register path and the clk pointer freed in
unregister path.
The side effect of not removing it from the list is either a null pointer
dereference or if lucky to boot the system, the number of clk entries in
debugfs disappear.

We could add more checks like if (inited && !clk->dentry) but just removing
the check for dentry made more sense as debugfs_remove_recursive() seems to be
safe with null pointers. This will ensure that the unregistering clk would be
removed from the debug list in all the code paths.

Without this patch kernel would crash with log:
Unable to handle kernel NULL pointer dereference at virtual address 00000000
pgd = c0204000
[00000000] *pgd=00000000
Internal error: Oops: 5 [#1] SMP ARM
Modules linked in:
CPU: 1 PID: 1 Comm: swapper/0 Tainted: G    B          3.19.0-rc3-00007-g412f9ba-dirty #840
Hardware name: Qualcomm (Flattened Device Tree)
task: ed948000 ti: ed944000 task.ti: ed944000
PC is at strlen+0xc/0x40
LR is at __create_file+0x64/0x1dc
pc : [<c04ee604>]    lr : [<c049f1c4>]    psr: 60000013
sp : ed945e40  ip : ed945e50  fp : ed945e4c
r10: 00000000  r9 : c1006094  r8 : 00000000
r7 : 000041ed  r6 : 00000000  r5 : ed4af998  r4 : c11b5e28
r3 : 00000000  r2 : ed945e38  r1 : a0000013  r0 : 00000000
Flags: nZCv  IRQs on  FIQs on  Mode SVC_32  ISA ARM  Segment kernel
Control: 10c5787d  Table: 8020406a  DAC: 00000015
Process swapper/0 (pid: 1, stack limit = 0xed944248)
Stack: (0xed945e40 to 0xed946000)
5e40: ed945e7c ed945e50 c049f1c4 c04ee604 c0fc2fa4 00000000 ecb748c0 c11c2b80
5e60: c0beec04 0000011c c0fc2fa4 00000000 ed945e94 ed945e80 c049f3e0 c049f16c
5e80: 00000000 00000000 ed945eac ed945e98 c08cbc50 c049f3c0 ecb748c0 c11c2b80
5ea0: ed945ed4 ed945eb0 c0fc3080 c08cbc30 c0beec04 c107e1d8 ecdf0600 c107e1d8
5ec0: c107e1d8 ecdf0600 ed945f54 ed945ed8 c0208ed4 c0fc2fb0 c026a784 c04ee628
5ee0: ed945f0c ed945ef0 c0f5d600 c04ee604 c0f5d5ec ef7fcc7d c0b40ecc 0000011c
5f00: ed945f54 ed945f10 c026a994 c0f5d5f8 c04ecc00 00000007 ef7fcc95 00000007
5f20: c0e90744 c0dd0884 ed945f54 c106cde0 00000007 c117f8c0 0000011c c0f5d5ec
5f40: c1006094 c100609c ed945f94 ed945f58 c0f5de34 c0208e50 00000007 00000007
5f60: c0f5d5ec be9b5ae0 00000000 c117f8c0 c0af1680 00000000 00000000 00000000
5f80: 00000000 00000000 ed945fac ed945f98 c0af169c c0f5dd2c ed944000 00000000
5fa0: 00000000 ed945fb0 c020f298 c0af168c 00000000 00000000 00000000 00000000
5fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000
5fe0: 00000000 00000000 00000000 00000000 00000013 00000000 ebcc6d33 bfffca73
[<c04ee604>] (strlen) from [<c049f1c4>] (__create_file+0x64/0x1dc)
[<c049f1c4>] (__create_file) from [<c049f3e0>] (debugfs_create_dir+0x2c/0x34)
[<c049f3e0>] (debugfs_create_dir) from [<c08cbc50>] (clk_debug_create_one+0x2c/0x16c)
[<c08cbc50>] (clk_debug_create_one) from [<c0fc3080>] (clk_debug_init+0xdc/0x144)
[<c0fc3080>] (clk_debug_init) from [<c0208ed4>] (do_one_initcall+0x90/0x1e0)
[<c0208ed4>] (do_one_initcall) from [<c0f5de34>] (kernel_init_freeable+0x114/0x1e0)
[<c0f5de34>] (kernel_init_freeable) from [<c0af169c>] (kernel_init+0x1c/0xfc)
[<c0af169c>] (kernel_init) from [<c020f298>] (ret_from_fork+0x14/0x3c)
Code: c0b40ecc e1a0c00d e92dd800 e24cb004 (e5d02000)
---[ end trace b940e45b5e25c1e7 ]---

Fixes: 6314b6796e "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-27 11:45:53 -08:00
Michael Turquette 88f52ecde0 Merge branch 'clk-shmobile-for-3.20' of git://git.kernel.org/pub/scm/linux/kernel/git/geert/renesas-drivers into clk-next 2015-01-27 11:34:41 -08:00
Olof Johansson 688a4994cc Allwinner core changes for 3.20
- Support for the A31s
   - Adding support for cpufreq using cpufreq-dt
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUxSahAAoJEBx+YmzsjxAgw7cP/iukSTTuTxagl9HLmet3pSY/
 v4WunNKUm/cTWQkcK9xEOy2TV2nFQ00mdji1Jf1EI/cacBKvByTsmPlEOkfj0dnG
 mfxkWiF3bwcpG1L0ABIFnU1A1/PjDGTl0jMp2q7S8BE09jJfb8TcY3wwfoWRwAeD
 LFPICHbsGRIb5WU/3pq14/GaYYSTt/BRe6+wCuB/zoU4b8HaGzw6ztZ2Gz2ztUtw
 m2xYcWUEj0kmeX/wg52eRxJrjcznwDoabxxPM+q7ttL3J3NG/A81Uf0lkLlwl2fD
 QSueSzsE68RsG0q/SkvQ5jkVDyOX/4o6bSdy6O8pS/qW1rwgqVDnPzrYXuj8duU4
 /Y+B6lAXdGierXSWhmuGBSPBNO/zblPNrJbJRqNlGscU1qfaWzZXSW8hRFlyMx4P
 17TARZLmZtruGsLWSwMpsjXFtJOnF7kdwdKqx2aoV1ZmTmNVhOKopUohNRFKSU+F
 e9a/U+yN5LggQG34s+YoPggwUg3qjBengA6yO8t5aOz9upjhEzqML1uulYrvPrRS
 8qsjkbgSdXZruG26l4pJYUIZ6QMgma3shxDGXvvenAI45pRniG1YfKPlh9Z0c3Dh
 VZRvR+mM6v82z3+mtOf9VSrJkUnOUTONRA3Qt2dSFU4LZaPlDtG0dxbxEA0E+KgQ
 0XRz7Bu0LRVkzn6un+4d
 =JU1v
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-core-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/soc

Merge "Allwinner core changes for 3.20" from Maxime Ripard:

  - Support for the A31s
  - Adding support for cpufreq using cpufreq-dt

* tag 'sunxi-core-for-3.20' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  ARM: sunxi: Register cpufreq-dt for sun[45678]i
  ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi

Signed-off-by: Olof Johansson <olof@lixom.net>
2015-01-26 20:23:45 -08:00
Hans de Goede 76820fcf7a sunxi: clk: Set sun6i-pll1 n_start = 1
For all pll-s on sun6i n == 0 means use a multiplier of 1, rather then 0 as
it means on sun4i / sun5i / sun7i. n_start = 1 is already correctly set
for sun6i pll6, but was missing for pll1, this commit fixes this.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-25 16:55:25 +01:00
Hans de Goede 6424e0aeeb clk: sunxi: rewrite sun9i_a80_get_pll4_factors()
The old implementation of sun9i_a80_get_pll4_factors() has several issues,
it checks against 256 / 512 in various places where it should use 255 / 511,
it does the wrong thing for low frequencies which are an even multiple of
6 MHz, e.g. if you ask it for 72 MHz it will result in 144 Mhz, and it does
not take into account that n must be at least 12. Moreover it is quite hard
to read / follow it.

This commit rewrites it to be correct in all cases, and makes it much easier
to follow the code / to read.

Cc: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-25 16:55:13 +01:00
Michael Turquette 57386798f7 Merge branch 'clk-has-parent' into clk-next 2015-01-24 16:58:40 -08:00
Thierry Reding 4e88f3de89 clk: Introduce clk_has_parent()
This new function is similar to clk_set_parent(), except that it doesn't
actually change the parent. It merely checks that the given parent clock
can be a parent for the given clock.

A situation where this is useful is to check that a particular setup is
valid before switching to it. One specific use-case for this is atomic
modesetting in the DRM framework where setting a mode is divided into a
check phase where a given configuration is validated before applying
changes to the hardware.

Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-24 16:56:55 -08:00
Heiko Stuebner e142a4e914 clk: rockchip: add a dummy clock for the watchdog pclk on rk3288
The pclk supplying the watchdog is controlled via the SGRF register area.
Currently we don't have any clock-type handling external clock bits like
this one. Additionally the SGRF isn't even writable in every boot mode.

But still the clock control is available and in the future someone might
want to use it. Therefore define a simple clock for the time being so
that the watchdog driver can read its rate.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:42:24 +01:00
huang lin cc6430689e clk: rockchip: add PVTM clocks on rk3288
Process-Voltage-Temperatiure Monitor block on RK3288 has two clocks:
PVTM_CORE and PVTM_GPU.

Signed-off-by: Huang Lin <hl@rock-chips.com>
Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:41:20 +01:00
Kever Yang f5c3018dd0 clk: rockchip: use the clock ID for usbphy480m_src
Use the clock ID for usbphy480m_src so that we can find
this clock node in dts.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2015-01-22 15:41:16 +01:00
Ingo Molnar f49028292c Merge branch 'for-mingo' of git://git.kernel.org/pub/scm/linux/kernel/git/paulmck/linux-rcu into core/rcu
Pull RCU updates from Paul E. McKenney:

  - Documentation updates.

  - Miscellaneous fixes.

  - Preemptible-RCU fixes, including fixing an old bug in the
    interaction of RCU priority boosting and CPU hotplug.

  - SRCU updates.

  - RCU CPU stall-warning updates.

  - RCU torture-test updates.

Signed-off-by: Ingo Molnar <mingo@kernel.org>
2015-01-21 06:12:21 +01:00
Oleksij Rempel ec6415dc41 ARM: clk: add clk-asm9260 driver
Provide CLK support for Alphascale ASM9260 SoC.

Signed-off-by: Oleksij Rempel <linux@rempel-privat.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:10:51 -08:00
Peter Griffin edc30077c9 clk: st: STiH410: Fix pdiv and fdiv divisor when setting rate
Debugging eMMC on upstream kernels it has been noticed that when the
targetpack configures MMC0 clock to 200Mhz (required to switch to
HS200) then everything works OK. However if the kernel sets the
clock rate using clk_set_rate, then the eMMC card initialisation
fails with timeouts. Lower clock speeds (the default being 50Mhz)
work ok, but they we fail to get good eMMC transfer rates.

Looking through the vendor kernel clock driver reveals Giuseppe
had already fixed this issue, but the patch hasn't made its way
upstream.

The issue is fixed by changing the logic to manage the pdiv and
fdiv divisors used for setting the rate inside the flexgen driver code.

Pdiv is mainly targeted for low freq results, while fdiv should be
used for divs =< 64. The other way can lead to 'duty cycle'
issues.

I have changed the original patch to keep the original behaviour
in cases where the div is >64 which matches the original comment
and patch description more closely. Although no clocks appear to hit
this case currently when booting an upstream kernel.

Signed-off-by: Peter Griffin <peter.griffin@linaro.org>
Signed-off-by: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:13 -08:00
Tang Yuantian 93a17c058f clk: ppc-corenet: rename driver to clk-qoriq
Freescale introduced new ARM-based socs which using the compatible
clock IP block with PowerPC-based socs'. So this driver can be used
on both platforms.
Updated relevant descriptions and renamed this driver to better
represent its meaning and keep the function of driver untouched.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:12 -08:00
Tang Yuantian 57bfd7ee6f clock: redefine variable clocks_per_pll as a struct member
redefine variable clocks_per_pll as a struct member

If there are multiple PLL clock nodes, this variable will
get overwritten. Redefining it as a struct member can avoid that.

Signed-off-by: Tang Yuantian <Yuantian.Tang@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:10 -08:00
Michael Turquette 1114428312 Merge tag 'for-v3.20-exynos7-clk' of git://linuxtv.org/snawrocki/samsung into clk-next
- Clock definitions for Exynos7 SoC peripheral devices:
  video scaler, USB, DMA, SPI and the audio subsystem.
2015-01-20 10:09:09 -08:00
Tony Lindgren 1a34275d34 clk: ti: Initialize clocks for dm816x
The clocks on ti81xx are not compatible with omap3. On dm816x
the clock source is a FAPLL (Flying Adder PLL), and on dm814x
there seems to be an APLL (All Digital PLL).

Let's fix up things for dm816x in preparation for adding the
FAPLL support. As we already have a dummy ti81xx_dt_clk_init()
in place, let's use that for now to avoid adding a dependency
to the omap patches.

Later on if somebody adds dm814x support we can split the
ti81xx_dt_clk_init() clock init function as needed.

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:08 -08:00
Tony Lindgren 163152cbbe clk: ti: Add support for FAPLL on dm816x
On dm816x the clocks are sourced from a FAPLL (Flying Adder PLL)
that does not seem to be used on the other omap variants.

There are four instances of the FAPLL on dm816x that each have three
to seven child synthesizers.

I've set up the FAPLL as a single fapll.c driver. Later on we could
potentially have the PLL code generic. To do that, we would have to
consider the following:

1. Setting the PLL to bypass mode also sets the child synthesizers
   into bypass mode. As the bypass rate can also be generated by
   the PLL in regular mode, there's no way for the child synthesizers
   to detect the bypass mode based on the parent clock rate.

2. The PLL registers control the power for each of the child
   syntheriser.

Note that the clocks are currently still missing the set_rate
implementation so things are still running based on the bootloader
values. That's OK for now as most of the outputs have dividers and
those can be set using the existing TI component clock code.

I have verified that the extclk rates are correct for a few clocks,
so adding the set_rate support should be fairly trivial later on.

This code is partially based on the TI81XX-LINUX-PSP-04.04.00.02
patches published at:

http://downloads.ti.com/dsps/dsps_public_sw/psp/LinuxPSP/TI81XX_04_04/04_04_00_02/index_FDS.html

Cc: Brian Hutchinson <b.hutchman@gmail.com>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:07 -08:00
Stephen Boyd 4526e7b857 clk: Skip fetching index for single parent clocks
We don't need to fetch the parent index for clocks if they only
have one parent. Doing this also avoid an unnecessary allocation
for the parent cache.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:06 -08:00
Sergei Shtylyov 2e9dcdae40 clk-gate: fix bit # check in clk_register_gate()
In case CLK_GATE_HIWORD_MASK flag is passed to clk_register_gate(), the bit #
should be no higher than 15, however the corresponding check is obviously off-
by-one.

Fixes: 045779942c ("clk: gate: add CLK_GATE_HIWORD_MASK")
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:05 -08:00
Kevin Hao 66619ac512 clk: ppc-corenet: fix section mismatch warning
In order to fix the following section mismatch warning:
  WARNING: drivers/clk/built-in.o(.data+0xe4): Section mismatch in reference from the variable ppc_corenet_clk_driver to the function .init.text:ppc_corenet_clk_probe()
  The variable ppc_corenet_clk_driver references
  the function __init ppc_corenet_clk_probe()
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

  WARNING: drivers/clk/built-in.o(.data+0x10c): Section mismatch in reference from the variable ppc_corenet_clk_driver to the variable .init.rodata:ppc_clk_ids
  The variable ppc_corenet_clk_driver references
  the variable __initconst ppc_clk_ids
  If the reference is valid then annotate the
  variable with __init* or __refdata (see linux/init.h) or name the variable:
  *_template, *_timer, *_sht, *_ops, *_probe, *_probe_one, *_console

We can't just add the __init annotation to ppc_corenet_clk_driver or
remove the __init from ppc_corenet_clk_probe() and ppc_clk_ids.
So choose to use CLK_OF_DECLARE to scan and init the clock devices.

Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-20 10:09:03 -08:00
Chen-Yu Tsai 7a6fca879f clk: sunxi: Add driver for A80 MMC config clocks/resets
On the A80 SoC, the 4 mmc controllers each have a separate register
controlling their register access clocks and reset controls. These
registers in turn share a ahb clock gate and reset control.

This patch adds a platform device driver for these controls. It
requires both clocks and reset controls to be available, so using
CLK_OF_DECLARE might not be the best way.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-20 17:14:38 +01:00
Chen-Yu Tsai 61af4d8dce clk: sunxi: Add mod0 and mmc module clock support for A80
The module 0 style clocks, or storage module clocks as named in the
official SDK, are almost the same as the module 0 clocks on earlier
Allwinner SoCs. The only difference is wider mux register bits.

As with earlier Allwinner SoCs, mmc module clocks are a special case
of mod0 clocks, with phase controls for 2 child clocks, output and
sample.

This patch adds support for both.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-19 22:48:55 +01:00
Krzysztof Kozlowski 27c76c4362 clk: exynos-audss: Fix memory leak on driver unbind or probe failure
The memory allocated by basic clock divider/gate/mux (struct clk_gate,
clk_divider and clk_mux) was leaking. During driver unbind or probe
failure the driver only unregistered the clocks.

Use clk_unregister_{gate,divider,mux} to release all resources.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17 13:52:41 -08:00
Krzysztof Kozlowski 4e3c021fb9 clk: Add clk_unregister_{divider, gate, mux} to close memory leak
The common clk_register_{divider,gate,mux} functions allocated memory
for internal data which wasn't freed anywhere. Drivers using these
helpers could only unregister clocks but the memory would still leak.

Add corresponding unregister functions which will release all resources.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17 13:52:41 -08:00
Max Filippov 0c7665c356 clk: TI CDCE706 clock synthesizer driver
The driver allows using CDCE706 in its default configuration recorded in
EEPROM and adjusting of synthesized clocks by consumers.

Signed-off-by: Max Filippov <jcmvbkbc@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17 13:52:40 -08:00
Stanimir Varbanov c7662fc59c clk: fix possible null pointer dereference
The commit 646cafc6 (clk: Change clk_ops->determine_rate to
return a clk_hw as the best parent) opens a possibility for
null pointer dereference, fix this.

Signed-off-by: Stanimir Varbanov <svarbanov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17 11:33:57 -08:00
Kevin Hao 176a107b86 Revert "clk: ppc-corenet: Fix Section mismatch warning"
This reverts commit da788acb28.

That commit tried to fix the section mismatch warning by moving the
ppc_corenet_clk_driver struct to init section. This is definitely wrong
because the kernel would free the memories occupied by this struct
after boot while this driver is still registered in the driver core.
The kernel would panic when accessing this driver struct.

Cc: stable@vger.kernel.org # 3.17
Signed-off-by: Kevin Hao <haokexin@gmail.com>
Acked-by: Scott Wood <scottwood@freescale.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-17 11:27:16 -08:00
Heiko Stübner a5e1baf7dc clk: rockchip: fix deadlock possibility in cpuclk
Lockdep reported a possible deadlock between the cpuclk lock and for example
the i2c driver.

       CPU0                    CPU1
       ----                    ----
  lock(clk_lock);
                               local_irq_disable();
                               lock(&(&i2c->lock)->rlock);
                               lock(clk_lock);
  <Interrupt>
    lock(&(&i2c->lock)->rlock);

 *** DEADLOCK ***

The generic clock-types of the core ccf already use spin_lock_irqsave when
touching clock registers, so do the same for the cpuclk.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed initialization of "flags"]
2015-01-17 11:22:39 -08:00
Alexandre Belloni 29ee506d0d ARM: at91: move at91rm9200_idle() to clk/at91/pmc.c
Move at91rm9200_idle() along with at91sam9_idle() in clk/at91/pmc.c.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2015-01-16 18:08:42 +01:00
Padmavathi Venna 9f930a39e1 clk: samsung: exynos7: add clocks for audio block
Add required clk support for I2S, PCM and SPDIF.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Reviewed-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 15:18:51 +01:00
Padmavathi Venna ee74b56ab2 clk: samsung: exynos7: add clocks for SPI block
Add clock support for 5 SPI channels.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 15:11:40 +01:00
Padmavathi Venna 9cc2a0c95f clk: samsung: exynos7: add gate clock for DMA block
Add support for PDMA0 and PDMA1 gate clks.

Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2015-01-15 15:11:40 +01:00
Chen-Yu Tsai eb378df79e clk: sunxi: Add a common setup function for mmc module clocks
The only difference between module clocks on different platforms is the
width of the mux register bits and the valid values, which are passed in
through struct factors_data. The phase clocks parts are identical.

This patch generalizes the setup function, so most of the code can be
reused when adding sun9i support, which has a wider mux register.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-14 17:26:03 +01:00
Maxime Ripard a7d19057e7 clk: sunxi: Remove custom phase function
Now that we don't have any user left for our custom phase function, we can
safely remove this hack from the code.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
2015-01-14 10:45:27 +01:00
Maxime Ripard 6b0b8ccff0 clk: sunxi: Rework MMC phase clocks
Instead of having three different clocks for the main MMC clock and the two
phase sub-clocks, which involved having three different drivers sharing the
same register, rework it to have the same single driver registering three
different clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Chen-Yu Tsai <wens@csie.org>
Tested-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
2015-01-14 10:39:16 +01:00
Wei Yongjun 16bd794f94 clk: shmobile: fix sparse NULL pointer warning
Fixes the following sparse warnings:

drivers/clk/shmobile/clk-sh73a0.c:57:17: warning:
 Using plain integer as NULL pointer

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2015-01-14 13:13:24 +09:00
Jisheng Zhang b71e8ecd57 clk: berlin: bg2q: remove non-exist "smemc" gate clock
The "smemc" clock is removed on BG2Q SoCs. In fact, bit19 of clkenable
register is for nfc. Current code use bit19 for non-exist "smemc"
incorrectly, this prevents eMMC from working due to the sdhci's
"core" clk is still gated.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Cc: stable@vger.kernel.org # 3.16+
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-13 10:58:43 -08:00
Boris Brezillon dca1a4b5ff clk: at91: keep slow clk enabled to prevent system hang
All slow clk users are not properly claiming it (get + prepare + enable)
before using it.
If all users properly claiming this clock release it, the clock is
disabled, but faulty users still depends on it, and the system hangs.

This fix prevents the slow clock from being disabled, and should solve the
hanging issue, but offending drivers should be patched to properly claim
this clock.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Bo Shen <voice.shen@atmel.com>
Cc: stable@vger.kernel.org
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2015-01-13 10:54:01 -08:00
Sergei Shtylyov 1484276119 clk: shmobile: Add R-Car Gen2 ADSP clock support
Add the ADSP clock support to the R-Car generation 2 CPG driver.  This clock
gets derived from  PLL1.  The layout of the ADSPCKCR register is  similar to
those of the clocks supported by the 'clk-div6' driver but the divider encoding
is non-linear, so can't be supported by that driver...

Based on the original patch by Konstantin Kozhevnikov
<konstantin.kozhevnikov@cogentembedded.com>.

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-01-08 16:14:31 +01:00
Sergei Shtylyov 90cf0e2b96 clk: shmobile: Add R-Car Gen2 RCAN clock support
Add the RCAN clock support to the R-Car generation 2 CPG driver.  This clock
gets derived from  the USB_EXTAL clock, dividing  it by 6.  The layout of the
RCANCKCR register is similar to those of the clocks supported by the 'clk-div6'
driver but has no divider field, and so can't be supported by that driver...

Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-01-08 16:14:31 +01:00
Ulrich Hecht 596bdcf778 clk: shmobile: r8a73a4 common clock framework implementation
Driver for the R8A73A4's clocks that are too specific to be supported by a
generic driver.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-01-08 16:14:30 +01:00
Hisashi Nakamura eb68343b3b clk: shmobile: Add r8a7793 support
R-Car M2N (r8a7793) clock is handled in R-Car Gen2 clock driver.

Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Signed-off-by: Yoshihiro Kaneko <ykaneko0929@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2015-01-08 16:14:29 +01:00
Geert Uytterhoeven 7980a86190 clk: shmobile: div6: Avoid changing divisor in .disable()
While DIV6 clocks require the divisor field to be non-zero when stopping
the clock, some clocks (e.g. ZB on sh73a0) fail to be re-enabled later
if the divisor field is changed when stopping the clock.
The reason for this is unknown.

To fix this, do not touch the divisor field if it's already non-zero.

On kzm9g, the smsc911x Ethernet controller is connected to the sh73a0
Bus State Controller, which is clocked by the ZB clock. Without this
fix, if the ZB clock is disabled during system suspend, and re-enabled
during resume, the kernel locks up when the smsc911x driver tries to
access the Ethernet registers.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
2015-01-08 16:13:19 +01:00
Pranith Kumar 83fe27ea53 rcu: Make SRCU optional by using CONFIG_SRCU
SRCU is not necessary to be compiled by default in all cases. For tinification
efforts not compiling SRCU unless necessary is desirable.

The current patch tries to make compiling SRCU optional by introducing a new
Kconfig option CONFIG_SRCU which is selected when any of the components making
use of SRCU are selected.

If we do not select CONFIG_SRCU, srcu.o will not be compiled at all.

   text    data     bss     dec     hex filename
   2007       0       0    2007     7d7 kernel/rcu/srcu.o

Size of arch/powerpc/boot/zImage changes from

   text    data     bss     dec     hex filename
 831552   64180   23944  919676   e087c arch/powerpc/boot/zImage : before
 829504   64180   23952  917636   e0084 arch/powerpc/boot/zImage : after

so the savings are about ~2000 bytes.

Signed-off-by: Pranith Kumar <bobby.prani@gmail.com>
CC: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
CC: Josh Triplett <josh@joshtriplett.org>
CC: Lai Jiangshan <laijs@cn.fujitsu.com>
Signed-off-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
[ paulmck: resolve conflict due to removal of arch/ia64/kvm/Kconfig. ]
2015-01-06 11:04:29 -08:00
Chen-Yu Tsai 3ec72fabcc clk: sunxi: Propagate rate changes to parent for mux clocks
The cpu clock on sunxi machines is just a mux clock, which is normally
fed by the main PLL, but can be muxed to the main or low power oscillator.

Make the mux clock propagate rate changes to its parent, so we can
change the clock rate of the PLL, and thus actually implement rate
changing on the cpu clock.

This patch also removes the no reparenting limit.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-06 17:00:15 +01:00
Hans de Goede 6ea3953da4 clk: sunxi: Make the mod0 clk driver also a platform driver
With the prcm in sun6i (and some later SoCs) some mod0 clocks are instantiated
through the mfd framework, and as such do not work with of_clk_declare, since
they do not have registers assigned to them yet at of_clk_declare init time.

Silence the error on not finding registers in the of_clk_declare mod0 clk
setup method, and also register mod0-clk support as a platform driver to work
properly with mfd instantiated mod0 clocks.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-06 10:31:35 +01:00
Hans de Goede b0f2faa5ca ARM: sunxi: Add "allwinner,sun6i-a31s" to mach-sunxi
So far the A31s is 100% compatible with the A31, still lets do the same
as what we've done for the A13 / A10s and give it its own compatible string,
in case we need to differentiate later.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
[Maxime: Removed unusude CPU_OF_DECLARE_METHOD]
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2015-01-05 09:50:39 +01:00
Roger Chen 7f186025c7 GMAC: modify CRU config for Rockchip RK3288 SoCs integrated GMAC
modify CRU config for GMAC driver

changes since v2:
1. remove SCLK_MAC_PLL

Signed-off-by: Roger Chen <roger.chen@rock-chips.com>
Signed-off-by: David S. Miller <davem@davemloft.net>
2014-12-31 19:14:18 -05:00
Doug Anderson a7d9500044 clk: rockchip: rk3288: Make s2r reliable by switching PLLs to slow mode
We've been seeing some crashes at resume time on rk3288-based systems.
On some machines they simply never wake up from suspend.  Symptoms
include:

- System clearly got to sleep OK.  Power consumption is low, the PWM
  for the PWM regulator has stopped, and the "global_pwroff" output
  shows that the system is down.

- When system tries to wake up power consumption goes up.

- No kernel resume code (which was left in PMU SRAM) ran.  We added
  some basic logging to this code (write to a location in SRAM right
  at resume time) and didn't see the logging run.

It appears that we can fix the problem by slowing down APLL before we
suspend.  On the system I tested things seemed reliable if I disabled
1.8GHz and 1.7GHz.  The Mask ROM itself tries to slow things down
(which is why PLLs are in slow mode by the time we get to the kernel),
but apparently it is crashing before it even gets there.

We'll be super paranoid and not just go down to 1.6GHz but we'll match
what the Mask ROM seems to be doing and go into slow mode.  We'll also
be safe and put all PLLs (not just APLL) into slow mode (well, except
DPLL which is needed for SDRAM).  We'll even put NPLL into slow mode
which the Mask ROM didn't do (not that it's used for much important
stuff at early resume time).

Note that the old Rockchip reference code did something just like
this, though they jammed it into pm.c instead of putting it in the
syscore ops of the clock driver.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-31 16:20:52 +01:00
Heiko Stuebner 9880d4277f clk: rockchip: fix rk3288 cpuclk core dividers
Commit 0e5bdb3f9f (clk: rockchip: switch to using the new cpuclk type
for armclk) didn't take into account that the divider used on rk3288
are of the (n+1) type.

The rk3066 and rk3188 socs use more complex divider types making it
necessary for the list-elements to be the real register-values to write.

Therefore reduce divider values in the table accordingly so that they
really are the values that should be written to the registers and match
the dividers actually specified for the rk3288.

Reported-by: Sonny Rao <sonnyrao@chromium.org>
Fixes: 0e5bdb3f9f ("clk: rockchip: switch to using the new cpuclk type for armclk")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Cc: stable@vger.kernel.org
2014-12-28 23:31:44 +01:00
Heiko Stuebner 12551f0239 clk: rockchip: fix rk3066 pll lock bit location
The bit locations indicating the locking status of the plls on rk3066 are
shifted by one to the right when compared to the rk3188, bits [7:4] instead
of [8:5] on the rk3188, thus indicating the locking state of the wrong pll
or a completely different information in case of the gpll.

The recently introduced pll init code exposed that problem on some rk3066
boards when it tried to bring the boot-pll value in line with the value
from the rate table.

Fix this by defining separate pll definitions for rk3066 with the correct
locking indices.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Fixes: 2c14736c75 ("clk: rockchip: add clock driver for rk3188 and rk3066 clocks")
Tested-by: FUKAUMI Naoki <naobsd@gmail.com>
Cc: stable@vger.kernel.org
2014-12-28 23:30:08 +01:00
Chanwoo Choi 01e5200d16 clk: samsung: exynos4415: Use samsung_cmu_register_one() to simplify code
This patch uses the samsung_cmu_register_one() to simplify code
for Exynos4415.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23 14:26:27 +01:00
Chanwoo Choi c913e1b32b clk: samsung: exynos3250: Use samsung_cmu_register_one() to simplify code
This patch uses the samsung_cmu_register_one() to simplify code
for Exynos3250.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23 14:25:52 +01:00
Chanwoo Choi 151d4d35f9 clk: samsung: Change the return value of samsung_cmu_register_one()
This patch changes the return value of samsung_cmu_register_one()
from 'void' to 'samsung_clk_provider structure' pointer type because
samsung_clk_provider may be used in each clock driver.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23 14:24:59 +01:00
Vivek Gautam 83f191a7cd clk: samsung: exynos7: Add required clock tree for USB
Adding required gate clocks for USB3.0 DRD controller
present on Exynos7.

Signed-off-by: Vivek Gautam <gautam.vivek@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23 12:02:14 +01:00
Tony K Nadackal 49cab82cb8 clk: samsung: exynos7: Add clocks for MSCL block
Add clock support for the MSCL block for Exynos7.

Signed-off-by: Tony K Nadackal <tony.kn@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-23 12:01:14 +01:00
Chen-Yu Tsai 66e79cf17e clk: sunxi: Fix factor clocks usage for sun9i core clocks
The sunxi factor clocks usage was changed in

    clk: sunxi: Give sunxi_factors_register a registers parameter

However the sun9i core clocks were not fixed up in that patch,
resulting in breakage. This patch fixes that.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Cc: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Hans de Goede 7c74c220e9 clk: sunxi: Give sunxi_factors_register a registers parameter
Before this commit sunxi_factors_register uses of_iomap(node, 0) to get
the clk registers. The sun6i prcm has factor clocks, for which we want to
use sunxi_factors_register, but of_iomap(node, 0) does not work for the prcm
factor clocks, because the prcm uses the mfd framework, so the registers
are not part of the dt-node, instead they are added to the platform_device,
as platform_device resources.

This commit makes getting the registers the callers duty, so that
sunxi_factors_register can be used with mfd instantiated platform device too.

While at it also add error checking to the of_iomap calls.

This commit also drops the __init function from sunxi_factors_register since
platform driver probe functions are not __init.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Chen-Yu Tsai 7954dfaee3 clk: sunxi: unify sun6i AHB1 clock with proper PLL6 pre-divider
This patch unifies the sun6i AHB1 clock, originally supported
with separate mux and divider clks. It also adds support for
the pre-divider on the PLL6 input, thus allowing the clock to
be muxed to PLL6 with proper clock rate calculation.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Chen-Yu Tsai 75bd2ec1a6 clk: sunxi: Remove ahb1_sdram from sun6i/sun8i protected clocks list
The ahb1_sdram clock gate is only used for accessing the sdram
controller's registers over the bus. It is not used for actually clock
the controller or the dram, hence it does not need to be protected.

This also gets rid of the problem when the protected ahb1_sdram gate
is prepared/enabled while it is still an orphan, and the operation
is not propagated to the correct parent.

This was confirmed on my A23 tablet and my A31 Hummingbird.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-12-21 23:51:37 +01:00
Romain Perier 5039d16abe clk: rockchip: Fix clock gate for rk3188 hclk_emem_peri
Do not disable clock gate "hclk_emem_peri", otherwise EMAC clocks no longer work
and it breaks ethernet on RK3066 and RK3188. It fixes a regression introduced by
commit 78eaf6095c ("clk: rockchip: disable unused clocks").

Signed-off-by: Romain Perier <romain.perier@gmail.com>
Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 15:21:28 +01:00
Julien CHAUVEAU caa6934ac7 clk: rockchip: add CLK_IGNORE_UNUSED flag to fix rk3066/rk3188 USB Host
This patch adds CLK_IGNORE_UNUSED flag to hclk_usb_peri, hclk_usbotg0
and hclk_usbotg1 because these clocks must remain enabled to use the
USB controllers in host mode.

This fixes a regression introduced by commit 78eaf6095c
("clk: rockchip: disable unused clocks").

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Fixes: 78eaf6095c ("clk: rockchip: disable unused clocks")
Reviewed-by: Romain Perier <romain.perier@gmail.com>
Tested-by: Romain Perier <romain.perier@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 15:18:24 +01:00
Doug Anderson 221dfbae2b clk: rockchip: Add CLK_SET_RATE_PARENT to sclk_uart clocks
We'd like to be able to set the clock rate of the sclk_uart clocks and
actually be able to achieve clock rates greater than 24MHz.  To do
this we need to be able to pass rate changes upward.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-12-21 14:15:26 +01:00
Ulrich Hecht ae073881aa clk: shmobile: sh73a0 common clock framework implementation
Driver for the SH73A0's clocks that are too specific to be supported by a
generic driver.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Tested-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-12-21 17:09:20 +09:00
Linus Torvalds bfc7249cc2 Please consider pulling the clk framework changes toward 3.19. It is
much later than usual due to several last minute bugs that had to be
 addressed. As usual the majority of changes are new drivers and
 modifications to existing drivers. The core recieved many fixes along
 with the groundwork for several large changes coming in the future which
 will better parition clock providers from clock consumers.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUlMRQAAoJEDqPOy9afJhJgdUQAK4myJT0q10LSqe9piwzGVXg
 uDcIN5CTtbdYkvdGIfCjeqz3t+DClnAMPx2ZPIjC0Z1mIvqq+ViqwP5U8kKd7z1a
 WCKV8e5Et3O1WNbslzsx5Z2JYJNgzqr1xxWAOLTLh5rYxVwE5b946Yv4Whxa694I
 ugm4wNlibeN3H8pnyH8YEiWEtahtu7B5v/9WELpyREwNxw7ZA18MttEvWaamAPHG
 rAxhQCB3A3HaIvyg8KFdVmwOBZQMc2EWT00kJfdRWL4/iGAipKCnbuh1c8Pr/RQE
 XRg5Y+MuMLotoUELYYeZHtEmIlW3A+9gR6tLivswPpOP8/5BVUyA5Hh0yCGUqUHD
 s5Iheq7s7xnKEgIu9cD4tf1nCY41gw+4/I4pm47WLkaRgehcEBcAibVC3CupZ5pI
 hJiFqEKWPKEk8vAJ/mM+wCGI4w01+eoICBm4EG06Nwj4xkQcAVqE67ZvgVs1LrmL
 efqSxkWpNoetf0Q12cfePHmWtesGNdvljLdXQ54T4qH9HxNaI9/9eM6tyFTfrDSe
 BG5h7gbPr6/aM/1FfcWn5jQIfjEjPhQtSpCehs8pMf/pG5QZgftBtwe3p+yz7zXJ
 Q/v8xNEcZ7Ze6/9rJsAcbLzyzcdk9NzTlEMplzGBoUQFNiEXKoIjCDKAx39UFtMz
 EccWXvt9iNZZhmDcu0pU
 =jD84
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux

Pull clk framework updates from Mike Turquette:
 "This is much later than usual due to several last minute bugs that had
  to be addressed.  As usual the majority of changes are new drivers and
  modifications to existing drivers.  The core recieved many fixes along
  with the groundwork for several large changes coming in the future
  which will better parition clock providers from clock consumers"

* tag 'clk-for-linus-3.19' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
  ARM: OMAP3: clock: fix boot breakage in legacy mode
  ARM: OMAP2+: clock: fix DPLL code to use new determine rate APIs
  clk: Really fix deadlock with mmap_sem
  clk: mmp: fix sparse non static symbol warning
  clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
  clk: change clk_debugfs_add_file to take a struct clk_hw
  clk: Don't expose __clk_get_accuracy
  clk: Don't try to use a struct clk* after it could have been freed
  clk: Remove unused function __clk_get_prepare_count
  clk: samsung: Fix double add of syscore ops after driver rebind
  clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
  clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
  clk: samsung: remove unnecessary inclusion of header files from clk.h
  clk: samsung: remove unnecessary CONFIG_OF from clk.c
  clk: samsung: Spelling s/bwtween/between/
  clk: rockchip: Add support for the mmc clock phases using the framework
  clk: rockchip: add bindings for the mmc clocks
  clk: rockchip: rk3288 export i2s0_clkout for use in DT
  clk: rockchip: use clock ID for DMC (memory controller) on rk3288
  ...
2014-12-20 16:42:36 -08:00
Krzysztof Kozlowski f1e9203e23 clk: samsung: Fix Exynos 5420 pinctrl setup and clock disable failure due to domain being gated
Audio subsystem clocks are located in separate block. On Exynos 5420 if
clock for this block (from main clock domain) 'mau_epll' is gated then
any read or write to audss registers will block.

This kind of boot hang was observed on Arndale Octa and Peach Pi/Pit
after introducing runtime PM to pl330 DMA driver. After that commit the
'mau_epll' was gated, because the "amba" clock was disabled and there
were no more users of mau_epll.

The system hang on one of steps:
1. Disabling unused clocks from audss block.
2. During audss GPIO setup (just before probing i2s0 because
   samsung_pinmux_setup() tried to access memory from audss block which was
   gated.

Add a workaround for this by enabling the 'mau_epll' clock in probe.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Tested-by: Kevin Hilman <khilman@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-17 07:31:51 -08:00
Michael Turquette b1924c2ec1 Merge tag 'for-v3.19/omap-a' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into tmp
Some OMAP clock/hwmod patches for v3.19.

Most of the patches are clock-related.  The DPLL implementation is
changed to better align to the common clock framework.
There is also a patch that removes a few lines from the hwmod code -
this patch should have no functional effect.

Basic build, boot, and PM test logs for these patches can be found here:

http://www.pwsan.com/omap/testlogs/omap-a-for-v3.19/20141113094101/
2014-12-15 17:05:07 -08:00
Stephen Boyd 89f7e9de59 clk: Really fix deadlock with mmap_sem
Commit 6314b6796e (clk: Don't hold prepare_lock across debugfs
creation, 2014-09-04) forgot to update one place where we hold
the prepare_lock while creating debugfs directories. This means
we still have the chance of a deadlock that the commit was trying
to fix. Actually fix it by moving the debugfs creation outside
the prepare_lock.

Cc: <stable@vger.kernel.org> # 3.18
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Fixes: 6314b6796e "clk: Don't hold prepare_lock across debugfs creation"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed lockdep_assert]
2014-12-15 17:02:06 -08:00
Linus Torvalds e6b5be2be4 Driver core patches for 3.19-rc1
Here's the set of driver core patches for 3.19-rc1.
 
 They are dominated by the removal of the .owner field in platform
 drivers.  They touch a lot of files, but they are "simple" changes, just
 removing a line in a structure.
 
 Other than that, a few minor driver core and debugfs changes.  There are
 some ath9k patches coming in through this tree that have been acked by
 the wireless maintainers as they relied on the debugfs changes.
 
 Everything has been in linux-next for a while.
 
 Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iEYEABECAAYFAlSOD20ACgkQMUfUDdst+ylLPACg2QrW1oHhdTMT9WI8jihlHVRM
 53kAoLeteByQ3iVwWurwwseRPiWa8+MI
 =OVRS
 -----END PGP SIGNATURE-----

Merge tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core

Pull driver core update from Greg KH:
 "Here's the set of driver core patches for 3.19-rc1.

  They are dominated by the removal of the .owner field in platform
  drivers.  They touch a lot of files, but they are "simple" changes,
  just removing a line in a structure.

  Other than that, a few minor driver core and debugfs changes.  There
  are some ath9k patches coming in through this tree that have been
  acked by the wireless maintainers as they relied on the debugfs
  changes.

  Everything has been in linux-next for a while"

* tag 'driver-core-3.19-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (324 commits)
  Revert "ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries"
  fs: debugfs: add forward declaration for struct device type
  firmware class: Deletion of an unnecessary check before the function call "vunmap"
  firmware loader: fix hung task warning dump
  devcoredump: provide a one-way disable function
  device: Add dev_<level>_once variants
  ath: ath9k: use debugfs_create_devm_seqfile() helper for seq_file entries
  ath: use seq_file api for ath9k debugfs files
  debugfs: add helper function to create device related seq_file
  drivers/base: cacheinfo: remove noisy error boot message
  Revert "core: platform: add warning if driver has no owner"
  drivers: base: support cpu cache information interface to userspace via sysfs
  drivers: base: add cpu_device_create to support per-cpu devices
  topology: replace custom attribute macros with standard DEVICE_ATTR*
  cpumask: factor out show_cpumap into separate helper function
  driver core: Fix unbalanced device reference in drivers_probe
  driver core: fix race with userland in device_add()
  sysfs/kernfs: make read requests on pre-alloc files use the buffer.
  sysfs/kernfs: allow attributes to request write buffer be pre-allocated.
  fs: sysfs: return EGBIG on write if offset is larger than file size
  ...
2014-12-14 16:10:09 -08:00
Linus Torvalds a7cb7bb664 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial
Pull trivial tree update from Jiri Kosina:
 "Usual stuff: documentation updates, printk() fixes, etc"

* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/jikos/trivial: (24 commits)
  intel_ips: fix a type in error message
  cpufreq: cpufreq-dt: Move newline to end of error message
  ps3rom: fix error return code
  treewide: fix typo in printk and Kconfig
  ARM: dts: bcm63138: change "interupts" to "interrupts"
  Replace mentions of "list_struct" to "list_head"
  kernel: trace: fix printk message
  scsi: mpt2sas: fix ioctl in comment
  zbud, zswap: change module author email
  clocksource: Fix 'clcoksource' typo in comment
  arm: fix wording of "Crotex" in CONFIG_ARCH_EXYNOS3 help
  gpio: msm-v1: make boolean argument more obvious
  usb: Fix typo in usb-serial-simple.c
  PCI: Fix comment typo 'COMFIG_PM_OPS'
  powerpc: Fix comment typo 'CONIFG_8xx'
  powerpc: Fix comment typos 'CONFiG_ALTIVEC'
  clk: st: Spelling s/stucture/structure/
  isci: Spelling s/stucture/structure/
  usb: gadget: zero: Spelling s/infrastucture/infrastructure/
  treewide: Fix company name in module descriptions
  ...
2014-12-12 10:08:06 -08:00
Linus Torvalds c0222ac086 Merge branch 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus
Pull MIPS updates from Ralf Baechle:
 "This is an unusually large pull request for MIPS - in parts because
  lots of patches missed the 3.18 deadline but primarily because some
  folks opened the flood gates.

   - Retire the MIPS-specific phys_t with the generic phys_addr_t.
   - Improvments for the backtrace code used by oprofile.
   - Better backtraces on SMP systems.
   - Cleanups for the Octeon platform code.
   - Cleanups and fixes for the Loongson platform code.
   - Cleanups and fixes to the firmware library.
   - Switch ATH79 platform to use the firmware library.
   - Grand overhault to the SEAD3 and Malta interrupt code.
   - Move the GIC interrupt code to drivers/irqchip
   - Lots of GIC cleanups and updates to the GIC code to use modern IRQ
     infrastructures and features of the kernel.
   - OF documentation updates for the GIC bindings
   - Move GIC clocksource driver to drivers/clocksource
   - Merge GIC clocksource driver with clockevent driver.
   - Further updates to bring the GIC clocksource driver up to date.
   - R3000 TLB code cleanups
   - Improvments to the Loongson 3 platform code.
   - Convert pr_warning to pr_warn.
   - Merge a bunch of small lantiq and ralink fixes that have been
     staged/lingering inside the openwrt tree for a while.
   - Update archhelp for IP22/IP32
   - Fix a number of issues for Loongson 1B.
   - New clocksource and clockevent driver for Loongson 1B.
   - Further work on clk handling for Loongson 1B.
   - Platform work for Broadcom BMIPS.
   - Error handling cleanups for TurboChannel.
   - Fixes and optimization to the microMIPS support.
   - Option to disable the FTLB.
   - Dump more relevant information on machine check exception
   - Change binfmt to allow arch to examine PT_*PROC headers
   - Support for new style FPU register model in O32
   - VDSO randomization.
   - BCM47xx cleanups
   - BCM47xx reimplement the way the kernel accesses NVRAM information.
   - Random cleanups
   - Add support for ATH25 platforms
   - Remove pointless locking code in some PCI platforms.
   - Some improvments to EVA support
   - Minor Alchemy cleanup"

* 'upstream' of git://git.linux-mips.org/pub/scm/ralf/upstream-linus: (185 commits)
  MIPS: Add MFHC0 and MTHC0 instructions to uasm.
  MIPS: Cosmetic cleanups of page table headers.
  MIPS: Add CP0 macros for extended EntryLo registers
  MIPS: Remove now unused definition of phys_t.
  MIPS: Replace use of phys_t with phys_addr_t.
  MIPS: Replace MIPS-specific 64BIT_PHYS_ADDR with generic PHYS_ADDR_T_64BIT
  PCMCIA: Alchemy Don't select 64BIT_PHYS_ADDR in Kconfig.
  MIPS: lib: memset: Clean up some MIPS{EL,EB} ifdefery
  MIPS: iomap: Use __mem_{read,write}{b,w,l} for MMIO
  MIPS: <asm/types.h> fix indentation.
  MAINTAINERS: Add entry for BMIPS multiplatform kernel
  MIPS: Enable VDSO randomization
  MIPS: Remove a temporary hack for debugging cache flushes in SMTC configuration
  MIPS: Remove declaration of obsolete arch_init_clk_ops()
  MIPS: atomic.h: Reformat to fit in 79 columns
  MIPS: Apply `.insn' to fixup labels throughout
  MIPS: Fix microMIPS LL/SC immediate offsets
  MIPS: Kconfig: Only allow 32-bit microMIPS builds
  MIPS: signal.c: Fix an invalid cast in ISA mode bit handling
  MIPS: mm: Only build one microassembler that is suitable
  ...
2014-12-11 17:56:37 -08:00
Michael Turquette c9b928148e - exynos4415 and exynos audio subsystem clk driver (build
with PM_SLEEP disabled, resource release) fixes
 - minor cleanups in drivers/clk/samsung/clk.c (spelling,
   includes)
 - modification of the exynos4 HDMI PHY clock definition to
   model dependency of "sclk_hdmiphy" on the "hdmi" clock
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABCAAGBQJUgZiKAAoJEE1bIKeAnHqL5AUP/2X0OnwWJYLskaNuFH622OQ5
 4AoKqdHxvVQIZZg9zlgxnxeegms5GzDDq/FEgUvzNQ4rIJWQTxkx14fBiLBLg4MI
 fljJ4IQ08sPKSrydmHVwrEVijoCH725o44pkaqn3xHjBWizOrdj9lnXEGlwUuZ4x
 uDoJ3LLwFav6OItI/abYHCuML4crMl7hJW4ltko4/7H4s1HIRlTKxRVPvCyYohdA
 gkA+4bFWjGELe0mnxO0Hlh48+tnsjjUUuAjWxfiOIcW2mOQS6ugCj7pLEIqbpEHu
 6d8Od1EH2GLTTqcMLPwiwqhze85802jTPBw3UL3XNQc1XBa+vUtEzapUDP6mRE6D
 KUvtqDStkUsjM1rflcd6P4MA5Z1PT9yuzW03mjuLl4J+sfHaYSaw1FfIE5GuUw/J
 w6ICdsuiEM2NZvp7OAzyWeT/skAYmhcFYy31yCulPBaRIGKCw0qJijBLT/4GVqoK
 TiLqbqOSuNvv2Dvbo+pQ6qvx8EZUK5zZBUks/wDvKyVXnkm6w5pOdSEELF6bbtN/
 7pOkjdY/3soWStRBcKV9cyGvpwc3FD3tn0hptfqxXzbJlyitYVwcwpacTdJATjK8
 6hMi3YlRYFGG8uqpg1IcKH/NooIhDW1eK7maRdq9ZsEWoJd+vr5pa7z+2urjV104
 8dZ9Bq/L6HcD7IrQsRV6
 =Q2e2
 -----END PGP SIGNATURE-----

Merge tag 'for-v3.19-exynos-clk-2' of git://linuxtv.org/snawrocki/samsung into clk-next

- exynos4415 and exynos audio subsystem clk driver (build
  with PM_SLEEP disabled, resource release) fixes
- minor cleanups in drivers/clk/samsung/clk.c (spelling,
  includes)
- modification of the exynos4 HDMI PHY clock definition to
  model dependency of "sclk_hdmiphy" on the "hdmi" clock
2014-12-11 12:17:15 -08:00
Wei Yongjun 74fc23aa40 clk: mmp: fix sparse non static symbol warning
Fixes the following sparse warnings:

drivers/clk/mmp/clk-frac.c:113:6: warning:
 symbol 'clk_factor_init' was not declared. Should it be static?

Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-11 12:14:09 -08:00
Linus Torvalds 3a647c1d7a ARM: SoC driver updates for 3.19
These are changes for drivers that are intimately tied to some SoC
 and for some reason could not get merged through the respective
 subsystem maintainer tree.
 
 The largest single change here this time around is the Tegra
 iommu/memory controller driver, which gets updated to the new
 iommu DT binding. More drivers like this are likely to follow
 for the following merge window, but we should be able to do
 those through the iommu maintainer.
 
 Other notable changes are:
 * reset controller drivers from the reset maintainer (socfpga, sti, berlin)
 * fixes for the keystone navigator driver merged last time
 * at91 rtc driver changes related to the at91 cleanups
 * ARM perf driver changes from Will Deacon
 * updates for the brcmstb_gisb driver
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAVIcj4mCrR//JCVInAQIvWg//WD72+2q0RmEvu8r/YN4SDfg5iY7OMzgy
 Jyt6rN1IhXBY5GJL5Hil1q2JP/7o8vypekllohmBYWzXO3ZJ2VK6NPIXEMuzaiCz
 D9gmb+N6FdR2L2iYPv7B/3uOf55pHjBu525+vLspCTOgcWBrLgCnA9e9Yg462AEf
 VP3x+kV0AH25lovEi3mPrc2e46jnl0Mzp3f3PCkPqRSEMn7sxu9ipii+elxvArYp
 jYYCB03ZEBFa7T0e4HD38gnVLbC6dTj47AcSCWYP9WhxJ2RmCQKRBEnJre02hgar
 NPg8z+OrUACIAkvJHzg3WccmXdi0aqQ2JDsl46Tkl7pA6NdyMLfizT3OiZnMRmgc
 34H0ZSxclW+j25aI8OmDpv2ypZev+UAzkbRobcvF+aV/zJeAX88tPgcshfCUVZll
 ZIqO7oJB73nCl1XBLv2ZrLV2tcOox6jL/5LQt0WYA5Szg5upo7D1fZl8v5jXX7eJ
 C62ychuABs6hsmH5jEy+73kdpHbYft7dZfGZxdgq1AIOkdWoynCze/R7Vj24xoXR
 118cTNN9ZTPHmN5yxUvuGoqA3FWOqkJXaTS4W0hRD6OxOGTsTV4FIlRnD+K7feOW
 ng1yfIcvKR1Dx7tsySTHQK+bZGNnovA/ENPK6VDuhbwE62Lx7N5hcbsSIKKwRI9C
 D1m1fC+AIcQ=
 =MwMG
 -----END PGP SIGNATURE-----

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  The largest single change here this time around is the Tegra
  iommu/memory controller driver, which gets updated to the new iommu DT
  binding.  More drivers like this are likely to follow for the
  following merge window, but we should be able to do those through the
  iommu maintainer.

  Other notable changes are:
   - reset controller drivers from the reset maintainer (socfpga, sti,
     berlin)
   - fixes for the keystone navigator driver merged last time
   - at91 rtc driver changes related to the at91 cleanups
   - ARM perf driver changes from Will Deacon
   - updates for the brcmstb_gisb driver"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (53 commits)
  clocksource: arch_timer: Allow the device tree to specify uninitialized timer registers
  clocksource: arch_timer: Fix code to use physical timers when requested
  memory: Add NVIDIA Tegra memory controller support
  bus: brcmstb_gisb: Add register offset tables for older chips
  bus: brcmstb_gisb: Look up register offsets in a table
  bus: brcmstb_gisb: Introduce wrapper functions for MMIO accesses
  bus: brcmstb_gisb: Make the driver buildable on MIPS
  of: Add NVIDIA Tegra memory controller binding
  ARM: tegra: Move AHB Kconfig to drivers/amba
  amba: Add Kconfig file
  clk: tegra: Implement memory-controller clock
  serial: samsung: Fix serial config dependencies for exynos7
  bus: brcmstb_gisb: resolve section mismatch
  ARM: common: edma: edma_pm_resume may be unused
  ARM: common: edma: add suspend resume hook
  powerpc/iommu: Rename iommu_[un]map_sg functions
  rtc: at91sam9: add DT bindings documentation
  rtc: at91sam9: use clk API instead of relying on AT91_SLOW_CLOCK
  ARM: at91: add clk_lookup entry for RTT devices
  rtc: at91sam9: rework the Kconfig description
  ...
2014-12-09 14:48:22 -08:00
Linus Torvalds 6cd94d5e57 ARM: SoC platform changes for 3.19
New and updated SoC support, notable changes include:
 
 * bcm: brcmstb SMP support
 * bcm: initial iproc/cygnus support
 * exynos: Exynos4415 SoC support
 * exynos: PMU and suspend support for Exynos5420
 * exynos: PMU support for Exynos3250
 * exynos: pm related maintenance
 * imx: new LS1021A SoC support
 * imx: vybrid 610 global timer support
 * integrator: convert to using multiplatform configuration
 * mediatek: earlyprintk support for mt8127/mt8135
 * meson: meson8 soc and l2 cache controller support
 * mvebu: Armada 38x CPU hotplug support
 * mvebu: drop support for prerelease Armada 375 Z1 stepping
 * mvebu: extended suspend support, now works on Armada 370/XP
 * omap: hwmod related maintenance
 * omap: prcm cleanup
 * pxa: initial pxa27x DT handling
 * rockchip: SMP support for rk3288
 * rockchip: add cpu frequency scaling support
 * shmobile: r8a7740 power domain support
 * shmobile: various small restart, timer, pci apmu changes
 * sunxi: Allwinner A80 (sun9i) earlyprintk support
 * ux500: power domain support
 
 Overall, a significant chunk of changes, coming mostly from
 the usual suspects: omap, shmobile, samsung and mvebu, all of
 which already contain a lot of platform specific code in
 arch/arm.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAVIcjyGCrR//JCVInAQJJCRAA1Tm+HZGiAiTvXEAcm/T9tIA08uqtawHt
 cqyEAUyrnE8QxE4EhUd2pTw4EunVusqKF5EsDxOzw7b3ukUdLAWZE7bqBOSIJLqn
 hrfsQQ8dXLbyC7T/CHPnBVeM+pn9LiIc9qzpZ0YToiMnHBBI4vKFQntBjd31yoRE
 hN08I6AmDjQolOzzlqR1fuM0uZaKiHIcytdauTt3Vfqgg7FTHcTy3u1kClHTR1Lp
 m/KuDothGpR5OKjSnUQz7EO5V3KJEnaKey8z2xM1a7DLLAvJ6r2+DUaDopv9Dbz1
 W/V3H7fi5tLvillVa8xmlmzqWZbPc1xw8MWqvHZSWIMRZqloAHpC1VWKn0ZuH4SW
 5Bj4ubSrpYjJxjKYfrxtjmuzru3A2jWBNTSP5A4nsny0C3AUsXkfRmRS0VNdegF8
 sUdQ1MF8vEMpQT3QPH88+ccFHeIgqbcayhKqLPf7r8q0kwlym5N7Y2amU2A/O6qz
 +324r+yzfSA70VgJZ5EhXxWVDOPB4Lc8EtoWnH6T/kjncIMwzEsbEbyB3X1OaREW
 pVn3PNo06VjHLYoiHX+8G99pOFR/JZvaQs6jGCXLs+Orjp5WfP+kafkWqcB5GAKU
 Pfd3AQsl6rKAITdu0XsTdPiICNS4CmBiWYPepQsTa3pQaNgB7fwZNQKelNRIdGc+
 dF1lnQ7CXLQ=
 =lFoH
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Arnd Bergmann:
 "New and updated SoC support, notable changes include:

   - bcm:
        brcmstb SMP support
        initial iproc/cygnus support
   - exynos:
        Exynos4415 SoC support
        PMU and suspend support for Exynos5420
        PMU support for Exynos3250
        pm related maintenance
   - imx:
        new LS1021A SoC support
        vybrid 610 global timer support
   - integrator:
        convert to using multiplatform configuration
   - mediatek:
        earlyprintk support for mt8127/mt8135
   - meson:
        meson8 soc and l2 cache controller support
   - mvebu:
        Armada 38x CPU hotplug support
        drop support for prerelease Armada 375 Z1 stepping
        extended suspend support, now works on Armada 370/XP
   - omap:
        hwmod related maintenance
        prcm cleanup
   - pxa:
        initial pxa27x DT handling
   - rockchip:
        SMP support for rk3288
        add cpu frequency scaling support
   - shmobile:
        r8a7740 power domain support
        various small restart, timer, pci apmu changes
   - sunxi:
        Allwinner A80 (sun9i) earlyprintk support
   - ux500:
        power domain support

  Overall, a significant chunk of changes, coming mostly from the usual
  suspects: omap, shmobile, samsung and mvebu, all of which already
  contain a lot of platform specific code in arch/arm"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (187 commits)
  ARM: mvebu: use the cpufreq-dt platform_data for independent clocks
  soc: integrator: Add terminating entry for integrator_cm_match
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  ARM: add lolevel debug support for asm9260
  ARM: add mach-asm9260
  ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
  power: reset: imx-snvs-poweroff: add power off driver for i.mx6
  ARM: imx: temporarily remove CONFIG_SOC_FSL from LS1021A
  ...
2014-12-09 14:38:28 -08:00
Linus Torvalds 6c9e92476b ARM: SoC cleanups for 3.19
The remaining cleanups for 3.19 are to a large part result of
 devicetree conversion nearing completion on two other platforms
 besides AT91:
 
 * Like AT91, Renesas shmobile is in the process to migrate to DT and
   multiplatform, but using a different approach of doing it one
   SoC at a time. For 3.19, the r8a7791 platform and associated\
   "Koelsch" board are considered complete and we remove the non-DT
   non-multiplatform support for this.
 
 * The ARM Versatile Express has supported DT and multiplatform
   for a long time, but we have still kept the legacy board files
   around, because not all drivers were fully working before. We
   have finally taken the last step to remove the board files.
 
 Other changes in this branch are preparation for the later branches
 or just unrelated to the more interesting changes:
 * The dts files for arm64 get moved into per-vendor directories for
   a clearer structure.
 * Some dead code removal (zynq, exynos, davinci, imx)
 * Using pr_*() macros more consistently instead of printk(KERN_*)
   in some platform code.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAVIdpgGCrR//JCVInAQIr/BAA3UZvPPf5dwy5OkULPTghvWueeL9NWZHr
 8KwNWIIkIzCgr8zUf2HrMRRLtG429WQWHWxNA+TH9HpcHFGo/zJDBPaJ63cb3Rv1
 YLDGJ0zYPXjOsiWUWHm2M5B4hWj0Is5CwYnuozcpLykzQ9QsLMTIv2CAXoJXpH9S
 sAdx/B5e9G7IqzlJRgbvCPNAZleLYUneYoIW5L68MaFIjfKXVrHzY6w0CJFt/UDa
 CVbP0iwVQNnL1Opr3ABAkBkJ7rrFU17jpBWMtrNsyyMCZQADiV5Z4+IBnW0uWSZj
 zn92dycwOSYRmrgOrI2J6r5vFtxWRyWfR5Au5rD02oQTIucGiLmaKMV5gNhoQrEq
 v53IknDZzqv+xbiARGnJKGdJs70AYjrurpNgXXzJt3W4dZ6vssotxhiYEXbpPPDN
 v5QxrOStePY+qBHeMLuQi8VoV9SI+j/YAiaXak4QWmiGHVDzvBfZ2P3wMCbj04Jp
 oxCZ6IGMczYwvqQ8vWXJOueLm+IfM0GcEFwslUwO95rMRMv7JRCXdvfNhL7wLlu8
 f2Hd/Pk/u0bOUQXhZlFKNRFg78t4hgD1hMKHgmpEDTZ8P1XMuIrWoQu0xkSQZsYG
 MiGIqwRd5Ow9OWzWq3DNJ4EjhmvPYv2X/Dcvu7Jv4yq1zZQ8G6OnWkmWWn5ghq6M
 grvB27RnbuE=
 =Apdh
 -----END PGP SIGNATURE-----

Merge tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Arnd Bergmann:
 "The remaining cleanups for 3.19 are to a large part result of
  devicetree conversion nearing completion on two other platforms
  besides AT91:

   - Like AT91, Renesas shmobile is in the process to migrate to DT and
     multiplatform, but using a different approach of doing it one SoC
     at a time.  For 3.19, the r8a7791 platform and associated "Koelsch"
     board are considered complete and we remove the non-DT
     non-multiplatform support for this.

   - The ARM Versatile Express has supported DT and multiplatform for a
     long time, but we have still kept the legacy board files around,
     because not all drivers were fully working before.  We have finally
     taken the last step to remove the board files.

  Other changes in this branch are preparation for the later branches or
  just unrelated to the more interesting changes:

   - The dts files for arm64 get moved into per-vendor directories for a
     clearer structure.

   - Some dead code removal (zynq, exynos, davinci, imx)

   - Using pr_*() macros more consistently instead of printk(KERN_*) in
     some platform code"

* tag 'cleanup-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (71 commits)
  ARM: zynq: Remove secondary_startup() declaration from header
  ARM: vexpress: Enable regulator framework when MMCI is in use
  ARM: vexpress: Remove non-DT code
  ARM: imx: Remove unneeded .map_io initialization
  ARM: dts: imx6qdl-sabresd: Fix the microphone route
  ARM: imx: refactor mxc_iomux_mode()
  ARM: imx: simplify clk_pllv3_prepare()
  ARM: imx6q: drop unnecessary semicolon
  ARM: imx: clean up machine mxc_arch_reset_init_dt reset init
  ARM: dts: imx6qdl-rex: Remove unneeded 'fsl,mode' property
  ARM: dts: imx6qdl-gw5x: Remove unneeded 'fsl,mode' property
  ARM: dts: imx6qdl-sabresd: Use IMX6QDL_CLK_CKO define
  ARM: at91: remove useless init_time for DT-only SoCs
  ARM: davinci: Remove redundant casts
  ARM: davinci: Use standard logging styles
  ARM: shmobile: r8a7779: Spelling/grammar s/entity/identity/, s/map/mapping/
  ARM: shmobile: sh7372: Spelling/grammar s/entity map/identity mapping/
  ARM: shmobile: sh73a0: Spelling/grammar s/entity map/identity mapping/
  ARM: EXYNOS: Remove unused static iomapping
  ARM: at91: fix build breakage due to legacy board removals
  ...
2014-12-09 14:18:35 -08:00
Linus Torvalds 3a7dbed7f2 Hi Linus,
Changes to the core:
  - Honour PLATFORM_DEVID_NONE and PLATFORM_DEVID_AUTO dev IDs
 
 Changes to existing drivers:
  - IRQ additions/fixes; axp20x, da9063-core
  - Code simplification; i2c-dln2
  - Regmap additions/fixes; max77693
  - Error checking/handling improvements; dln2, db8500-prcmu
  - Bug fixes; dln2, wm8350-core
  - DT support/documentation; max77693, max77686, tps65217, twl4030-power,
                              gpio-tc3589x
  - Decouple syscon interface from platform devices
  - Use MFD hotplug registration; rtsx_usb, viperboard, hid-sensor-hub
  - Regulator fixups; sec-core
  - Power Management additions/fixes; rts5227, tc6393xb
  - Remove relic/redundant code; ab8500-sysctrl, lpc_sch, max77693-private
  - Clean-up/coding style changes; tps65090
  - Clk additions/fixes; tc6393xb, tc6387xb, t7l66xb
  - Add USB-SPI support; dln2
  - Trivial changes; max14577, arizona-spi, lpc_sch, wm8997-tables, wm5102-tables
                     wm5110-tables, axp20x, atmel-hlcdc, rtsx_pci
 
 New drivers/supported devices:
  - axp288 PMIC support added to axp20x
  - s2mps13 support added to sec-core
  - New support for Diolan DLN-2
  - New support for atmel-hlcdc
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUhZDaAAoJEFGvii+H/HdhEY4P+gOlEIU+LYDdKmRjXLp85+ZS
 zrkLQdxvRp61LzzcIMGnduPFAOk8ixb3nRqSJv7P5WQG26I6qoI44zeTF2iSmLTp
 iVLtXRFSlo/lRyWT+2jXwL5iC47PCoJuJajNeM/YEbMERR3sWWAPrATZrQSPoKcZ
 D3qtXge3d+zq2rqpSvNAFNPEC4i9xawwa9GHMte9T/XhaoyVhaK6ITMsh0RK4B0p
 RRc2zy9BGEkuZMu3aC7P/qhfu3uSrxzI6FCHNSbZt/p5aq8klMBGqpK9Tgg4UHUG
 jqAd2lCXHVSVI07CO0YvVUDWV+5NlB1kAeRddohJujV9o5ciaqKCGPKK1Fz0PMxf
 u30t0X4Fb4QCAZVeo1hX9KWKQaQinUzPhANT4Sz0DY1S7arZ6PlJO/obGIys5JCf
 ElJuYNSRqRp6DcaoTHf19DUcxJXnqk73PU3hmsdS4UkweBWDYeagK2gqDwjIhAY6
 DJZ5uqaa829fx/Jj8sUo0EgWZs/Cahf/td7y35fM4bMgU+vHd1xeBvMeltiJ2kuC
 OoZwtyHbV29sMCL2i5VQMkTkLJz49hPOEZolDKUxsV1QEPhi62DRmiHZlKABh3+D
 wzTkTRLfDhlrNedY529/1i3IxIlnzWXfInohe+WadapTFXuISIv6dyAyh9eNKnfd
 ZVf+1NwaCGbZbbPkSBqK
 =dJJd
 -----END PGP SIGNATURE-----

Merge tag 'mfd-for-linus-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd

Pull MFD updates from Lee Jones:
 "Changes to the core:
   - Honour PLATFORM_DEVID_NONE and PLATFORM_DEVID_AUTO dev IDs

  Changes to existing drivers:
   - IRQ additions/fixes; axp20x, da9063-core
   - Code simplification; i2c-dln2
   - Regmap additions/fixes; max77693
   - Error checking/handling improvements; dln2, db8500-prcmu
   - Bug fixes; dln2, wm8350-core
   - DT support/documentation; max77693, max77686, tps65217, twl4030-power,
                               gpio-tc3589x
   - Decouple syscon interface from platform devices
   - Use MFD hotplug registration; rtsx_usb, viperboard, hid-sensor-hub
   - Regulator fixups; sec-core
   - Power Management additions/fixes; rts5227, tc6393xb
   - Remove relic/redundant code; ab8500-sysctrl, lpc_sch, max77693-private
   - Clean-up/coding style changes; tps65090
   - Clk additions/fixes; tc6393xb, tc6387xb, t7l66xb
   - Add USB-SPI support; dln2
   - Trivial changes; max14577, arizona-spi, lpc_sch, wm8997-tables, wm5102-tables
                      wm5110-tables, axp20x, atmel-hlcdc, rtsx_pci

  New drivers/supported devices:
   - axp288 PMIC support added to axp20x
   - s2mps13 support added to sec-core
   - New support for Diolan DLN-2
   - New support for atmel-hlcdc"

* tag 'mfd-for-linus-3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd: (55 commits)
  mfd: rtsx: Add func to split u32 into register
  mfd: atmel-hlcdc: Add Kconfig option description and name
  mfd: da9063: Get irq base dynamically before registering device
  mfd: max14577: Fix obvious typo in company name in copyright
  mfd: axp20x: Constify axp20x_acpi_match and rid unused warning
  mfd: t7l66xb: prepare/unprepare clocks
  mfd: tc6387xb: prepare/unprepare clocks
  mfd: dln2: add support for USB-SPI module
  mfd: wm5110: Add missing registers for AIF2 channels 3-6
  mfd: tc3589x: get rid of static base
  mfd: arizona: Document HP_CTRL_1L and HP_CTRL_1R registers
  mfd: wm8997: Mark INTERRUPT_STATUS_2_MASK as readable
  mfd: tc6393xb: Prepare/unprepare clocks
  mfd: tps65090: Fix bonkers indenting strategy
  mfd: tc6393xb: Fail ohci suspend if full state restore is required
  mfd: lpc_sch: Don't call mfd_remove_devices()
  mfd: wm8350-core: Fix probable mask then right shift defect
  mfd: ab8500-sysctrl: Drop ab8500_restart
  mfd: db8500-prcmu: Provide sane error path values
  mfd: db8500-prcmu: Check return of devm_ioremap for error
  ...
2014-12-08 20:02:54 -08:00
Arnd Bergmann ab64920c37 mvebu SoC suspend changes for v3.19
- Armada 370/XP suspend/resume support
 
  - mvebu SoC driver suspend/resume support
     - irqchip
     - clocksource
     - mbus
     - clk
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJUe0lIAAoJEP45WPkGe8Zn/IgP/jOO8c7t7dohRbAe3axzIcaC
 DLL7d7j0AScZGXLx1/xJrFFY/P3gn3dlLR7HnT0t4K7vcW0kP4orMGo6FcGicSOZ
 VzQf88cOkunKf9NTM1Y0LOXVWTHGuACiXAnxook5A6k+l0xQ1t+uewgEKrg/33VK
 6WQ6woe2eYFwghkFwL3ybjttOPM5nxPef6v3TZ3LfwSUBsnSm70F1XiO8xZJH+LM
 fL83P409LGWgohwSaXYRdPJcNM0U7QMNo6i/If9NNBhIkdKb6llhQ/DvI+aXUvqB
 aD9/4t+Q75yki0mXIin6irltjspWsR8OFbaKZOM5IBFp/XrsKvNU+wy++7z9se9z
 qfG1QYmKk3ddI0isoksuIJpfbrlbQqFKCGlNkn8HVi4xCYCijNgb5bUrHQ27Aa4U
 GGisAOhqs9Ktpz96WeNKjvNQBSJZ3ESd6tlLrwCei8DwEdT0Z73jr1aEnulurpPG
 A3kiUhVpRIU+w0cth5Kix2bZj7JGsykzu1x5xORLE+MN8RSgmoveGyY5CBp2MHrl
 NxR/u98SD9I/rWT3DwQIKxM5ZqF4AAnyj4SaSWR/f40kWMU+A+eMEfo8VUeO88fl
 ygeeHTghSf58gbdgganRfDyY8OaQHeYNNKbWK6c7vxyMX98vwHOtOb5JS3nn0p7q
 Fugy/6qf+ZqYHT4nczJO
 =uX+e
 -----END PGP SIGNATURE-----

Merge tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu into next/soc

Pull "mvebu SoC suspend changes for v3.19" from Jason Cooper:

 - Armada 370/XP suspend/resume support

 - mvebu SoC driver suspend/resume support
    - irqchip
    - clocksource
    - mbus
    - clk

* tag 'mvebu-soc-suspend-3.19' of git://git.infradead.org/linux-mvebu:
  ARM: mvebu: add SDRAM controller description for Armada XP
  ARM: mvebu: adjust mbus controller description on Armada 370/XP
  ARM: mvebu: add suspend/resume DT information for Armada XP GP
  ARM: mvebu: synchronize secondary CPU clocks on resume
  ARM: mvebu: make sure MMU is disabled in armada_370_xp_cpu_resume
  ARM: mvebu: Armada XP GP specific suspend/resume code
  ARM: mvebu: reserve the first 10 KB of each memory bank for suspend/resume
  ARM: mvebu: implement suspend/resume support for Armada XP
  clk: mvebu: add suspend/resume for gatable clocks
  bus: mvebu-mbus: provide a mechanism to save SDRAM window configuration
  bus: mvebu-mbus: suspend/resume support
  clocksource: time-armada-370-xp: add suspend/resume support
  irqchip: armada-370-xp: Add suspend/resume support
  Documentation: dt-bindings: minimal documentation for MVEBU SDRAM controller

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-12-04 16:46:43 +01:00
Tomeu Vizoso 646cafc6aa clk: Change clk_ops->determine_rate to return a clk_hw as the best parent
This is in preparation for clock providers to not have to deal with struct clk.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 16:21:37 -08:00
Tomeu Vizoso 61c7cddfad clk: change clk_debugfs_add_file to take a struct clk_hw
Instead of struct clk, as this should be only used by providers.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 15:15:35 -08:00
Tomeu Vizoso 920f1c7472 clk: Don't expose __clk_get_accuracy
As it's only used internally, in drivers/clk/clk.c.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 15:15:34 -08:00
Tomeu Vizoso 10cdfe54da clk: Don't try to use a struct clk* after it could have been freed
As __clk_release could call kfree on clk and then we wouldn't have a safe way
of getting the module that owns the clock.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Fixes: fcb0ee6a3d ("clk: Implement clk_unregister")
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 15:15:34 -08:00
Tomeu Vizoso 4afbe1760d clk: Remove unused function __clk_get_prepare_count
Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-12-03 15:15:34 -08:00
Krzysztof Kozlowski c31844ffdb clk: samsung: Fix double add of syscore ops after driver rebind
During driver unbind the syscore ops were not unregistered which lead to
double add on syscore list:

$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/unbind
$ echo "3810000.audss-clock-controller" > /sys/bus/platform/drivers/exynos-audss-clk/bind
[ 1463.044061] ------------[ cut here ]------------
[ 1463.047255] WARNING: CPU: 0 PID: 1 at lib/list_debug.c:36 __list_add+0x8c/0xc0()
[ 1463.054613] list_add double add: new=c06e52c0, prev=c06e52c0, next=c06d5f84.
[ 1463.061625] Modules linked in:
[ 1463.064623] CPU: 0 PID: 1 Comm: bash Tainted: G        W      3.18.0-rc5-next-20141121-00005-ga8fab06eab42-dirty #1022
[ 1463.075338] [<c0014e2c>] (unwind_backtrace) from [<c0011d80>] (show_stack+0x10/0x14)
[ 1463.083046] [<c0011d80>] (show_stack) from [<c048bb70>] (dump_stack+0x70/0xbc)
[ 1463.090236] [<c048bb70>] (dump_stack) from [<c00233d4>] (warn_slowpath_common+0x74/0xb0)
[ 1463.098295] [<c00233d4>] (warn_slowpath_common) from [<c00234a4>] (warn_slowpath_fmt+0x30/0x40)
[ 1463.106962] [<c00234a4>] (warn_slowpath_fmt) from [<c020fe80>] (__list_add+0x8c/0xc0)
[ 1463.114760] [<c020fe80>] (__list_add) from [<c0282094>] (register_syscore_ops+0x30/0x3c)
[ 1463.122819] [<c0282094>] (register_syscore_ops) from [<c0392f20>] (exynos_audss_clk_probe+0x36c/0x460)
[ 1463.132091] [<c0392f20>] (exynos_audss_clk_probe) from [<c0283084>] (platform_drv_probe+0x48/0xa4)
[ 1463.141013] [<c0283084>] (platform_drv_probe) from [<c0281a14>] (driver_probe_device+0x13c/0x37c)
[ 1463.149852] [<c0281a14>] (driver_probe_device) from [<c0280560>] (bind_store+0x90/0xe0)
[ 1463.157822] [<c0280560>] (bind_store) from [<c027fd10>] (drv_attr_store+0x20/0x2c)
[ 1463.165363] [<c027fd10>] (drv_attr_store) from [<c0143898>] (sysfs_kf_write+0x4c/0x50)
[ 1463.173252] [<c0143898>] (sysfs_kf_write) from [<c0142c80>] (kernfs_fop_write+0xbc/0x198)
[ 1463.181395] [<c0142c80>] (kernfs_fop_write) from [<c00e2be0>] (vfs_write+0xa0/0x1a8)
[ 1463.189104] [<c00e2be0>] (vfs_write) from [<c00e2f00>] (SyS_write+0x40/0x8c)
[ 1463.196122] [<c00e2f00>] (SyS_write) from [<c000f2a0>] (ret_fast_syscall+0x0/0x48)
[ 1463.203655] ---[ end trace 08f6710c9bc8d8f3 ]---
[ 1463.208244] exynos-audss-clk 3810000.audss-clock-controller: setup completed

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Fixes: 1241ef94cc ("clk: samsung: register audio subsystem clocks using common clock framework")
Cc: <stable@vger.kernel.org>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:59 +01:00
Andrzej Hajda df019a5c0f clk: samsung: exynos4: set parent of sclk_hdmiphy to hdmi
sclk_hdmiphy clock is generated by HDMI-PHY and depends on hdmi gate clock.
The patch models this dependency using parent/child hirerarchy.

The patch fixes issue with system hangs during mixer device access, mixer uses
sclk_hdmiphy descendant clock.

Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:58 +01:00
Krzysztof Kozlowski b5f56e14c1 clk: samsung: exynos4415: Fix build with PM_SLEEP disabled
Fix following build errors when PM_SLEEP is disabled (e.g. by disabling
SUSPEND and HIBERNATION):

drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_init’:
drivers/clk/samsung/clk-exynos4415.c:982:2: error: ‘exynos4415_ctx’ undeclared (first use in this function)
drivers/clk/samsung/clk-exynos4415.c:982:2: note: each undeclared identifier is reported only once for each function it appears in
drivers/clk/samsung/clk-exynos4415.c: In function ‘exynos4415_cmu_dmc_init’:
drivers/clk/samsung/clk-exynos4415.c:1123:2: error: ‘exynos4415_dmc_ctx’ undeclared (first use in this function)
make[3]: *** [drivers/clk/samsung/clk-exynos4415.o] Error 1

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:22:58 +01:00
Pankaj Dubey 8b2f63606a clk: samsung: remove unnecessary inclusion of header files from clk.h
Let's remove unnecessary include of header files from clk.h and add
required one in clk.c

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
[s.nawrocki@samsung.com: dropped removal of '#include <linux/syscore_ops.h>']
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 16:21:37 +01:00
Pankaj Dubey 7882857e98 clk: samsung: remove unnecessary CONFIG_OF from clk.c
Remove unnecessary CONFIG_OF from samsung/clk.c.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 12:28:24 +01:00
Pankaj Dubey 2e41b9fc11 clk: samsung: Spelling s/bwtween/between/
Fix a typo in comment section of "struct samsung_clk_provider".

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-12-02 12:28:20 +01:00
Thomas Petazzoni f571053152 clk: mvebu: add suspend/resume for gatable clocks
This commit adds suspend/resume support for the gatable clock driver
used on Marvell EBU platforms. When getting out of suspend, the
Marvell EBU platforms go through the bootloader, which re-enables all
gatable clocks. However, upon resume, the clock framework will not
disable again all gatable clocks that are not used.

Therefore, if the clock driver does not save/restore the state of the
gatable clocks, all gatable clocks that are not claimed by any device
driver will remain enabled after a resume. This is why this driver
saves and restores the state of those clocks.

Since clocks aren't real devices, we don't have the normal ->suspend()
and ->resume() of the device model, and have to use the ->suspend()
and ->resume() hooks of the syscore_ops mechanism. This mechanism has
the unfortunate idea of not providing a way of passing private data,
which requires us to change the driver to make the assumption that
there is only once instance of the gatable clock control structure.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: linux-kernel@vger.kernel.org
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1416585613-2113-9-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-11-30 16:40:12 +00:00
Michael Turquette ffa3a37a61 Immutable branch between MFD, Regulator and Clk, due for v3.19
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUdKaZAAoJEFGvii+H/HdhPj8P/1Jl60LnYPozG0eu6+rNaLDj
 AL8bNLWh0pANQzpYstE4aHDmrEWTArJ37eIet6BrPN/nv/ej2DR7hgK7Eh8h4P1t
 2LtBpxCT3f/Md92iBTLa/bMFm4VuuT/GiOurb1vR9BtTyH1bD8ftmXwhmzHskBuT
 wK0lfdvLEMRI2YIkgnLcuto07kMAIbLAQ4TANWvnHL2XLGd0/aPn68q3jNgwPjgf
 ufi5/eV8y+M/oopYPjU4Mt4W5fOTCZ6yINsp3tkOhPk9G28wJSmAiDkm9bn7KVrz
 Jwy60tpO9Z2+kff62uMjcWvMEvnMcrfQJ3cGm+Si64DuM+s2hmWpA/rXeO+Ep7VX
 jk3aiYXkFmUfgFXz7qMhFEERXu4nwhSGgdbEZWRmG8rcSaS3KnBNDaSvZOOH2mCq
 8iQmMzSMDK6CnW2wIr+2AsrrizPEPrvMOs7GLiUiyXlOjkUSR1XjJ6HlIfXKiMYg
 bWliacyGm3v+K3g41u9ULHNmLi779SlsUrH+Z6NARN5kRKXvsPntDA+8em11euvt
 7h1/wyPpjvJi8Cj5VJzinh4l/9t9O2GNeDuKExuOnaRHoOhzGkFwwMBgUkEdb5lX
 1il7JIXb/MfrwDbd4EZ/G0Ju2icFOfuwCAjad0upBfGkU11zJEa/KozN1ymjq/bD
 whTJLra7D6P0E8DBdS/0
 =WTv4
 -----END PGP SIGNATURE-----

Merge tag 'ib-mfd-regulator-clk-v3.19' of git://git.kernel.org/pub/scm/linux/kernel/git/lee/mfd into clk-next

Immutable branch between MFD, Regulator and Clk, due for v3.19
2014-11-28 21:11:10 -08:00
Michael Turquette b572b5f821 - clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
 - some more exported clocks
 - fixes for some clocks (typos etc) all of them not yet used
   in actual drivers
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUd7jIAAoJEPOmecmc0R2BrOkIAJpMe0tqHxtcN1fBSS2rS3/b
 bgcu37WfGXt1FkBkGPyoVfy0m6tQ9hHx07o62IowVvaWzmvoQppLmC20+y6gKVMj
 nVGlhbfhZ3bDJBbsbWAyzQvH+fJx+pOTIGQJCCNX/aixSYnfvda/FP0u7EVrY4W/
 mF/b5mPmHhah9EeyuAwy4eAT5xCCER5DqR9eryObDwj3N9cUluM9BiK1JWXXWdYt
 i/p3NS+MEjFG2KrLB+Rzu39yFRsjF8IOBKuYNh752NVcsNy2CuxqbDSpn8NM2niW
 bxW07X5J8JSpecpuzJmkuOomauE+4pKXMM3W+XL+XO8iF3h9inXXp0nzX31cQRI=
 =st2A
 -----END PGP SIGNATURE-----

Merge tag 'v3.19-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

- clock phase setting capability for the rk3288 mmc clocks
- pll init to allow syncing to actual rate table values
- some more exported clocks
- fixes for some clocks (typos etc) all of them not yet used
  in actual drivers
2014-11-28 21:00:16 -08:00
Pawel Moll 81cc3f868d ARM: vexpress: Remove non-DT code
Now, with the CLCD DT support available, there is no
more reason to keep the non-DT support for V2P-CA9.

Removed, together with "some" supporting code. It was
necessary to make PLAT_VERSATILE_SCHED_CLOCK optional
and selected by the machines still interested in it.

Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28 16:08:16 +01:00
Arnd Bergmann 09ffd948a0 Samsung PM 3rd updates for v3.19
- exynos3250
   : add PMU support
 
 - PMU refactoring
   : move restart code into PMU driver
   : move restart code for exynos440 into clk driver
 
 - use u8 for val[] in struct exynos_pmu_conf
 
 Note that this branch is based on tags/samsung-exynos-v3.19
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJUdsuOAAoJEA0Cl+kVi2xq4fkP/R4LIcYizfZxpe810YJWcIxU
 +1Ex5uesn0hgO8SfOaYixeuMyfhTWt4PQzfrFofL/WeQwgEMHeuBCqyWMbzBoF2v
 oi4U8zE90z8YTsKR31qXfwcZydMpXnqpj9KeIXsh/1S1wvJduKExQ6vgRdzD1cSK
 t/NXiU3AkvDrAf/NGgbM9bY6+vKpqMGY2OpLjYzouGA+3xObjbSol+aI9xMpagbh
 AacVwYOUHu+KKQx2A34toGVnrhNo6kPQ+eYR6JMCpHC3cNmysW8JeDCS/GI+dJLe
 Nu3NEOtPL2E4KsPm+4O44dRkxZVfhWht/+5KhSpyU8OCU7k876iP9HsMDbRRc251
 WCoKMCPReZtbR3KDE1xU/qZhiBSe2bMo0EgnZn/rTg4pusbaBgtpmA8dy17hYfLQ
 YCYMV867Zcq8uZseiuaR6UaSqKPF4jciSq6w56YC3Ozi1DRmo1vKA0VHqYKiWZPm
 8iD14+enPj1QNHwlYln2HyyttvreEFeU/wMUKe/qdQhPftrLlNDeliXHy12HZ6K+
 eRgC8JmLITQiJ/mVy8yshsLa62S2jdEbWYmlOniTpaELFpgmMGVCBKySXdSh7sVf
 feaybFIUDjt0IxkKYTceqIpOs+dJ7eP/ccmcokMET8jpw78a1jMSddqt6PJz1ooZ
 /egKklt67zQuYlpGhWjv
 =bi8c
 -----END PGP SIGNATURE-----

Merge tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc

Pull "Samsung PM 3rd updates for v3.19" from Kukjin Kim:

- exynos3250
  : add PMU support

- PMU refactoring
  : move restart code into PMU driver
  : move restart code for exynos440 into clk driver

- use u8 for val[] in struct exynos_pmu_conf

Note that this branch is based on tags/samsung-exynos-v3.19

* tag 'samsung-pm-3' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
  ARM: EXYNOS: use u8 for val[] in struct exynos_pmu_conf
  ARM: EXYNOS: move restart code into pmu driver
  clk: exynos5440: move restart code into clock driver
  ARM: EXYNOS: add exynos3250 PMU support

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2014-11-28 13:21:28 +01:00
Alexandru M Stan 89bf26cbc1 clk: rockchip: Add support for the mmc clock phases using the framework
This patch adds the 2 physical clocks for the mmc (drive and sample). They're
mostly there for the phase properties, but they also show the true clock
(by dividing by RK3288_MMC_CLKGEN_DIV).

The drive and sample phases are generated by dividing an upstream parent clock
by 2, this allows us to adjust the phase by 90 deg.

There's also an option to have up to 255 delay elements (40-80 picoseconds long).
This driver uses those elements (under the assumption that they're 60 ps long)
to generate approximate 22.5 degrees options. 67.5 (22.5*3) might be as high as
90 deg if the delay elements are as big as 80 ps, so a finer division (smaller
than 22.5) was not picked because the phase might not be monotonic anymore.

Suggested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Alexandru M Stan <amstan@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28 00:44:24 +01:00
Sonny Rao 6d288b169b clk: rockchip: rk3288 export i2s0_clkout for use in DT
This exposes the clock that comes out of the i2s block which generally
goes to the audio codec.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
[removed CLK_SET_RATE_PARENT from original patch]
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-28 00:37:47 +01:00
Jeff Chen a72da7c166 clk: rockchip: use clock ID for DMC (memory controller) on rk3288
The DMC clocks need to be turned off at runtime.  Use the newly
assigned clock IDs to export them.

Signed-off-by: Jeff Chen <cym@rock-chips.com>
[dianders: split into two patches; adjusted commit msg]
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-26 18:32:28 +01:00
Thierry Reding 4f4f85fa0b clk: tegra: Implement memory-controller clock
The memory controller clock runs either at half or the same frequency as
the EMC clock.

Reviewed-By: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2014-11-26 09:43:23 +01:00
kbuild test robot 250d07d1e7 clk: clk-s2mps11: fix semicolon.cocci warnings
drivers/clk/clk-s2mps11.c:181:2-3: Unneeded semicolon

 Removes unneeded semicolon.

Generated by: scripts/coccinelle/misc/semicolon.cocci

CC: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Fengguang Wu <fengguang.wu@intel.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-25 17:27:41 -08:00
Chanwoo Choi f928b53d74 clk: s2mps11: Add the support for S2MPS13 PMIC clock
This patch adds the support for S2MPS13 PMIC clock which is same with existing
S2MPS14 RTC IP. But, S2MPS13 uses all of clocks (32khz_{ap|bt|cp}).

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Acked-by: Michael Turquette <mturquette@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
2014-11-25 15:55:11 +00:00
Heiko Stuebner dd79c0bea7 clk: rockchip: add ROCKCHIP_PLL_SYNC_RATE flag to some plls
Add the new flag to gpll and cpll on rk3188 and similar and to
gpll, cpll and npll on rk3288.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:22 +01:00
Heiko Stuebner 0bb66d3b6e clk: rockchip: add optional sync to pll rate parameters
In some cases firmware brings up plls with different parameters than the ones
noted in the rate table for the specific frequency. These firmware-selected
parameters are worse than the tested ones in the pll rate tables but cannot
be changed by a simple clk_set_rate call when the rate stays the same.

Therefore add a ROCKCHIP_PLL_SYNC_RATE flag and implement an init callback
that checks the runtime-parameters against the matching rate table entry
and adjusts them to the table-ones if necessary.

If no rate table is set or the current rate does not match any rate-table
entry no changes are made.

Being able to limit this adjustment to specific plls is necessary to not
touch the ones supplying core components like the apll and dpll supplying
the armcores and dram.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:18 +01:00
Heiko Stuebner d0e7a0ca4b clk: rockchip: setup pll_mux data earlier
In some cases we might need to access the data of the pll mux before the actual
mux gets registered - like in the following patch adding an init-callback.

Therefore populate pll_mux before registering the core pll-clock.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:13 +01:00
Heiko Stuebner 4f8a7c549f clk: rockchip: add ability to specify pll-specific flags
This adds a flag parameter to plls that allows us to create
special flags to tweak the behaviour of the plls if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
2014-11-25 09:57:07 +01:00
Michael Turquette b082915c9d Allwinner Clocks additions for 3.19
A few patches that should go through the clock tree, mostly fixes, cleanups,
 and new clocks additions to start to support the A80.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUcgvhAAoJEBx+YmzsjxAgMBQQALMexo9E+r09f/1+rtH9iFXC
 XBWbGZJufGHLPP0RYNhOK1m6TShpaZMMu6OTWHkQZ8sUUb0e35AhgvZxdMtdj/9T
 K3yQ2PX4YlcJJUOK1HiLNXtVa//evth/GjXEB7MC1D8FW6hbXU6jkvhbLiCDAxyl
 s3PPvbi6EXRExiHN6r5U3PD3BdLjSr/eRZLNvbHM5ImFMA03rmJsRcIK+STP01zg
 OYgEkwSq+n0lJ+9d7mFXb+Bb7fPUvwDGtgqdoajiMOJc99p/91bDHTu84Fq0g2X2
 m/2ofaiuioVj6QiIH+tm1WiOU0qON70N23YSaeG4c9yGZI1CnRIsUvjRWA8/mWtb
 94O+k+LpU1fk1xWvNL+uthIHiiBJqlg5255ry02jKIZWMeuNVlBLawynvnaQ2Lki
 RkOQkaMYtYTFUsKWCf0LSEwCC8UCuXa3mkRfPioC6Pk/fE5Doqb56qnDHdxhn0VX
 t6GH03Pzb1OLLMdxfK7VcamLwA3MeEp7byxpCZ24GSUtthhFdXvyduaeXSV7+Lo7
 gg7NdFwlNy6RXAMkP1CpnYF0sZsekn7hToUl+GQzYSAP35Mt2C62sHzMD9Pxgezv
 n7WXThKIYJz/r7S00MnTFlp2Ge20NtUp/BEFbxn6w3FvG7R8Gk633z1LiZ1mGEJ9
 4iMjTj20SnN+GOz0p7qA
 =Krm9
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clocks-for-3.19' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner Clocks additions for 3.19

A few patches that should go through the clock tree, mostly fixes, cleanups,
and new clocks additions to start to support the A80.
2014-11-24 18:08:53 -08:00
Michael Turquette da57b46010 Merge branch 'clk-fixes' into clk-next 2014-11-24 17:45:33 -08:00
Kelvin Cheung 3526f74fa9 clk: ls1x: Update relationship among all clocks
- Add clock lookups for APB devices.
 - Update clock relationship to make it more exact and clear.
                                 _____
         _______________________|     |
 OSC ___/                       | MUX |___ XXX CLK
        \___ PLL ___ XXX DIV ___|     |
                                |_____|

Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Cc: linux-kernel@vger.kernel.org
Cc: mturquette@linaro.org
Cc: linux-mips@linux-mips.org
Patchwork: https://patchwork.linux-mips.org/patch/8026/
Signed-off-by: Ralf Baechle <ralf@linux-mips.org>
2014-11-24 07:45:09 +01:00
Hans de Goede c1ec516030 clk: sunxi: gmac-tx-clk mux is not a CLK_MUX_INDEX_BIT mux
A CLK_MUX_INDEX_BIT mux has one bit per parent, but the sun7i-a20-gmac-clk
has 2 bits selecting between 3 possible parents using values of 0, 1, 2,
which makes it a regular mux which should not have CLK_MUX_INDEX_BIT set in
its flag.

However we do not support parent 1 (an external clock), so use a table to
select parent 0 or 2, which are the 2 parents we support.

Note this has not been causing any issues sofar, because we start with a
parent setting of parent 0, and only ever re-parent to parent 2 (for which
we use an index of 1 as we skip parent 1) and with CLK_MUX_INDEX_BIT set
we write a value of 2 for index 1.

Tested on both a cubietruck (which uses rgmii mode) as well as a cs908
(an a31s board which uses mii mode).

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:57 +01:00
Chen-Yu Tsai 95e94c1fad clk: sunxi: Implement A31 PLL6 as a divs clock for 2x output
Some clock modules on the A31 use PLL6x2 as one of their inputs.
This patch changes the PLL6 implementation for A31 to a divs clock,
i.e. clock with multiple outputs that have different dividers.
The first output will be the normal PLL6 output, and the second
will be PLL6x2.

This patch fixes the PLL6 N factor in the clock driver, and removes
any /2 dividers in the PLL6 factors clock part. The N factor counts
from 1 to 32, mapping to values 0 to 31, as shown in the A31 manual.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Chen-Yu Tsai 13d52f6106 clk: sunxi: Specify number of child clocks for divs clocks
Currently sunxi_divs_clk_setup assumes the number of child clocks
to be the same as the number of clock-output-names, and a maximum
of SUNXI_DIVS_MAX_QTY child clocks.

On sun6i, PLL6 only has 1 child clock, but the parent would be used
as well, thereby also having it's own clock-output-names entry. This
results in an extra bogus clock being registered.

This patch adds an entry for the number of child clocks alongside
the data structures for them.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Chen-Yu Tsai eaa2e9804e clk: sunxi: Removed unused/incorrect sun6i-a31-apb2-clk driver
This driver does not match the hardware, which is actually compatible
to sun4i-a10-apb1-clk. Since we've switch to the correct one, drop
this driver.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-23 17:02:56 +01:00
Julien CHAUVEAU 12c0a0e81e clk: rockchip: fix rk3188 USB HSIC PHY clock divider
The USB HSIC PHY clock divider is set in the register RK2928_CLKSEL_CON(11).

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-23 01:55:14 +01:00
Julien CHAUVEAU b7bdb7f45e clk: rockchip: fix clock gate for rk3188 spdif_pre
In rk3188 clock branches, spdif_pre gate was set to RK2928_CLKGATE_CON(13) bit 13.
This appears to be a copy-paste error because such a register does not exist.
We correct it to RK2928_CLKGATE_CON(0) and find out that the rk3188 spdif clock
is the same as the rk3066 spdif clock, so we move it to the common clock branches.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-23 00:39:57 +01:00
Pankaj Dubey 5e6473f422 clk: exynos5440: move restart code into clock driver
Let's register restart handler for Exynos5440 from it's clock driver
for restart functionality. So that we can cleanup restart hooks from
machine specific file.

CC: Sylwester Nawrocki <s.nawrocki@samsung.com>
CC: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Acked-by: Guenter Roeck <linux@roeck-us.net>
Acked-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
2014-11-22 23:07:21 +09:00
Jiri Kosina a02001086b Merge Linus' tree to be be to apply submitted patches to newer code than
current trivial.git base
2014-11-20 14:42:02 +01:00
Bintian Wang 7f615dd43c clk: hi3620: Move const initdata into correct code section
Use __initconst instead of __initdata for constant init data.

Signed-off-by: Bintian Wang <bintian.wang@huawei.com>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-19 16:56:31 -08:00
Hans de Goede 6793b3cd5d clk_mux: Fix set_parent doing the wrong thing when INDEX_BIT && index >= 3
If CLK_MUX_INDEX_BIT is set, then each bit turns on / off a single parent,
so theoretically multiple parents could be enabled at the same time, but in
practice only one bit should ever be 1. So to select parent 0, set
the register (*) to 0x01, to select parent 1 set it 0x02, parent 2, 0x04,
parent 3, 0x08, etc.

But the current code does:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = (1 << ffs(index));

Which means that:

For an input index of 0, ffs returns 0, so we set the register
to 0x01, ok.

For an input index of 1, ffs returns 1, so we set the register
to 0x02, ok.

For an input index of 2, ffs returns 2, so we set the register
to 0x04, ok.

For an input index of 3, ffs returns 1, so we set the register
to 0x02, not good!

The code should simply be:

                if (mux->flags & CLK_MUX_INDEX_BIT)
                        index = 1 << index;

Which always does the right thing, this commit fixes this.

Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-19 14:03:13 -08:00
Michael Turquette 3c7f4fe810 Merge branch 'for-v3.19/exynos-clk' of git://linuxtv.org/snawrocki/samsung into clk-next-exynos 2014-11-19 11:41:21 -08:00
Michael Turquette d4f2016f59 Merge branch 'clk-next-shmobile' into clk-next 2014-11-19 11:41:19 -08:00
Zhen Lei 40ba3f0ff2 clk: delete a local variable's repeated assignment
It's the same to the next statement, "ret = clk->parent". I think compiler will
optimize it, it's just not looking well.

Signed-off-by: Zhen Lei <thunder.leizhen@huawei.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-19 11:41:18 -08:00
Michael Turquette 54b3d182b5 Merge tag 'v3.19-rockchip-clk1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next-rockchip
- fixes for clock ordering/rate issues
- do not keep all clocks enabled anymore
- allow special pll rates for special cases
2014-11-19 11:41:17 -08:00
Julien CHAUVEAU f0c71718c2 clk: rockchip: fix parent clock for rk3188 hclk_lcdc1
The parent clock for hclk_lcdc1 was set to aclk_cpu instead of hclk_cpu.

Signed-off-by: Julien CHAUVEAU <julien.chauveau@neo-technologies.fr>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-18 16:40:46 +01:00
Robert Jarzmik 6f8a444aa6 clk: pxa: keep clocks initialization separated per variant
Have each pxa variant (pxa25x, pxa27x, pxa3xx) have its own device-tree
clock initializing function, to be able to register its own specific
core clocks.

Apply that change specifically to pxa27x.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:27:45 -08:00
Robert Jarzmik 14dd5b01ae clk: pxa: declare init function and data __init
As the clock descriptions are constant and only usefull at init time,
mark them as such by :
 - spliting clock description (desc) and clock private data (dynamic)
 - mark __initdata clock descriptions

This makes all the register and descriptions of the clocks to go after
kernel init phase.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:27:44 -08:00
Robert Jarzmik dcf3d45830 clk: pxa: fix pxa27x CCCR bit usage
Trivial fix to check the A bit of CCCR for memory frequency
calculations, where the shift of the bit index was missing, triggering a
wrong calculation of memory frequency.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:25:29 -08:00
Robert Jarzmik fe7710fae4 clk: add pxa25x clock drivers
Move pxa25x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
 - convert to new clock framework legacy clocks
 - provide clocks as before for platform data based boards
 - provide clocks through devicetree with clk-pxa-dt

This is the preliminary step in the conversion. The remaining steps are
:
 - pxa3xx
 - once PXA is fully converted to device tree, if that happens,
   clk-pxa2* and clk-pxa3* should only hold the core clocks which cannot
   be described in devicetree.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Tested-by: Dmitry Eremin-Solenikov <dbaryshkov@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:20:55 -08:00
James Hogan e6d5e7d90b clk-divider: Fix READ_ONLY when divider > 1
Commit 79c6ab5095 (clk: divider: add CLK_DIVIDER_READ_ONLY flag) in
v3.16 introduced the CLK_DIVIDER_READ_ONLY flag which caused the
recalc_rate() and round_rate() clock callbacks to be omitted.

However using this flag has the unfortunate side effect of causing the
clock recalculation code when a clock rate change is attempted to always
treat it as a pass-through clock, i.e. with a fixed divide of 1, which
may not be the case. Child clock rates are then recalculated using the
wrong parent rate.

Therefore instead of dropping the recalc_rate() and round_rate()
callbacks, alter clk_divider_bestdiv() to always report the current
divider as the best divider so that it is never altered.

For me the read only clock was the system clock, which divided the PLL
rate by 2, from which both the UART and the SPI clocks were divided.
Initial setting of the UART rate set it correctly, but when the SPI
clock was set, the other child clocks were miscalculated. The UART clock
was recalculated using the PLL rate as the parent rate, resulting in a
UART new_rate of double what it should be, and a UART which spewed forth
garbage when the rate changes were propagated.

Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Thomas Abraham <thomas.ab@samsung.com>
Cc: Tomasz Figa <t.figa@samsung.com>
Cc: Max Schwarz <max.schwarz@online.de>
Cc: <stable@vger.kernel.org> # v3.16+
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 11:13:52 -08:00
Georgi Djakov 9a6cb70f40 clk: qcom: Fix duplicate rbcpr clock name
There is a duplication in a clock name for apq8084 platform that causes
the following warning: "RBCPR_CLK_SRC" redefined

Resolve this by adding a MMSS_ prefix to this clock and making its name
coherent with msm8974 platform.

Fixes: 2b46cd23a5 ("clk: qcom: Add APQ8084 Multimedia Clock Controller (MMCC) support")
Signed-off-by: Georgi Djakov <gdjakov@mm-sol.com>
Reviewed-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 10:40:42 -08:00
Boris Brezillon 69daf75aaf clk: at91: usb: fix at91sam9x5 recalc, round and set rate
First check for rate == 0 in set_rate and round_rate to avoid div by zero.
Then, in order to get the closest rate, round all divisions to the closest
result instead of rounding them down.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 10:38:40 -08:00
Boris Brezillon ff553ea1a3 clk: at91: usb: fix at91rm9200 round and set rate
at91rm9200_clk_usb_set_rate might fail depending on the requested rate,
because the parent_rate / rate remainder is not necessarily zero.
Moreover, when rounding down the calculated rate we might alter the
divisor calculation and end up with an invalid divisor.

To solve those problems, accept a non zero remainder, and always round
division to the closest result.

Signed-off-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Reported-by: Andreas Henriksson <andreas.henriksson@endian.se>
Tested-by: Andreas Henriksson <andreas.henriksson@endian.se>
Acked-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-17 10:38:40 -08:00
Kever Yang 29e9446851 clk: rockchip: fix clock select order for rk3288 usbphy480m_src
According to rk3288 trm, the mux selector locate at bit[12:11]
of CRU_CLKSEL13_CON shows:
2'b00: select HOST0 USB pll clock (clk_otgphy1)
2'b01: select HOST1 USB pll clock (clk_otgphy2)
2'b10: select OTG USB pll clock   (clk_otgphy0)

The clock map is in Fig. 3-4 CRU Clock Architecture Diagram 3
- clk_otgphy0 -> USB PHY OTG
- clk_otgphy1 -> USB PHY host0
- clk_otgphy2 -> USB PHY host1

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-16 00:40:19 +01:00
Kever Yang 0132234160 clk: rockchip: fix rk3288 clk_usbphy480m_gate bit location in register
According to rk3288 trm, the clk_usbphy480m_gate is located at
bit 14 of CRU_CLKGATE5_CON register.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-16 00:02:24 +01:00
Tero Kristo 2e1a7b014f ARM: OMAP3+: DPLL: use determine_rate() and set_rate_and_parent()
Currently, DPLLs are hiding the gory details of switching parent
within set_rate, which confuses the common clock code and is wrong.
Fixed by applying the new determine_rate() and set_rate_and_parent()
functionality to any clock-ops previously using the broken approach.
This patch also removes the broken legacy code.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
2014-11-13 09:26:45 -07:00
Dmitry Torokhov 9aa75e6e09 clk: rockchip: ensure HCLK_VIO2_H2P and PCLK_VIO2_H2P stay enabled
Currently there is no driver owning these clocks and they have to stay
up for the system to function properly, so let's mark them as
CLK_IGNORE_UNUSED.

Without this patch we have trouble with suspend/resume and we have
trouble turning the eDP back on if it ever idles off.

Signed-off-by: Dmitry Torokhov <dtor@chromium.org>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-13 11:55:45 +01:00
Chao Xie 1ec770d92a clk: mmp: add mmp2 DT support for clock driver
It adds the DT support for mmp2 clock subsystem.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:22 -08:00
Chao Xie 2bc61da9f7 clk: mmp: add pxa910 DT support for clock driver
It adds the DT support for pxa910 clock subsystem.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:18 -08:00
Chao Xie ab08aefcd1 clk: mmp: add pxa168 DT support for clock driver
It adds the DT support for pxa168 clock subsystem.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:14 -08:00
Chao Xie ae32a5b321 clk: mmp: add reset support
Some clock control regsiter has bit to reset the cotroller.
So before enable the clock, we need deassert the reset pin.
Make use of reset controller framework to export reset interface
for device drivers, then device driver can control the reset action.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:10 -08:00
Chao Xie 4661fda10f clk: mmp: add basic support functions for DT support
In order to support DT for mmp SOC clocks, it defines
some basic APIs which are shared by all mmp SOC clock
units.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:05 -08:00
Chao Xie cdce35460f clk: mmp: add mmp private gate clock
Some SOCes have this kind of the gate clock
1. There are some bits to control the gate not only one bit.
2. It is not always that "1" is to enable while "0" is to disable
   when write register.

So we have to define the "mask", "enable_val", "disable_val" for
this kind of gate clock.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:34:00 -08:00
Chao Xie ee81f4ee2a clk: mmp: add clock type mix
The clock type mix is a kind of clock combines "div" and "mux".
This kind of clock can not allow to change div first then
mux or change mux first or div.
The reason is
1. Some clock has frequency change bit. Each time want to change
   the frequency, there are some operations based on this bit, and
   these operations are time-cost.
   Seperating div and mux change will make the process longer, and
   waste more time.
2. Seperting the div and mux may generate middle clock that the
   peripharals do not support. It may make the peripharals hang.

There are three kinds of this type of clock in all SOCes.
1. The clock has bit to trigger the frequency change.
2. Same as #1, but the operations for the bit is different
3. Do not have frequency change bit.

So this type of clock has implemented the callbacks
->determine_rate
->set_rate_and_parent
These callbacks can help to change the div and mux together.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:33:52 -08:00
Chao Xie 3a2b2f8495 clk: mmp: move definiton of mmp_clk_frac to clk.h
Move the definition of structure of mmp_clk_frac to
clk.h.
So device tree support can use this structure.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:33:48 -08:00
Chao Xie 0c4c11f355 clk: mmp: add init callback for clk-frac
For the clk-frac, we need to make sure that the initial
clock rate is one item of the table.
If it is not, we use the first item in the table by default.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:33:43 -08:00
Chao Xie 6125613391 clk: mmp: add spin lock for clk-frac
The register used by clk-frac may be shared with
other clocks.
So it needs to use spin lock to protect the register
access.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:33:37 -08:00
Chao Xie 2bd1e256e4 clk: mmp: add prefix "mmp" for structures defined for clk-frac
The structures defined for clk-frac will be used out side
of clk-frac.c.
To avoid conflicts, add prefix "mmp" for these structures'
name.

Signed-off-by: Chao Xie <chao.xie@marvell.com>
Acked-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Michael Turquette <mturquette@linaro.org>
2014-11-12 16:33:22 -08:00
Ulrich Hecht c6d67fb037 clk: shmobile: div6: support selectable-input clocks
Support for setting the parent at initialization time based on the current
hardware configuration in DIV6 clocks with selectable parents as found in
the r8a73a4, r8a7740, sh73a0, and other SoCs.

Signed-off-by: Ulrich Hecht <ulrich.hecht+renesas@gmail.com>
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
2014-11-12 14:24:08 +01:00
Emilio López 93746e70be clk: sunxi: unify APB1 clock
This commit unifies the APB1 mux with the APB1 clock, using the new
factors infrastructure.

Signed-off-by: Emilio López <emilio@elopez.com.ar>
[wens@csie.org: Add mux mask bits]
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-11-11 15:54:40 +01:00
Chris Zhong 33aa59c232 clk: rockchip: rk3288: add suspend and resume
save and restore some clks, which might be changed in suspend.

Signed-off-by: Tony Xie <xxx@rock-chips.com>
Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-10 20:56:42 +01:00
Heiko Stübner d1f931be7c clk: rockchip: fix rk3188 hsadc_frac definition
The arguments to COMPOSITE_FRAC for hsadc_frac were mangled, leaving out the
the general clock flags argument. This results in strange effects, as only
sometimes a zero-division is reported as the wrong register is read.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-07 23:41:14 +01:00
Kever Yang 78eaf6095c clk: rockchip: disable unused clocks
The rockchip clock driver use CLK_IGNORE_UNUSED flag to make sure
all the clocks are available like default power on state.
We have implement the clock manage in most of rockchip drivers,
it is time to remove it for power save.
Instead we add CLK_IGNORE_UNUSED for some clock nodes which should
be on during boot or no module driver in kernel will initialize it.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-11-04 22:52:51 +01:00
Abhilash Kesavan 932e98224d clk: samsung: exynos7: add gate clock for ADC block
Add clock support for the ADC interface in Exynos7.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:54 +01:00
Naveen Krishna Ch 2ab2dfe5d4 clk: samsung: exynos7: add gate clocks for WDT, TMU and PWM blocks
Add clock support for the watchdog timer, pwm timer and thermal
management unit IPs in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:53 +01:00
Naveen Krishna Ch f5e127cd5e clk: samsung: exynos7: add clocks for RTC block
Add clock support for the RTC block in Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:52 +01:00
Naveen Krishna Ch 6d0c8c723f clk: samsung: exynos7: add clocks for MMC block
Exynos7 supports 3 MMC channels, add the MMC gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:51 +01:00
Naveen Krishna Ch 57a2b485fa clk: samsung: exynos7: add clocks for I2C block
Exynos7 supports 12 I2C channels, add the I2C gate clocks to
support them.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:51 +01:00
Naveen Krishna Ch 532abc3a4a clk: samsung: add initial clock support for Exynos7 SoC
Add initial clock support for Exynos7 SoC which is required
to bring up platforms based on Exynos7.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:47 +01:00
Naveen Krishna Ch 0e5af27008 clk: samsung: Add fixed_factor_clocks field to struct exynos_cmu_info
Add the fields "fixed_factor_clks" and "nr_fixed_factor_clks" to
"struct exynos_cmu_info" to allow registering of fixed factor
clocks as well with exynos_cmu_register_one().

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:46 +01:00
Naveen Krishna Ch 16a9013b83 clk: samsung: Factor out the common code to clk.c
While adding clock support for Exynos5260, the infrastructure to
register multiple clock controllers was introduced. Factor out the
support for registering multiple clock controller from Exynos5260
clock code to common samsung clock code so that it can be used by
other Exynos SoC which have multiple clock controllers.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:45 +01:00
Naveen Krishna Ch 0c23e2af67 clk: samsung: add support for 145xx and 1460x PLLs
PLL145xx is similar to PLL35xx and PLL1460x is almost similar
to PLL46xx with minor differences in bit positions. Hence,
reuse the functions defined for pll_35xx and pll_46xx to
support 145xx and 1460x PLLs respectively.

Signed-off-by: Naveen Krishna Ch <naveenkrishna.ch@gmail.com>
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Reviewed-by: Thomas Abraham <thomas.ab@samsung.com>
Tested-by: Thomas Abraham <thomas.ab@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-31 10:45:35 +01:00
Chanwoo Choi 384cb2ce81 clk: samsung: exynos4415: Add clocks using common clock framework
This patch adds clock driver of Exynos4415 SoC based on Cortex-A9 using
common clock framework. The CMU (Clock Management Unit) of Exynos4415
controls PLLs(Phase Locked Loops) and generates system clocks for CPU,
busses and function clocks for individual IPs.

Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Seung-Woo Kim <sw0312.kim@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
2014-10-30 19:53:04 +01:00
Kever Yang 49ed9ee442 clk: rockchip: change PLL setting for better clock jitter
dclk_vop0/1 is the source of HDMI TMDS clock in rk3288, usually we
use 594MHz for clock source of dclk_vop0/1.

HDMI CTS 7-9 require TMDS Clock jitter is lower than 0.25*Tbit:
TMDS clock(MHz)		CTS require jitter (ps)
	297		84.2
	148.5		168
	74.25		336
	27		1247

PLL BW and VCO frequency effects the jitter of PLL output clock,
clock jitter is better if BW is lower or VCO frequency is higher.

If PLL use default setting of RK3066_PLL_RATE( 594000000, 2, 198, 4),
the TMDS Clock jitter is higher than 250ps, which means we can't
pass the test when TMDS clock is 297MHz or 148.5MHz.

If we use RK3066_PLL_RATE_BWADJ(594000000, 1, 198, 8, 1),
the TMDS Clock jitter is about 60ps and we can pass all test case.

So we need this patch to make hdmi si test pass.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-29 20:27:20 +01:00
Masanari Iida fe4e437229 treewide: Fix company name in module descriptions
This patch fix company name's spelling typo in module descriptions
and a Kconfig.

Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Acked-by: Chris Snook <chris.snook@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
2014-10-29 14:36:36 +01:00
Chen-Yu Tsai 0b0f08028e clk: sunxi: Add support for bus clock gates on Allwinner A80 SoC
This adds the gate clocks for AHB/APB busses on the A80 SoC.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:47:34 +02:00
Chen-Yu Tsai 3b2bd70f03 clk: sunxi: Add support for A80 basic bus clocks
The A80 SoC has 12 PLL clocks, 3 AHB clocks, 2 APB clocks, and a
new "GT" bus, which I assume is some kind of data bus connecting
the processor cores, memory and various busses. Also there is a
bus clock for a ARM CCI400 module.

As far as I can tell, the GT bus and CCI400 bus clock must be
protected.

This patch adds driver support for peripheral related PLLs and
bus clocks on the A80. The GT and CCI400 clocks are added as well
as these 2 along with the PLLs they are clocked from must not be
disabled.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:45:48 +02:00
Chen-Yu Tsai e94f8cb32d clk: sunxi: make factors clock mux mask configurable
Some of the factors-style clocks on the A80 have different widths
for the mux values in the registers.

Add a .muxmask field to clk_factors_config to make it configurable.
Passing a bitmask instead of a width parameter will allow reuse
in case we support table-based muxes in the future.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-10-21 21:40:56 +02:00
Wolfram Sang e030f980b3 clk: x86: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:23 +02:00
Wolfram Sang 661ff5be95 clk: ux500: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:23 +02:00
Wolfram Sang c8da4a0ec6 clk: samsung: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:22 +02:00
Wolfram Sang 1f46c71d6e clk: qcom: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:22 +02:00
Wolfram Sang a4ae8f3b0f clk: drop owner assignment from platform_drivers
A platform_driver does not need to set an owner, it will be populated by the
driver core.

Signed-off-by: Wolfram Sang <wsa@the-dreams.de>
2014-10-20 16:20:22 +02:00
Kever Yang 89c107a88d clk: rockchip: add npll to source of sclk_gpu
The possible sources for the rk3288-gpu-clock also include the npll,
making it the same list of sources as for uart0.

This patch make a common source for uart0 pll src and sclk_gpu,
so that gpu can get its clock from npll.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 14:00:18 +02:00
Jianqun 8f06f5d392 clk: rockchip: rk3288: removing the CLK_SET_RATE_PARENT from i2s_clkout
Removing the CLK_SET_RATE_PARENT from i2s_clkout, to limit i2s0_clkout
to select between its two parent without being able influence the core
i2s clock.

Tested on rk3288 board, suggested by Heiko.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 13:53:56 +02:00
Kever Yang cd9b4609a5 clk: rockchip: add 400MHz and 500MHz for rk3288 clock rate
This patch add 400MHz and 500MHz to clock rate table for rk3288.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:56 +02:00
Doug Anderson 61e309f322 clk: rockchip: Add CLK_SET_RATE_PARENT to aclk_cpu_pre
We'd like to be able to call clk_set_rate() on aclk_cpu (a gate) at
bootup.  In order for this to have any effect we need its parent
(aclk_cpu_pre) to percolate the rate change to _its_ parent
(aclk_cpu_src).  Add CLK_SET_RATE_PARENT to make this happen.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:55 +02:00
Sonny Rao de7d6c3eeb clk: rockchip: fix parent for spdif_8ch_frac on rk3288
The parent should be spdif_8ch_pre not spdif_8ch_src, which doesn't
exist and looks to be a typo.  The TRM also confirms this.

Signed-off-by: Sonny Rao <sonnyrao@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-20 12:00:55 +02:00
Linus Torvalds c0fa2373f8 The clk tree changes for 3.18 are dominated by clock drivers. Mostly
fixes and enhancements to existing drivers as well as new drivers. This
 tag contains a bit more arch code than I usually take due to some OMAP2+
 changes. Additionally it contains the restart notifier handlers which
 are merged as a dependency into several trees.
 
 The PXA changes are the only messy part. Due to having a stable tree I
 had to revert one patch and follow up with one more fix near the tip of
 this tag. Some dead code is introduced but it will soon become live code
 after 3.18-rc1 is released as the rest of the PXA family is converted
 over to the common clock framework.
 
 Another trend in this tag is that multiple vendors have started to push
 the complexity of changing their CPU frequency into the clock driver,
 whereas this used to be done in CPUfreq drivers.
 
 Changes to the clk core include a generic gpio-clock type and a
 clk_set_phase() function added to the top-level clk.h api. Due to some
 confusion on the fbdev mailing list the kernel boot parameters
 documentation was updated to further explain the clk_ignore_unused
 parameter, which is often required by users of the simplefb driver.
 Finally some fixes to the locking around the clock debugfs stuff was
 done to prevent deadlocks when interacting with other subsystems.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJUMu8gAAoJEDqPOy9afJhJ+GwP/3aU1PzhEPooZ3sZ5hkhmRYc
 RTzNZAODuOGbGnAiNQcr8XW3LJ6wKz5TSzzUC8IQkTcYM1Tsc7s5B6v+nMOkR2Jh
 sfrlnDEV/dsW9/3QADFuBowCaZdsaZnHn96RDhTmyDlPjh4HRR2k8ITT+TREbFrd
 cHDWy4QnI0u4NzhKtitvgW2770HyBpr31v5IdoRhVi5whoiBNL49BPwhwDWhwZVe
 w6qvc0jV8FK9Ra/Q7Vw6r3tiKkpO/upqVFDrsO831mp2qDcQvtOgNW9H2fjcobaX
 3/KCbs1TZs39e71RsEGwCvmCudXkTgO1wUJ86MuCLHeb2o78Vx8EYie02/RApTOJ
 0KGR+kFouggy2naeH8pXiTZk2HWMCbut6NQ1+AVbea5Em7hgHbYaQN71wVFKR4L7
 QL+TugrIg81fGWSvxoTo6fsbEiKOUdhXvHFWP5etKHL+Ll+7ku05ojHLOZgEEwTf
 zFWSSF4XSFQtuQD1gup0pSfoLs6qVR57l8FsrxfRPK9jGttg5z1wyNkY+585ptim
 eyTn4mkvkx9t9Sx47VRj9WPcPr2SW1w8lTMw1WqKfHG7AEUJHHkRQThQmiU82b47
 dTls4BBZ6sVZ8wj0V4zvnvbmtdYohOmBqNDEYx+a0dzPKstcAJyZgcjWBc13zds4
 rIKKxhiU7jGWH4qnJLrx
 =w2rN
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux

Pull clock tree updates from Mike Turquette:
 "The clk tree changes for 3.18 are dominated by clock drivers.  Mostly
  fixes and enhancements to existing drivers as well as new drivers.
  This tag contains a bit more arch code than I usually take due to some
  OMAP2+ changes.  Additionally it contains the restart notifier
  handlers which are merged as a dependency into several trees.

  The PXA changes are the only messy part.  Due to having a stable tree
  I had to revert one patch and follow up with one more fix near the tip
  of this tag.  Some dead code is introduced but it will soon become
  live code after 3.18-rc1 is released as the rest of the PXA family is
  converted over to the common clock framework.

  Another trend in this tag is that multiple vendors have started to
  push the complexity of changing their CPU frequency into the clock
  driver, whereas this used to be done in CPUfreq drivers.

  Changes to the clk core include a generic gpio-clock type and a
  clk_set_phase() function added to the top-level clk.h api.  Due to
  some confusion on the fbdev mailing list the kernel boot parameters
  documentation was updated to further explain the clk_ignore_unused
  parameter, which is often required by users of the simplefb driver.

  Finally some fixes to the locking around the clock debugfs stuff was
  done to prevent deadlocks when interacting with other subsystems."

* tag 'clk-for-linus-3.18' of git://git.linaro.org/people/mike.turquette/linux: (99 commits)
  clk: pxa clocks build system fix
  Revert "arm: pxa: Transition pxa27x to clk framework"
  clk: samsung: register restart handlers for s3c2412 and s3c2443
  clk: rockchip: add restart handler
  clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
  doc/kernel-parameters.txt: clarify clk_ignore_unused
  arm: pxa: Transition pxa27x to clk framework
  dts: add devicetree bindings for pxa27x clocks
  clk: add pxa27x clock drivers
  arm: pxa: add clock pll selection bits
  clk: dts: document pxa clock binding
  clk: add pxa clocks infrastructure
  clk: gpio-gate: Ensure gpiod_ APIs are prototyped
  clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe
  clk: ti: LLVMLinux: Move __init outside of type definition
  clk: ti: consider the fact that of_clk_get() might return an error
  clk: ti: dra7-atl-clock: fix a memory leak
  clk: ti: change clock init to use generic of_clk_init
  clk: hix5hd2: add I2C clocks
  clk: hix5hd2: add watchdog0 clocks
  ...
2014-10-15 07:05:03 +02:00
Linus Torvalds f33a3faa25 Merge branch 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild
Pull kbuild changes from Michal Marek:
 - fix for handling dependencies of *-objs targets by Masahiro Yamada
 - lots of cleanups in the kbuild machinery, also by Masahiro
 - fixes for the kconfig build to use an UTF-8 capable ncurses library
   if possible and to build on not-so-standard installs
 - some more minor fixes

* 'kbuild' of git://git.kernel.org/pub/scm/linux/kernel/git/mmarek/kbuild:
  kbuild: Do not reference *-n variables in the Makefile
  kbuild: simplify build, clean, modbuiltin shorthands
  kbuild: arm: Do not define "comma" twice
  kbuild: remove obj-n and lib-n handling
  kbuild: remove unnecessary variable initializaions
  kbuild: remove unnecessary "obj- := dummy.o" trick
  kbuild: handle C=... and M=... after entering into build directory
  kbuild: use $(Q) for sub-make target
  kbuild: fake the "Entering directory ..." message more simply
  kconfig/lxdialog: get ncurses CFLAGS with pkg-config
  kconfig: nconfig: fix multi-byte UTF handling
  kconfig: lxdialog: fix spelling
  kbuild: Make scripts executable
  kbuild: remove redundant clean-files from scripts/kconfig/Makefile
  kbuild: refactor script/kconfig/Makefile
  kbuild: handle the dependency of multi-objs hostprogs appropriately
  kbuild: handle multi-objs dependency appropriately
2014-10-14 09:22:26 +02:00
Chris Zhong 038b892aa9 clk: RK808: add clkout driver for RK808
This is the initial version of the RK808 PMIC.  This is a power management
IC for multimedia products.  It provides regulators that are able to
supply power to processor cores and other components.  The chip provides
other modules including RTC, Clockout.

Signed-off-by: Chris Zhong <zyw@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Ian Campbell <ijc+devicetree@hellion.org.uk>
Cc: Samuel Ortiz <sameo@linux.intel.com> says:
Cc: Alessandro Zummo <a.zummo@towertech.it>
Cc: Olof Johansson <olof@lixom.net>
Cc: Dmitry Torokhov <dtor@chromium.org>
Cc: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Cc: Kever Yang <kever.yang@rock-chips.com>
Cc: Li Zhong <zhong@linux.vnet.ibm.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2014-10-14 02:18:18 +02:00
Linus Torvalds 8b45bc892e ARM: SoC driver updates for 3.18
These are changes for drivers that are intimately tied to some SoC
 and for some reason could not get merged through the respective
 subsystem maintainer tree.
 
 Most of the new code is for the Keystone Navigator driver, which is
 new base support that is going to be needed for their hardware
 accelerated network driver and other units.
 
 Most of the commits are for moving old code around from at91 and omap
 for things that are done in device drivers nowadays.
 
 - at91: move reset, poweroff, memory and clocksource code into drivers
   directories
 - socfpga: add edac driver (through arm-soc, as requested by Boris)
 - omap: move omap-intc code to drivers/irqchip
 - sunxi: added an RTC driver for sun6i
 - omap: mailbox driver related changes
 - keystone: support for the "Navigator" component
 - versatile: new reboot, led and soc drivers
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAVDWWQGCrR//JCVInAQKX7Q//bDkoseKCZsGaXN7vfQ2YhT3SAc52mROV
 YQKdNmtMUrHqDgngATZTx5ogOh1hInnqueFjGGhfMYsHQO1Vj8+odj0r+4jhjuUY
 3YfY+qZ+91tq33JlUOhKn+mfVMdxJc8XarGgR6MSWYkqWVYCtLtBluum7hKm2UJ6
 /e4hd2zzImX5ATwj/LXWLx5eTf1qAVFGWzNUph1DrW+1V5lOu58X4gKwk1QOCVEh
 Pa0GV9oRTkjoswwz9drzjeFtie2yofQ2mygj6QKxg5NsosIF0+B8kJ61Sxwg56Ak
 tF+qn1hGtB2cDQkpxK4o2cZgCELhkh5Aqgol/vZUS1DMBSUEGCV9PPp2eOW83r3B
 0zsTgsShyVcTh7khdpQmHNRigvcc7e69LaAGC4o/RxaZpCU/LUNCQ+/iqVExSE8A
 VNEXr+JNxGxhj3m9KUHuEktdWx1oNvaYR8Rr4RPr6EWR8R6emJ04I7kXInvzhJZL
 HOGh75vSuAU83FrsP8fFRLadoHNVDXylAs38BPfGEMngVpjvwJLgQ3+729CwW+Q4
 +xQXAKSwKfr8xA8eg6wBSbFcwnEW4QwRqFqQ5XPw7zTZkCZbiLtvn3JpI5bH5A5Q
 /d2D+M2vFbB7VbWJBM4etO95eNS/pfhqJhcQh4t0DjXjoW6WqLiHCxhEx8Ogfvop
 /4ckyGvtEOI=
 =POJD
 -----END PGP SIGNATURE-----

Merge tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC driver updates from Arnd Bergmann:
 "These are changes for drivers that are intimately tied to some SoC and
  for some reason could not get merged through the respective subsystem
  maintainer tree.

  Most of the new code is for the Keystone Navigator driver, which is
  new base support that is going to be needed for their hardware
  accelerated network driver and other units.

  Most of the commits are for moving old code around from at91 and omap
  for things that are done in device drivers nowadays.

   - at91: move reset, poweroff, memory and clocksource code into
     drivers directories
   - socfpga: add edac driver (through arm-soc, as requested by Boris)
   - omap: move omap-intc code to drivers/irqchip
   - sunxi: added an RTC driver for sun6i
   - omap: mailbox driver related changes
   - keystone: support for the "Navigator" component
   - versatile: new reboot, led and soc drivers"

* tag 'drivers-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (92 commits)
  bus: arm-ccn: Fix spurious warning message
  leds: add device tree bindings for register bit LEDs
  soc: add driver for the ARM RealView
  power: reset: driver for the Versatile syscon reboot
  leds: add a driver for syscon-based LEDs
  drivers/soc: ti: fix build break with modules
  MAINTAINERS: Add Keystone Multicore Navigator drivers entry
  soc: ti: add Keystone Navigator DMA support
  Documentation: dt: soc: add Keystone Navigator DMA bindings
  soc: ti: add Keystone Navigator QMSS driver
  Documentation: dt: soc: add Keystone Navigator QMSS bindings
  rtc: sunxi: Depend on platforms sun4i/sun7i that actually have the rtc
  rtc: sun6i: Add sun6i RTC driver
  irqchip: omap-intc: remove unnecessary comments
  irqchip: omap-intc: correct maximum number or MIR registers
  irqchip: omap-intc: enable TURBO idle mode
  irqchip: omap-intc: enable IP protection
  irqchip: omap-intc: remove unnecesary of_address_to_resource() call
  irqchip: omap-intc: comment style cleanup
  irqchip: omap-intc: minor improvement to omap_irq_pending()
  ...
2014-10-08 17:37:16 -04:00
Linus Torvalds cf377ad7d4 ARM: SoC platform changes for 3.18
New and updated SoC support. Among the things new for this release are:
 
 - at91: Added support for the new SAMA5D4 SoC, following the earlier SAMA5D3
 - bcm: Added support for BCM63XX family of DSL SoCs
 - hisi: Added support for HiP04 server-class SoC
 - meson: Initial support for the Amlogic Meson6 (aka 8726MX) platform
 - shmobile: added support for new r8a7794 (R-Car E2) automotive SoC
 
 Noteworthy changes to existing SoC support are:
 
 - imx: convert i.MX1 to device tree
 - omap: lots of power management work
 - omap: base support to enable moving to standard UART driver
 - shmobile: lots of progress for multiplatform support, still ongoing
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.12 (GNU/Linux)
 
 iQIVAwUAVDWVHWCrR//JCVInAQJQVw/+NEfKWh6blDvLEWHpkmBtzdsT3s+r1wwb
 ATtvd1Q7RlOMEbzxc2J87tJ44yHb64mSPBbC4BCGuQsM5IIvM4potmBphl/XxLfd
 b8PNcI6nvLO+FZOcgon0JWmvVnt+vLGKPUWzURXSRjdrpVRg2qyRpW+nPBnvX4HP
 qyzlSskkYzKm7WJQrIV1K3yYwRLrVZdz4DuF340mSFy+4H+uci2Fw91HJ9lKKmPS
 24Klx2Q4n6wfg946WazWtz21HjEBuMzRCq0CGZrwcTJffRyMxa4iq/kqE3xGbPtN
 onuP1gmAM7UOMewEvc1ZLycY7JyZ3mhKnKduqS/QN2JLLQEY2v1iYFnEKP8mHnnw
 ax6RVi91PC2MSLZyPcRtsegSKB9l16I7H+C5pgTOMgsSaqxSG1JtV1qZl3uwhBnE
 GB45KHPvTFojrH2+CqneNTLET1ozKgwtuHkWTG61/puYeap/VlpRU2OWj2mQF2E0
 SiBzmlbUBpSqzjFgVGD4ywKAuVA/WpJtaOB7Qg26GL2QoNKrY/wsUCY8hU742+jE
 b/N6obGcpmjytLkFRHx+AbYc75DHXkPtF4CWawDeQFW30LUeixZJqewQ61a56QF8
 49DbO6J+sR0n3xlteD49QdQJzDCtKw3BV+VQaFRcxqVDq4LJAxtUHJZ7c3iyvzEi
 6Yt+PsqSP7Y=
 =ZHtj
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Arnd Bergmann:
 "New and updated SoC support.  Among the things new for this release
  are:

   - at91: Added support for the new SAMA5D4 SoC, following the earlier
     SAMA5D3
   - bcm: Added support for BCM63XX family of DSL SoCs
   - hisi: Added support for HiP04 server-class SoC
   - meson: Initial support for the Amlogic Meson6 (aka 8726MX) platform
   - shmobile: added support for new r8a7794 (R-Car E2) automotive SoC

  Noteworthy changes to existing SoC support are:

   - imx: convert i.MX1 to device tree
   - omap: lots of power management work
   - omap: base support to enable moving to standard UART driver
   - shmobile: lots of progress for multiplatform support, still
     ongoing"

* tag 'soc-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (171 commits)
  ARM: hisi: depend on ARCH_MULTI_V7
  CNS3xxx: Fix debug UART.
  ARM: at91: fix nommu build regression
  ARM: meson: add basic support for MesonX SoCs
  ARM: meson: debug: add debug UART for earlyprintk support
  irq: Export handle_fasteoi_irq
  ARM: mediatek: Add earlyprintk support for mt6589
  ARM: hisi: Fix platmcpm compilation when ARMv6 is selected
  ARM: debug: fix alphanumerical order on debug uarts
  ARM: at91: document Atmel SMART compatibles
  ARM: at91: add sama5d4 support to sama5_defconfig
  ARM: at91: dt: add device tree file for SAMA5D4ek board
  ARM: at91: dt: add device tree file for SAMA5D4 SoC
  ARM: at91: SAMA5D4 SoC detection code and low level routines
  ARM: at91: introduce basic SAMA5D4 support
  clk: at91: add a driver for the h32mx clock
  ARM: pxa3xx: provide specific platform_devices for all ssp ports
  ARM: pxa: ssp: provide platform_device_id for PXA3xx
  ARM: OMAP4+: Remove static iotable mappings for SRAM
  ARM: OMAP4+: Move SRAM data to DT
  ...
2014-10-08 17:13:04 -04:00
Robert Jarzmik 98d147f50e clk: pxa clocks build system fix
Fix the building of pxa clock drivers so that the files are actually
compiled if and only if COMMON_CLK was selected by the architecture.

This prevents conflicts with mach-pxa clock legacy implementation.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-10-05 13:41:53 -07:00
Mike Turquette a66993e05b clock mvebu changes for v3.18 (round 2)
- armada 370/375
     - Fix SSCG node lookup
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJULVYpAAoJEP45WPkGe8ZnSOAP/2V3KoDeaINR0cGG/u/YI/hp
 M5E4nZtRF9rZS3WMhULVjevcoddClDpvSJIvW34ZEI5uWc+kqkq+Q5Jj23t1oczq
 f5TqRDR2GenvxF1RbNGazZhLUJE6ubV1ADRKZNdRYfwR33RgrjRmWe2xrQ4vpemf
 58BSYbYwsrySd6s7KRJaSnSLrhxywPZCaisod4oquZF75cZ3W63V9RugHGADu/SZ
 gSxU+0bN4nbU8MFQxyaKq94FeyaAoDPkrMiSXAtjPQzl9a4zZd+BD/KArnf5LCs/
 kmRUfOQ38p4KIH9W49YRESZdh2/jUO+3hFTSsAKcXid7ZTadSH/WKHC4LCXH5Td6
 ST1fq0gGTPwDqULSCguw0n/UgIsn3D3fI3ruXuAAoV1S36Hzsh6n3dhZunfE9V/Y
 yKjf36GHT6g9a3CV3CEuSY18mLdDvkN9F/4A2mGhVHt11gl0JbaAKPb0D1GWzucP
 1N24NqCZ8/tOO4J3wseqvEW0imsZY4GB5CauJr9bgARaZhv2rjks79KExgpoTyk3
 ttDMl2JAspcZntHQQxVBGa3buux11SAH4jUdhtJC8BNGFXPo9XThNS2m+shseSJP
 UDlo6SWSMNohwAcWVSyEGkTHSe7Z2h3+PHDBKB8LwW8he9EIbCsxKJgk+Uz/gq8x
 8uMlUwJz1LajKur3+MSP
 =q4nx
 -----END PGP SIGNATURE-----

Merge tag 'clk-mvebu-3.18-2' of git://git.infradead.org/linux-mvebu into clk-next

clock mvebu changes for v3.18 (round 2)

 - armada 370/375
    - Fix SSCG node lookup
2014-10-03 16:43:02 -07:00
Masahiro Yamada 895ed4e895 kbuild: remove unnecessary "obj- := dummy.o" trick
In these Makefiles, at least one of "obj-y" and "obj-" is non-empty,
hence built-in.o is always created without such a trick.

Signed-off-by: Masahiro Yamada <yamada.m@jp.panasonic.com>
Acked-by: Peter Foley <pefoley2@pefoley.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Simon Horman <horms+renesas@verge.net.au> [shmobile]
Acked-by: David S. Miller <davem@davemloft.net> [networking]
Signed-off-by: Michal Marek <mmarek@suse.cz>
2014-10-02 13:55:02 +02:00
Mike Turquette a797900950 Allow parent rate changes for i2s on rk3288
and rockchip as well as s3c24xx restart handlers.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUK/GYAAoJEPOmecmc0R2Bnc8IAJY3NpUhN2It0WqL1meeIDr7
 jGVphxhiEsAlXMbHyO0V/LhUTbGtjfDotd43Y84cZW43R7G2ErvvBsWMKCff2xIB
 cVtjXJ8JI+s2T/gBEssZDnhh1dcP04fnZ2LMdLCGudnmn2AyR2AXQQBqFiO+kQWe
 0x2dsGgcQPn93X9i9sT03BKJTZjRoCZkUh0aJ2y+yL9Y5A9CNXCVGfJ5E1GNw3Px
 ffeKA0OsOhUMw9aqb8fLvDuRd0mo1i+BSCaOeNTlwzASmxCUJ9MOOKtF/Khx7x2r
 6N3w/EN4F8R+qJ/gOyZR9I3SrnLU1rMBOHvaSxDJb0RXAq5AROvQS1t4GiF2A68=
 =bvGz
 -----END PGP SIGNATURE-----

Merge tag 'v3.18-rockchip-clk2' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

Allow parent rate changes for i2s on rk3288
and rockchip as well as s3c24xx restart handlers.
2014-10-01 11:19:10 -07:00
Heiko Stübner e317c19470 clk: samsung: register restart handlers for s3c2412 and s3c2443
S3C2412, S3C2443 and their derivatives contain a special software-reset
register in their system-controller.

Therefore register a restart handler for those.

Tested on a s3c2416-based board, s3c2412 compile-tested.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-10-01 14:14:46 +02:00
Heiko Stübner 6f1294b5a8 clk: rockchip: add restart handler
Add infrastructure to write the correct value to the restart register and
register the restart notifier for both rk3188 (including rk3066) and rk3288.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Guenter Roeck <linux@roeck-us.net>
2014-10-01 14:11:42 +02:00
Jianqun fc69ed70c1 clk: rockchip: rk3288: i2s_frac adds flag to set parent's rate
The relation of i2s nodes as follows:
          i2s_src               0           0            594000000  0
             i2s_frac           0           0            11289600   0
                i2s_pre         0           0            11289600   0
                   sclk_i2s0    0           0            11289600   0
                   i2s0_clkout  0           0            11289600   0
                      hclk_i2s0 1           1            99000000   0

sclk_i2s0 is the master clock, when to set rate of sclk_i2s0, should
allow to set its parent's rate, by add flag CLK_SET_RATE_PARENT for
"i2s_frac", "i2s_pre", "i2s0_clkout" and "sclk_i2s0".

Tested on rk3288 board using max98090, with command "aplay <music.wav>"

Change-Id: I12faad082566532b65a7de8c0a6845e1c17870e6
Signed-off-by: Jianqun <jay.xu@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-10-01 10:55:13 +02:00
Mike Turquette 38bf3a7978 Merge branch 'clk-pxa27x' into clk-next 2014-09-30 12:49:42 -07:00
Robert Jarzmik d40670dc61 clk: add pxa27x clock drivers
Move pxa27x clock drivers from arch/arm/mach-pxa to driver/clk.
In the move :
 - convert to new clock framework legacy clocks
 - provide clocks as before for platform data based boards
 - provide clocks through devicetree

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30 12:31:31 -07:00
Robert Jarzmik bda0030366 clk: add pxa clocks infrastructure
Add a the common code used by all PXA variants.

This is the first step in the transition from architecture defined
clocks (in arch/arm/mach-pxa) towards clock framework. The goal is to
have the same features (and not all the features) of the existing
clocks, and enable the transition of PXA to device-tree.

All PXA rely on a "CKEN" type clock, which :
 - has a gate (bit in CKEN register)
 - is generated from a PLL, generally divided
 - has an alternate low power clock

Each variant will specialize the CKEN clock :
 - pxa25x have no low power clock
 - pxa27x in low power use always the 13 MHz ring oscillator
 - pxa3xx in low power have specific dividers for each clock

The device-tree provides a list of CLK_* (ex: CLK_USB or CLK_I2C) to get
a handle on the clock. While pxa-clock.h will describe all the clocks of
all the variants, each variant will only use a subset of it.

Signed-off-by: Robert Jarzmik <robert.jarzmik@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30 12:31:30 -07:00
Mark Brown 44b4aa97be clk: gpio-gate: Ensure gpiod_ APIs are prototyped
The gpio-gate clock uses the gpiod_ APIs but does not directly include the
header for them causing build failures in some configurations including ARM
allnoconfig. Include the header directly.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-30 11:57:54 -07:00
Mike Turquette 24afc3852e Samsung clock patches for v3.18
1) non-critical fixes (without the need to push to stable)
 
 fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
 b511593d71 clk: samsung: exynos4: fix g3d clocks
 c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
 22842d244a clk: samsung: exynos5260: fix typo in clock name
 e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
 59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
 5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list
 
 2) Clock driver extensions
 
 07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
 d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
 e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
 4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJUKcEKAAoJEIv3Hb8G/XruW/cP/34kC45bvMqXIIcDHq3CRRpG
 i3HgG3mJb/rSzE4rDMPBtBXmkp45tHfOh4npdw5Db/+Kpb6m22X0yEYmGtH5Yfpw
 thQEuAeCjL5jDob/YjbPHH1PeoBHy5LS5wgwaJIC/aLQj6od31mgWZabYpeVX3AE
 flrWoxVmFVWGUKqfk2hJMY7RVuJcNw2CyIJ/jK0V3zh05GM9e8sFulXY3vellofW
 6aSaRYWqD7QYlf9VSU0ECHpCoFTIRCDh0k/yafDZrvOyKuWfyvGYorGnLh3wE7S7
 bPi+fo47WKRtoiKEeQDa0egxq/fl0ksp3kubWZq09EQYKQE/pMHayCYyImxGyAeK
 gy0M6E8M3Xwf+Slg+xKrNRP89ExfW0ymTbaNMgKJf96ocQjSH93rcPZGrXhrPILT
 CV8jWNRSjNcAfAvuzH2CZiLfCrc9phTbz3WEce8D8zf14fPOkGrYQB0GMr1+HUj1
 4LL/3JcCt/3wrliSVim3eSf1lgUCLKocMM1lrzzc7JhBamKvesKU2gw+RRSg9Pe5
 gg7RPCSgQMieGp1yO8nNkbmZhhXPNIXoEHjMlS1XTymBHiG+24f1mX7Q/nfGD5mY
 VP7LKeLUIYKPQZlvM9d9Ko2Xt13ypDZLGAM/bmEtOoibeNbELbfzeIxiUkgkB6rE
 uADWSEd6SDyV+E6nK62z
 =MsKp
 -----END PGP SIGNATURE-----

Merge tag 'for_3.18/samsung-clk' of git://git.kernel.org/pub/scm/linux/kernel/git/tfiga/samsung-clk into clk-next

Samsung clock patches for v3.18

1) non-critical fixes (without the need to push to stable)

fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
b511593d71 clk: samsung: exynos4: fix g3d clocks
c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
22842d244a clk: samsung: exynos5260: fix typo in clock name
e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list

2) Clock driver extensions

07ccf02ba5 dt-bindings: clk: samsung: Document the DMC domain of Exynos3250 CMU
d0e73eaf19 ARM: dts: exynos3250: Add CMU node for DMC domain clocks
e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
2014-09-29 23:43:12 -07:00
Mike Turquette 82de1bc86c Merge branch 'for-v3.18/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-next 2014-09-29 23:38:59 -07:00
Peter Ujfalusi 04ed831f22 clk: ti: dra7-atl-clock: Mark the device as pm_runtime_irq_safe
It is safe to call the pm sync calls in interrupt context in this driver.

Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:14 +03:00
Behan Webster e8627a9ec3 clk: ti: LLVMLinux: Move __init outside of type definition
As written, the __init for ti_clk_get_div_table is in the middle of the return
type.

The gcc documentation indicates that section attributes should be added to the
end of the function declaration:

  extern void foobar (void) __attribute__ ((section ("bar")));

However gcc seems to be very permissive with where attributes can be placed.
clang on the other hand isn't so permissive, and fails if you put the section
definition in the middle of the return type:

drivers/clk/ti/divider.c:298:28: error: expected ';' after struct
static struct clk_div_table
                           ^
                           ;
drivers/clk/ti/divider.c:298:1: warning: 'static' ignored on this
      declaration [-Wmissing-declarations]
static struct clk_div_table
^
drivers/clk/ti/divider.c:299:9: error: type specifier missing,
      defaults to 'int' [-Werror,-Wimplicit-int]
__init *ti_clk_get_div_table(struct device_node *node)
~~~~~~  ^
drivers/clk/ti/divider.c:345:9: warning: incompatible pointer types
      returning 'struct clk_div_table *' from a function with result type 'int *' [-Wincompatible-pointer-types]
        return table;
               ^~~~~
drivers/clk/ti/divider.c:419:9: warning: incompatible pointer types
      assigning to 'const struct clk_div_table *' from 'int *' [-Wincompatible-pointer-types]
        *table = ti_clk_get_div_table(node);
               ^ ~~~~~~~~~~~~~~~~~~~~~~~~~~
3 warnings and 2 errors generated.

By convention, most of the kernel code puts section attributes between the
return type and function name. In the case where the return type is a pointer,
it's important to place the '*' on left of the __init.

This updated code works for both gcc and clang.

Signed-off-by: Behan Webster <behanw@converseincode.com>
Reviewed-by: Mark Charlebois <charlebm@gmail.com>
Reviewed-by: Felipe Balbi <balbi@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:14 +03:00
Sebastian Andrzej Siewior 319f1276f9 clk: ti: consider the fact that of_clk_get() might return an error
I "forgot" to update the dtb and the kernel crashed:
|Unable to handle kernel NULL pointer dereference at virtual address 0000002e
|PC is at __clk_get_flags+0x4/0xc
|LR is at ti_dt_clockdomains_setup+0x70/0xe8

because I did not have the clock nodes. of_clk_get() returns an error
pointer which is not checked here.

Acked-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Sebastian Andrzej Siewior <bigeasy@linutronix.de>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-09-29 11:51:13 +03:00
Tero Kristo 73b5d5f711 clk: ti: dra7-atl-clock: fix a memory leak
of_clk_add_provider makes an internal copy of the parent_names property
while its called, thus it is no longer needed after this call and can
be freed.

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
2014-09-29 11:51:13 +03:00
Tero Kristo c08ee14cc6 clk: ti: change clock init to use generic of_clk_init
Previously, the TI clock driver initialized all the clocks hierarchically
under each separate clock provider node. Now, each clock that requires
IO access will instead check their parent node to find out which IO range
to use.

This patch allows the TI clock driver to use a few new features provided
by the generic of_clk_init, and also allows registration of clock nodes
outside the clock hierarchy (for example, any external clocks.)

Signed-off-by: Tero Kristo <t-kristo@ti.com>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Peter Ujfalusi <peter.ujfalusi@ti.com>
Cc: Jyri Sarha <jsarha@ti.com>
Cc: Stefan Assmann <sassmann@kpanic.de>
Acked-by: Tony Lindgren <tony@atomide.com>
2014-09-29 11:51:13 +03:00
Mike Turquette 6e18ff26c2 Hisilicon HiX5HD2 clock updates for 3.18-v2
- Add I2C clocks
 - Add watchdog clocks
 - Add sd clocks
 - Add complex clock implementation to support sata, usb and ethernet
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJUJ3bFAAoJEGROujcbgXtLdJMP/3OV7vktoDknOi50sJPb4CRj
 qjGxQ7XcHLCwvzTdnTcorV3x8t8iNReaG2QiESVJA62criTJSxG9/rNK8N6z2233
 X8VAZDBIRY2aa8T/jAwHQKTNspQTxIeaBxJ63IqFss3kfsQS9haQZoBAnFciiFLu
 5qIrJilVRkpWbXst5XAYLfNy5bLzBJNjUcO8N6JrLI+0yE9vIIxcLtNuUBNAdqi1
 hiNxeLIrKmQ4RTobZWCm2BuvW89NTgi1xf+hnLWq6F+e98auGvIoXOHZoF5X58pc
 eeI8e2r1TcnmcSR96zwesGUelUlfMXKJ7JM2GVKt1kCINyCFFKYGe3evTCRK0+8W
 9t8NkJh43x30prcJUM4X8cv2P+tzUTRSgcJqDNqmdNPiaPo7f2QlolyeaO53o+I4
 vGydbl0vawk1sHWWE4fRRPXlWK+BWV3Pd0XbLneU2QVlULKyJGGpWWtj4sG+B0oe
 HF7aelZwVWVy2VoUihZ9f2R3PW1f2MOMzkv25QvOpYlb3/rhjPNVu/+TsBnMbk+3
 tf5vZpo7KoZ6AD7EwayhsJc3R0RGwsHx7V422cy6FLbQum0ILG9yWEvLGtzT6gkw
 Nt/F3LhDSfJbnFwGrW29aSYp3NTEXSS4rY3Y038VV1Apc1UhqK1RaR4uCFQUIHce
 PJO8lHp8gyTA/++yfM01
 =Fqwn
 -----END PGP SIGNATURE-----

Merge tag 'hix5hd2-clock-for-3.18-v2' of git://github.com/hisilicon/linux-hisi into clk-next

Hisilicon HiX5HD2 clock updates for 3.18-v2

- Add I2C clocks
- Add watchdog clocks
- Add sd clocks
- Add complex clock implementation to support sata, usb and ethernet
2014-09-28 10:47:15 -07:00
Wei Yan 45bcf9c6f2 clk: hix5hd2: add I2C clocks
hix5hd2 add I2C clocks (I2C0~i2C5)

Signed-off-by: Wei Yan <sledge.yanwei@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:09 +08:00
Guoxiong Yan 1463fba39c clk: hix5hd2: add watchdog0 clocks
hix5hd2 add watchdog0 clocks

Signed-off-by: Guoxiong Yan <yanguoxiong@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:04 +08:00
Jiancheng Xue cc855dd999 clk: hix5hd2: add sd clk
Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:27:01 +08:00
Zhangfei Gao 20e0755859 clk: hix5hd2: add complex clk
Support clk of sata, usb and ethernet

Signed-off-by: Jiancheng Xue <xuejiancheng@huawei.com>
Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2014-09-28 10:26:49 +08:00
Xiubo Li 7af4724857 clk: use uninitialized_var instead setting 'flags' to 0 directly.
Setting 'flags' to zero will be certainly a misleading way to avoid
warning of 'flags' may be used uninitialized. uninitialized_var is
a correct way because the warning is a false possitive.

Signed-off-by: Xiubo Li <Li.Xiubo@freescale.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-27 16:03:06 -07:00
Mike Turquette 4dc7ed32f3 Allwinner Clocks Additions for 3.18
The most important part of this serie is the addition of the phase API to
 handle the MMC clocks in the Allwinner SoCs.
 
 Apart from that, the A23 gained a new mbus driver, and there's a fix for a
 incorrect divider table on the APB0 clock.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJUJm3zAAoJEBx+YmzsjxAgxJwQAJk3+Oq3J54jzRxKLGjUpfy9
 Ma9p/78ZSnYlYWrEn62vzu7sGeMJsPo4Lsmy+Hch2r765+PzFZw9oDaxjFT5poQy
 Mv8F7Uyetc99sGAfmg/fKnzgQpp1t+9+kB42cV6lzjXolqX/ACcIjzFOzROXEF9B
 2bnQ3RwXqvQhKKryDBg9+hJYt1R15d4SxQ7Rn6lb6WsZTxjGVO0cvvU3tp4QGQgg
 ZDUkJNLzLYdMK9XUNyqreatmz+HMxL5vYHeEWFz388ECp9DRUPT3MqlQcUqgSLlD
 eMqQPOnd5p5ZEUdB8qAAtf4kIbQTaVa7/4u37sE/+fogw6Pq/6a2Jqppl9aJWD7I
 PDFjxSMl77W5mQZSEanbc0a0qmqAqtZokDusP0bc0ETSZzmPVvohjW5Fa9Awyi0j
 PeN2bTglaFDPsHxKlQ31HF/e/almXkpiIXegeG0e/3VrGSrghFMQtqLEUXgVPu10
 4PV8x7O2ib1VVAowwOb10qGv0fLGC8UCqL9zXVNlCy268ijjKMlNyK3U1sllphba
 fWBYgtg9+1YHONI1SewuYibAqROC7ICDXiqDkJVb6UWmO39HBcOFDb3HJ0EIj8T4
 9v1clkVy1vONIqfvi1SeTekLovpROOxhxGtyXTpdx5qdlVhBjkEsNVHc5jh6BPHr
 o9TlBnnmIPajvF9wMN+H
 =ZkI9
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into clk-next

Allwinner Clocks Additions for 3.18

The most important part of this serie is the addition of the phase API to
handle the MMC clocks in the Allwinner SoCs.

Apart from that, the A23 gained a new mbus driver, and there's a fix for a
incorrect divider table on the APB0 clock.
2014-09-27 12:52:33 -07:00
Mike Turquette 5ad67d3e5e CPU clock handling for Rockchip SoCs
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQEcBAABCAAGBQJUJt+NAAoJEPOmecmc0R2BzmEH/00GYMLZZZrhUUBzF5+O5Wvu
 2jjVwZkyDsEL7Dnhen45Z+2umoXat8TbgNoeX+BbLEj55ntfAv1aNV62gO/wLrJy
 GbUDeAMNLXnJsF3UefBHvDf1F7SOZAm7QPs9oYQMyUDQqzsorfuDjKDPPLAHoiO9
 7TfVxLYqkd4lVm0cYo4tMYTgONK2QR6iKEGHHkXIsKZXMdd2gMAxuTIjBcTqbBu1
 9Hxt9P2G9InmRaSmW4zXzMlur0it16BnFt2wnJGoawBZkkwnvkze54APQgA4GV61
 tqUhh94mQdAzJd1wMtJASK6ZY79pjv9pmGgQ5kNVlDV0SaSafZ1MhQU4k7NdemQ=
 =myeX
 -----END PGP SIGNATURE-----

Merge tag 'v3.18-rockchip-cpuclk' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into clk-next

CPU clock handling for Rockchip SoCs
2014-09-27 12:50:40 -07:00
Heiko Stuebner 0e5bdb3f9f clk: rockchip: switch to using the new cpuclk type for armclk
This adds the necessary soc-specific divider values and switches the armclk
to use the newly introduced cpuclk type.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:46 +02:00
Heiko Stuebner f6fba5f696 clk: rockchip: add new clock-type for the cpuclk
When changing the armclk on Rockchip SoCs it is supposed to be reparented
to an alternate parent before changing the underlying pll and back after
the change. Additionally there exist clocks that are very tightly bound to
the armclk whose divider values are set according to the armclk rate.

Add a special clock-type to handle all that. The rate table and divider
values will be supplied from the soc-specific clock controllers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
On a rk3288-board:
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:41 +02:00
Heiko Stuebner 2b9bceeab7 clk: rockchip: make tightly bound armclk child-clocks read-only
Rockchip SoCs contain clocks tightly bound to the armclk, where the best
rate / divider is supplied by the vendor after careful measuring.
Often this ideal rate may be greater than the current rate.

Therefore prevent the ccf from trying to set these dividers itself by
setting them to read-only.

In the case of the rk3066, this also includes the aclk_cpu, which makes it
necessary to also split its direct child-clocks (pclk_cpu, hclk_cpu, ...)
into individual definitions for rk3066 and rk3188.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:17 +02:00
Heiko Stuebner f5f7004fde clk: rockchip: reparent aclk_cpu_pre to the gpll
aclk_cpu_pre on the rk3188 can either be sourced from the armclk or the gpll.
To reduce complexity on apll changes caused by cpufreq, reparent it always
to the gpll source.

If really necessary it could be reparented back on a per board level using
the assigned-clocks mechanism.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:14 +02:00
Jianqun ee17eb83c4 clk: rockchip: fix rk3288 pll status register location
In RK3288, APLL lock status bit is in GRF_SOC_STATUS1,
but in RK3188, is GRFSOC_STATUS0.

Signed-off-by: Jianqun <jay.xu@rock-chips.com>

Also name the constant accordingly as GRF_SOC_STATUS1
to prevent confusion.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
2014-09-27 17:57:10 +02:00
Heiko Stuebner 11ff376fcf clk: rockchip: fix rk3066 pll status register location
The register providing the pll lock status is at a different address on the
rk3066. The error became apparent while working on cpufreq support for
the rockchip SoCs.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:07 +02:00
Doug Anderson 9c030ea70b clk: rockchip: change pll rate without a clk-notifier
The Rockchip PLL code switches into slow mode (AKA bypass more AKA
24MHz mode) before actually changing the PLL.  This keeps anyone from
using the PLL while it's changing.  However, in all known Rockchip
SoCs nobody should ever see the 24MHz when changing the PLL supplying
the armclk because we should reparent children to an alternate
(faster than 24MHz) PLL.

One problem is that the code to switch to an alternate parent was
running in PRE_RATE_CHANGE.  ...and the code to switch to slow mode
was _also_ running in PRE_RATE_CHANGE.  That meant there was no real
guarantee that we would switch to an alternate parent before switching
to 24MHz mode.

Let's move the switch to "slow mode" straight into
rockchip_rk3066_pll_set_rate().  That means we're guaranteed that the
24MHz is really a last-resort.

Note that without this change on real systems we were the code to
switch to an alternate parent at 24MHz.  In some older versions of
that code we'd appy a (temporary) / 5 to the 24MHz causing us to run
at 4.8MHz.  That wasn't enough to service USB interrupts in some cases
and could lead to a system hang.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2014-09-27 17:57:04 +02:00
Chen-Yu Tsai 9c8176bfb6 clk: sunxi: Add sun8i MBUS clock support
The MBUS clock on sun8i is slightly different from the old mod0 clocks.
The divider is 3 bits wider, while also needing a divider table for the
higher 4 values, which all set the same divider.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-27 09:05:43 +02:00
Maxime Ripard 37e1041f04 clk: sunxi: mod0: Introduce MMC proper phase handling
The MMC clock we thought we had until now are actually not one but three
different clocks.

The main one is unchanged, and will have three outputs:
  - The clock fed into the MMC
  - a sample and output clocks, to deal with when should we output/sample data
    to/from the MMC bus

The phase control we had are actually controlling the two latter clocks, but
the main MMC one is unchanged.

We can adjust the phase with a 3 bits value, from 0 to 7, 0 meaning a 180 phase
shift, and the other values being the number of periods from the MMC parent
clock to outphase the clock of.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:04 +02:00
Maxime Ripard eaa18f5d09 clk: sunxi: Move mbus to mod0 file
Move the MBUS clock to the module clocks file. It's pretty trivial, but still
requires to enable the clocks to make sure it won't get disabled.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:03 +02:00
Maxime Ripard 992a56e489 clk: sunxi: Move mod0 clock to a file of its own
Since we know have the ability to declare factors clock outside of clk-sunxi,
create a new mod0 driver to deal with the mod0 clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:03 +02:00
Maxime Ripard 03e29bbf40 clk: sunxi: Introduce mbus compatible
Even though the mbus clock is a regular module clock, given its nature, it
needs to be enabled all the time.

Introduce a new compatible, to differentiate it from the other module clocks.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:02 +02:00
Maxime Ripard 601da9d0a5 clk: sunxi: factors: Invert the probing logic
Until now, the factors clock probing was done directly by sunxi_init_clocks,
with the factors registration being called directly with the clocks data passed
as an argument.

This approch has shown its limits when we added more clocks, since we couldn't
really split code with such a logic in smaller files, and led to a huge file
having all the clocks.

Introduce an intermediate probing function, so that factor clocks will be able
to directly be called by CLK_OF_DECLARE, which will in turn ease the split into
several files.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:58:01 +02:00
Maxime Ripard 9824cf73c3 clk: Add a function to retrieve phase
The current phase API doesn't look into the actual hardware to get the phase
value, but will rather get it from a variable only set by the set_phase
function.

This will cause issue when the client driver will never call the set_phase
function, where we can end up having a reported phase that will not match what
the hardware has been programmed to by the bootloader or what phase is
programmed out of reset.

Add a new get_phase function for the drivers to implement so that we can get
this value.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:57:51 +02:00
Mike Turquette e59c5371fb clk: introduce clk_set_phase function & callback
A common operation for a clock signal generator is to shift the phase of
that signal. This patch introduces a new function to the clk.h API to
dynamically adjust the phase of a clock signal. Additionally this patch
introduces support for the new function in the common clock framework
via the .set_phase call back in struct clk_ops.

Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Hans de Goede <hdegoede@redhat.com>
2014-09-27 08:57:38 +02:00
Mike Turquette 8791db53a9 clock changes for mvebu for v3.18
- correct timer drift caused by SSCG deviation
  - fix typo in comment
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v2
 
 iQIcBAABAgAGBQJUFVIYAAoJEP45WPkGe8Zns1MQAJeD6jSRzNyqc5Hn0Z2+ibGK
 TQhFcGF2KTySOSnqP7OpdR/LQXaKIb8bcbslfG7FZBXICEVpkHBibf4DoHQtEwoY
 fx1QB73jio3ks9UGpQgVPFTgysfxHsuL8/RTT6QOeyUU8Z0pyOSjDqWDh7z5ZPjY
 aaiT9Ckq1KRzSkMGRqeXZgSqR2lPG1UYet49AlLp1QpjR7i7WfQuQ2W07D2YJQfy
 ault8QKMhNKQ2U8sB69IV/hBpkf6GAKSos8KMAH0+FwxzlfsP5gMTLUyhxFDQ5sA
 4d8qYEPTPj4Acw+uSVI8EDlCWMTyMASCi+Tk6eY9wy2j8zPbfuw1IKtsXqVf3eu9
 huIkdrcLlVeQNnSEu7M35GLCmNVc0bG2qKQKSvrJhaDmVSP+5fVP7jJdStDHVhC/
 GViuJ8SpS147oTV7yL3hh12UNIORsjvjB+MZL7g60bnHyuAEU5Sd0vQBdqcTqBnF
 VE1qMawGdI6lzulhGJ4j+yz766ut9x1je9DwLtj218pfyg0nvg4ujrxF2yGkYdVE
 tQahztzH3DaAX+wPoCybM+HFEtXmlX773Q0TkU7XA7XeFTkXUz5b/CY/A6HertCE
 4sGNxw2Wn8m6kvMVkFJ4oKN8VEFvu73SOWmq9Hz9apYMVWvwFeDplqt4zUjb7oCa
 1Oofky2uBsHpXYa0v9Yi
 =CGwg
 -----END PGP SIGNATURE-----

Merge tag 'clk-mvebu-3.18' of git://git.infradead.org/linux-mvebu into clk-next

clock changes for mvebu for v3.18

 - correct timer drift caused by SSCG deviation
 - fix typo in comment
2014-09-26 17:04:08 -07:00
Jyri Sarha c873d14d30 clk: add gpio gated clock
The added gpio-gate-clock is a basic clock that can be enabled and
disabled trough a gpio output. The DT binding document for the clock
is also added. For EPROBE_DEFER handling the registering of the clock
has to be delayed until of_clk_get() call time.

Signed-off-by: Jyri Sarha <jsarha@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-26 16:51:42 -07:00
Mike Turquette db0bcc33a8 qcom clock changes for 3.18
Some fixes for the IPQ driver and some code consolidation
 and refactoring.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABCAAGBQJUIJ/oAAoJENidgRMleOc94WoP/1f7pk2ZWZzLPF1WRDwff0Ng
 71g5iRYhzwxHvM5bgMLBtBRaDGY9Q2aUPPAfJNYF76foR3CPwB0XPVPk+vNaJGl7
 Yxwighg9wNz904dVKsEeErmdaHZKzQCtser6/aj43EWRMfwoT9OLgwKJApVaVoUz
 bTMEKLN/HEcp/FECShulfvk9qnvMCKckxuRidl01UwXv/Ha3Em84MkxAGJZmbGha
 RGcvlkU5E06x6FEhtWM/lk2UoFTX1D2+tIugt05q3eUSvt93zy/9tGYqiaeHKO5w
 AaYS09qYNCrbW6LovlATv6hecwfVvMliT6uz9us+dk2vzqdtjcwaXldOouWr/7H2
 M62aQIUJg7QpS5p28WnUcNhv4rJUT7+sRrGmsgVRx0Amn/97Ed/v62y9cyPjWsou
 6QKehahf/Kq690M/jWU3vkanWvszFHZ/dw+GsAPSlx9kHZAUbSqim1x/zlaKZ+S7
 nh3v6glwlhFCogdBDOZr1nPiFFGK2VESukFmWU12qA0huqEQ7rh0eLB2HBwN8neu
 Leli/e7vnjcuhqjixqlrZGXv/O8cU8EHW1VCtP4FyiLZTBVe7nlWMARdgCYcauC/
 cWNsO6FlU6y0qqpFCZ+p+nUU2+/n1tnfzzS/j55pzwp6keqt5lJcUL/yHOP8mhez
 ewruBUdui4U1gFjazfj0
 =fPIM
 -----END PGP SIGNATURE-----

Merge tag 'qcom-clocks-for-3.18' of git://git.kernel.org/pub/scm/linux/kernel/git/galak/linux-qcom into clk-next

qcom clock changes for 3.18

Some fixes for the IPQ driver and some code consolidation
and refactoring.
2014-09-26 16:10:57 -07:00
Mike Turquette b6b2fe5b6e Tegra clk updates for 3.18
-----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQIcBAABAgAGBQJUHBvYAAoJEFFb18rurjwTyaoP/37XBxRXfN2mL+WroUC7rb4m
 qb7PKg0RTOjjWV6Dp2EzmXThxsy0sGRpML9ZNp6LYIqPOH4sBHNeRK0+Qf1dB1XZ
 /DySj4oqEgJ+x8GHTqceM5x4C5fwDrF4sl5uacYIZcA42ih3nY331zlJaNPpkSpx
 iP91SJsQghK9OpdnOTl8oOV9p6PIjFfn712GPIRL7PBIBkVswdkJHufozzvcX+mI
 O30/FGEGbQCmCs1pFXufFNwJQcOy0qK5zyZPhGbzyji9gkCXz4OQOqWLdE1kXbWY
 CDfolp0Xdr+hLN/6YkQBEkZSjvKzLZf8OOYmVsXWXplVDjLf9/2p/Kq33p8JGKUa
 R8BC17MtmKjNgJ7g0Zo870meRWDcsLOfr60Wu4MIhzSJKSVDp6oq0ZqYay10/ZuF
 iMv49Mcpbgl4d0D6DgJztMPYwQZrMOkTLByGo+s/UxB+gY2XtvUO/6mPchYfhYUX
 M7y28Im4j5pmTKw5WhulfDWTBUPul8tvqGLdB4i9zKOA0iszby7pnGzjKfZd4RYg
 FD5Byzd225X92R/kKxWPTv4SQBM7flVkfvJLbOV2SiedoCHcyLXJjtSgaFlE3XYY
 gUt9uqM5cwiw6hwPVzP1su02419L6cZYkCWOlVMNlMZ3fjd6js6NUtNjxH30tU7H
 TrwJ4tAYaIkuTw0jBnFE
 =WIPU
 -----END PGP SIGNATURE-----

Merge tag 'tegra-clk-3.18' of git://nv-tegra.nvidia.com/user/pdeschrijver/linux into clk-next

Tegra clk updates for 3.18
2014-09-26 16:09:39 -07:00
Kiran Padwal 59c0621d4d clk: Remove .owner field for driver
There is no need to init .owner field.

Based on the patch from Peter Griffin <peter.griffin@linaro.org>
"mmc: remove .owner field for drivers using module_platform_driver"

This patch removes the superflous .owner field for drivers which
use the module_platform_driver API, as this is overriden in
platform_driver_register anyway."

Signed-off-by: Kiran Padwal <kiran.padwal@smartplayin.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 17:43:31 -07:00
Mike Turquette fa531042ac Merge branch 'clk-next-rockchip' into clk-next 2014-09-25 15:48:04 -07:00
Kever Yang cd24850292 clk: rockchip: add clock node in PD_VIDEO
This patch add the clock node in PD_VIDEO

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 15:47:45 -07:00
Arnd Bergmann 6d50424a39 Second SoC batch for 3.18:
- introduction of the new SAMA5D4 SoC and associated Evaluation Kit
 - low level soc detection and early printk code
 - taking advantage of this, documentation of all AT91 SoC DT strings
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.11 (GNU/Linux)
 
 iQEcBAABAgAGBQJUIB6OAAoJEAf03oE53VmQL+IIALNg2XPS49u2Y6VMjL3srFLt
 7CUdNoGB7GJKoGrIXPSyAhJLkRlWREgRsEk/RSYqfBpyBZV4PIx9R6dIz1L+VxGU
 9neXLkZGrYNzN8qJPz82+ARuCXdCF13N8ClVfXkNDhwbDnlbZgTkh4hNV118mKLt
 +PF0d3w354ujieUD7D0pOcdRlny487qMNjtc/0U4P+H2sp2EtL0PpFHicn79InPT
 V36PpFtUMEgbw2wQPNtlFkjQWstyZ7WJJGUbIX/2P3PASCwKsgrbmkvDvmfp5tUT
 FdclJwJnxgcpni2fDvbz8Vq04i3hixl2Olm8tAvIXOI/hdVcurvZSfweJ5BrfDk=
 =fMfO
 -----END PGP SIGNATURE-----

Merge tag 'at91-soc2' of git://github.com/at91linux/linux-at91 into next/soc

Pull "Second SoC batch for 3.18" from Nicolas Ferre:

- introduction of the new SAMA5D4 SoC and associated Evaluation Kit
- low level soc detection and early printk code
- taking advantage of this, documentation of all AT91 SoC DT strings

Signed-off-by: Arnd Bergmann <arnd@arndb.de>

* tag 'at91-soc2' of git://github.com/at91linux/linux-at91:
  ARM: at91: document Atmel SMART compatibles
  ARM: at91: add sama5d4 support to sama5_defconfig
  ARM: at91: dt: add device tree file for SAMA5D4ek board
  ARM: at91: dt: add device tree file for SAMA5D4 SoC
  ARM: at91: SAMA5D4 SoC detection code and low level routines
  ARM: at91: introduce basic SAMA5D4 support
  clk: at91: add a driver for the h32mx clock
2014-09-26 00:15:09 +02:00
Kever Yang 89d83e14f4 clk: rockchip: use the clock id for nodes init
This patch use the new defined clock ID to initial the clock nodes.

Signed-off-by: Kever Yang <kever.yang@rock-chips.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 15:06:43 -07:00
Heiko Stübner d1a559a1cb clk: rockchip: add missing rk3288 npll rate table
The npll on rk3288 is exactly the same pll type as the other 4. Yet it
was missing the link to the rate table, making rate changes impossible.
Change that by setting the table.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 14:48:40 -07:00
Mark yao f9c0d14062 clk: rockchip: rk3288: fix softreset register count
The rk3288 actually has 12 softresets, so fix the register count.

Signed-off-by: Mark yao <mark.yao@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-25 14:45:58 -07:00
Thomas Abraham fa0111be4f clk: samsung: exynos4: remove duplicate div_core2 divider clock instantiation
The 'div_core2' clock and the 'arm_clk' divider clocks are instances of
the same divider clock. So remove the 'arm_clk' clock instance.

Signed-off-by: Thomas Abraham <thomas.ab@samsung.com>
[tomasz.figa@gmail.com: Fixed remaining occurences of 'arm_clk'.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-24 12:41:33 +02:00
Stephen Boyd 229fd4a505 clk: qcom: Add support for banked MD RCGs
The banked MD RCGs in global clock control have a different
register layout than the ones implemented in multimedia clock
control. Add support for these types of clocks so we can change
the rates of the UBI32 clocks.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22 15:16:54 -07:00
Stephen Boyd ae3669ac5c clk: qcom: Add support for setting rates on PLLs
Some PLLs may require changing their rate at runtime. Add support
for these PLLs.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22 15:16:53 -07:00
Stephen Boyd 50c6a50344 clk: qcom: Consolidate frequency finding logic
There are two find_freq() functions in clk-rcg.c and clk-rcg2.c
that are almost exactly the same. Consolidate them into one
function to save on some code space.

Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22 15:16:52 -07:00
Andy Gross dc1b3f657f clk: qcom: Add IPQ8064 PLL required for USB
This patch adds the PLL0 that is required for the USB clocks to
work properly.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Fixes: 24d8fba44a "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
2014-09-22 15:16:52 -07:00
Marek Szyprowski b511593d71 clk: samsung: exynos4: fix g3d clocks
sclk_g3d clock doesn't have enable/disable bits, but the driver hijacked
g3d gate clock bits for this purpose and didn't provide real g3d clock
at all. This patch fixes this issue by adding proper definition for g3d
clock and removing incorrect access to GATE_IP_G3D register in sclk_g3d.
In addition CLK_SET_RATE_PARENT flag is dropped from sclk_g3d, because
it does not make any sense and most likely has been added by mistake.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
[tomasz.figa@gmail.com: Adjusted commit message.]
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:19 +02:00
Marek Szyprowski 4676f0aab9 clk: samsung: exynos4: add support for MOUT_HDMI and MOUT_MIXER clocks
This patch adds support for exporting mout_hdmi and mout_mixer to device
tree. Access to those clocks is required to correctly setup HDMI module
on Exynos 4210 and 4x12 SoCs.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
CC: Mike Turquette <mturquette@linaro.org>
CC: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:14 +02:00
Marek Szyprowski c142543001 clk: samsung: exynos4: add missing smmu_g2d clock and update comments
This patch adds missing smmu_g2d clock implementation and updates
comment about Exynos4 clocks from 278-282 range. Those clocks are
available on all Exynos4 SoC series, so the misleading comment has been
removed.

Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:31:06 +02:00
Krzysztof Kozlowski e3c3f19bc6 clk: samsung: exynos3250: Register DMC clk provider
Add clock provider for clocks in DMC domain including EPLL and BPLL. The
DMC clocks are necessary for Exynos3 devfreq driver.

The DMC clock domain uses different address space (0x105C0000) than
standard clock domain (0x10030000 - 0x10050000). The difference is huge
enough to add new DT node for the clock provider, rather than extending
existing address space.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:49 +02:00
Chander Kashyap 22842d244a clk: samsung: exynos5260: fix typo in clock name
The parent name added in parent list as
mout_phyclk_mipi_dphy_4l_m_txbyte_clkhs_p, is different
than the defined parent due to typo.

Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Chander Kashyap <k.chander@samsung.com>
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:45 +02:00
Pankaj Dubey e82ba578cc clk: samsung: exynos3250: fix width field of mout_mmc0/1
As per Exynos3250 user manual mmc0/1 mux selection has 4 bit wide.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:38 +02:00
Pankaj Dubey 59037b92f4 clk: samsung: exynos3250: fix width and shift of div_spi0_isp clock
Update shift and width field of div_spi0_isp clock as per Exynos3250
user manual.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:35 +02:00
Pankaj Dubey 5ce37f2666 clk: samsung: exynos3250: fix mout_cam_blk parent list
As per user manual of Exynos3250 SRC_CAM can select
div_cam_blk_320 if it's value is 0xC, so placing
div_cam_blk_320 at proper index in parent list of mout_cam_blk.

Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
2014-09-22 14:28:28 +02:00
Alexandre Belloni bcc5fd49a0 clk: at91: add a driver for the h32mx clock
Newer SoCs have two different AHB interconnect. The AHB 32 bits Matrix
interconnect (h32mx) has a clock that can be setup at the half of the h64mx
clock (which is mck). The h32mx clock can not exceed 90 MHz.

Signed-off-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
2014-09-22 11:38:59 +02:00
Tomeu Vizoso b9e742c316 clk: tegra: Make clock initialization more robust
Don't abort clock initialization if we cannot match an entry in
tegra_clk_init_table to a valid entry in the clk array.

Also log a corresponding error message.

This was discovered when testing a patch that removed the EMC clock from
tegra124_clks but left a mention in tegra_clk_init_table.

Signed-off-by: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Reviewed-by: Stephen Warren <swarren@nvidia.com>
2014-09-18 14:56:53 +03:00
Mikko Perttunen 4c495c204f clk: tegra124: Add PLL_M_UD and PLL_C_UD clocks
These clocks are used as parents for some EMC timings.

Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
2014-09-18 13:57:12 +03:00
Mike Turquette a52ae5a755 Merge branch 'clk-fixes' into clk-next 2014-09-17 11:47:56 -07:00
Thomas Petazzoni 5f093ee76c clk: mvebu: fix sscg node lookup
Commit 15917b1602 ("clk: mvebu: Fix clk
frequency value if SSCG is enabled") introduced some logic in the
common mvebu clock code to adjust the clock frequency according to the
configuration of the SSCG.

In order to do this, it looks up for a DT node called "sscg" and maps
it before accessing the SSCG configuration register.

However, the lookup is currently done using:

	 sscg_np = of_find_node_by_name(np, "sscg");

where "np" is a pointer to the DT node of the clock for which we are
calculating the adjusted frequency. This means that if the "sscg" node
is *after* the clock node in the Device Tree, it works fine (and
that's the case for Armada 370).

However, if it turns out that the "sscg" node is *before* the clock
node in the Device Tree, it won't work because the sscg node will not
be found.

What we really want here is a search of the entire Device Tree, not
only starting from the clock node, so instead of passing "np" as first
argument of of_find_node_by_name(), we simply need to pass
NULL. Passing a non-NULL argument is typically used in a loop, so that
the search for the next matching node starts right after the node that
was matched.

This makes the "np" argument to the kirkwood_fix_sscg_deviation()
function unnecessary, which leads to further cleanups.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Fixes: 15917b1602 ("clk: mvebu: Fix clk frequency value if SSCG is enabled")
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Link: https://lkml.kernel.org/r/1410880503-2322-1-git-send-email-thomas.petazzoni@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-16 15:39:33 +00:00
Chen-Yu Tsai cfe4c93b58 clk: sunxi: add correct divider table for sun4i-apb0 clock
The sun4i-apb0 clock, as found on all platforms using it, is a
power-of-two-based divider clock, with a special divider of 2
for value 0.

This was causing the clock framework to incorrectly calculate
the clock rate for apb1 and related modules on sun6i and sun8i.
On sun[4/5/7]i, u-boot SPL configures the divider with value 1
for /2 divider, so no suprises there.

This patch adds a proper divider table for it, so the correct
clock rate can be calculated.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Acked-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-09-13 10:07:24 +02:00
Mike Turquette 0469a43bc3 Merge branch 'clk-next-debugfs-lock' into clk-next 2014-09-10 14:42:37 -07:00
Stephen Boyd 6314b6796e clk: Don't hold prepare_lock across debugfs creation
Rob Clark reports a lockdep splat that involves the prepare_lock
chained with the mmap semaphore.

======================================================
[ INFO: possible circular locking dependency detected ]
3.17.0-rc1-00050-g07a489b #802 Tainted: G        W
-------------------------------------------------------
Xorg.bin/5413 is trying to acquire lock:
 (prepare_lock){+.+.+.}, at: [<c0781280>] clk_prepare_lock+0x88/0xfc

but task is already holding lock:
 (qcom_iommu_lock){+.+...}, at: [<c079f664>] qcom_iommu_unmap+0x1c/0x1f0

which lock already depends on the new lock.

the existing dependency chain (in reverse order) is:

-> #4 (qcom_iommu_lock){+.+...}:
       [<c079f860>] qcom_iommu_map+0x28/0x450
       [<c079eb50>] iommu_map+0xc8/0x12c
       [<c056c1fc>] msm_iommu_map+0xb4/0x130
       [<c05697bc>] msm_gem_get_iova_locked+0x9c/0xe8
       [<c0569854>] msm_gem_get_iova+0x4c/0x64
       [<c0562208>] mdp4_kms_init+0x4c4/0x6c0
       [<c056881c>] msm_load+0x2ac/0x34c
       [<c0545724>] drm_dev_register+0xac/0x108
       [<c0547510>] drm_platform_init+0x50/0xf0
       [<c0578a60>] try_to_bring_up_master.part.3+0xc8/0x108
       [<c0578b48>] component_master_add_with_match+0xa8/0x104
       [<c0568294>] msm_pdev_probe+0x64/0x70
       [<c057e704>] platform_drv_probe+0x2c/0x60
       [<c057cff8>] driver_probe_device+0x108/0x234
       [<c057b65c>] bus_for_each_drv+0x64/0x98
       [<c057cec0>] device_attach+0x78/0x8c
       [<c057c590>] bus_probe_device+0x88/0xac
       [<c057c9b8>] deferred_probe_work_func+0x68/0x9c
       [<c0259db4>] process_one_work+0x1a0/0x40c
       [<c025a710>] worker_thread+0x44/0x4d8
       [<c025ec54>] kthread+0xd8/0xec
       [<c020e9a8>] ret_from_fork+0x14/0x2c

-> #3 (&dev->struct_mutex){+.+.+.}:
       [<c0541188>] drm_gem_mmap+0x38/0xd0
       [<c05695b8>] msm_gem_mmap+0xc/0x5c
       [<c02f0b6c>] mmap_region+0x35c/0x6c8
       [<c02f11ec>] do_mmap_pgoff+0x314/0x398
       [<c02de1e0>] vm_mmap_pgoff+0x84/0xb4
       [<c02ef83c>] SyS_mmap_pgoff+0x94/0xbc
       [<c020e8e0>] ret_fast_syscall+0x0/0x48

-> #2 (&mm->mmap_sem){++++++}:
       [<c0321138>] filldir64+0x68/0x180
       [<c0333fe0>] dcache_readdir+0x188/0x22c
       [<c0320ed0>] iterate_dir+0x9c/0x11c
       [<c03213b0>] SyS_getdents64+0x78/0xe8
       [<c020e8e0>] ret_fast_syscall+0x0/0x48

-> #1 (&sb->s_type->i_mutex_key#3){+.+.+.}:
       [<c03fc544>] __create_file+0x58/0x1dc
       [<c03fc70c>] debugfs_create_dir+0x1c/0x24
       [<c0781c7c>] clk_debug_create_subtree+0x20/0x170
       [<c0be2af8>] clk_debug_init+0xec/0x14c
       [<c0208c70>] do_one_initcall+0x8c/0x1c8
       [<c0b9cce4>] kernel_init_freeable+0x13c/0x1dc
       [<c0877bc4>] kernel_init+0x8/0xe8
       [<c020e9a8>] ret_from_fork+0x14/0x2c

-> #0 (prepare_lock){+.+.+.}:
       [<c087c408>] mutex_lock_nested+0x70/0x3e8
       [<c0781280>] clk_prepare_lock+0x88/0xfc
       [<c0782c50>] clk_prepare+0xc/0x24
       [<c079f474>] __enable_clocks.isra.4+0x18/0xa4
       [<c079f614>] __flush_iotlb_va+0xe0/0x114
       [<c079f6f4>] qcom_iommu_unmap+0xac/0x1f0
       [<c079ea3c>] iommu_unmap+0x9c/0xe8
       [<c056c2fc>] msm_iommu_unmap+0x64/0x84
       [<c0569da4>] msm_gem_free_object+0x11c/0x338
       [<c05413ec>] drm_gem_object_handle_unreference_unlocked+0xfc/0x130
       [<c0541604>] drm_gem_object_release_handle+0x50/0x68
       [<c0447a98>] idr_for_each+0xa8/0xdc
       [<c0541c10>] drm_gem_release+0x1c/0x28
       [<c0540b3c>] drm_release+0x370/0x428
       [<c031105c>] __fput+0x98/0x1e8
       [<c025d73c>] task_work_run+0xb0/0xfc
       [<c02477ec>] do_exit+0x2ec/0x948
       [<c0247ec0>] do_group_exit+0x4c/0xb8
       [<c025180c>] get_signal+0x28c/0x6ac
       [<c0211204>] do_signal+0xc4/0x3e4
       [<c02116cc>] do_work_pending+0xb4/0xc4
       [<c020e938>] work_pending+0xc/0x20

other info that might help us debug this:

Chain exists of:
  prepare_lock --> &dev->struct_mutex --> qcom_iommu_lock

 Possible unsafe locking scenario:

       CPU0                    CPU1
       ----                    ----
  lock(qcom_iommu_lock);
                               lock(&dev->struct_mutex);
                               lock(qcom_iommu_lock);
  lock(prepare_lock);

 *** DEADLOCK ***

3 locks held by Xorg.bin/5413:
 #0:  (drm_global_mutex){+.+.+.}, at: [<c0540800>] drm_release+0x34/0x428
 #1:  (&dev->struct_mutex){+.+.+.}, at: [<c05413bc>] drm_gem_object_handle_unreference_unlocked+0xcc/0x130
 #2:  (qcom_iommu_lock){+.+...}, at: [<c079f664>] qcom_iommu_unmap+0x1c/0x1f0

stack backtrace:
CPU: 1 PID: 5413 Comm: Xorg.bin Tainted: G        W      3.17.0-rc1-00050-g07a489b #802
[<c0216290>] (unwind_backtrace) from [<c0211d8c>] (show_stack+0x10/0x14)
[<c0211d8c>] (show_stack) from [<c087a078>] (dump_stack+0x98/0xb8)
[<c087a078>] (dump_stack) from [<c027f024>] (print_circular_bug+0x218/0x340)
[<c027f024>] (print_circular_bug) from [<c0283e08>] (__lock_acquire+0x1d24/0x20b8)
[<c0283e08>] (__lock_acquire) from [<c0284774>] (lock_acquire+0x9c/0xbc)
[<c0284774>] (lock_acquire) from [<c087c408>] (mutex_lock_nested+0x70/0x3e8)
[<c087c408>] (mutex_lock_nested) from [<c0781280>] (clk_prepare_lock+0x88/0xfc)
[<c0781280>] (clk_prepare_lock) from [<c0782c50>] (clk_prepare+0xc/0x24)
[<c0782c50>] (clk_prepare) from [<c079f474>] (__enable_clocks.isra.4+0x18/0xa4)
[<c079f474>] (__enable_clocks.isra.4) from [<c079f614>] (__flush_iotlb_va+0xe0/0x114)
[<c079f614>] (__flush_iotlb_va) from [<c079f6f4>] (qcom_iommu_unmap+0xac/0x1f0)
[<c079f6f4>] (qcom_iommu_unmap) from [<c079ea3c>] (iommu_unmap+0x9c/0xe8)
[<c079ea3c>] (iommu_unmap) from [<c056c2fc>] (msm_iommu_unmap+0x64/0x84)
[<c056c2fc>] (msm_iommu_unmap) from [<c0569da4>] (msm_gem_free_object+0x11c/0x338)
[<c0569da4>] (msm_gem_free_object) from [<c05413ec>] (drm_gem_object_handle_unreference_unlocked+0xfc/0x130)
[<c05413ec>] (drm_gem_object_handle_unreference_unlocked) from [<c0541604>] (drm_gem_object_release_handle+0x50/0x68)
[<c0541604>] (drm_gem_object_release_handle) from [<c0447a98>] (idr_for_each+0xa8/0xdc)
[<c0447a98>] (idr_for_each) from [<c0541c10>] (drm_gem_release+0x1c/0x28)
[<c0541c10>] (drm_gem_release) from [<c0540b3c>] (drm_release+0x370/0x428)
[<c0540b3c>] (drm_release) from [<c031105c>] (__fput+0x98/0x1e8)
[<c031105c>] (__fput) from [<c025d73c>] (task_work_run+0xb0/0xfc)
[<c025d73c>] (task_work_run) from [<c02477ec>] (do_exit+0x2ec/0x948)
[<c02477ec>] (do_exit) from [<c0247ec0>] (do_group_exit+0x4c/0xb8)
[<c0247ec0>] (do_group_exit) from [<c025180c>] (get_signal+0x28c/0x6ac)
[<c025180c>] (get_signal) from [<c0211204>] (do_signal+0xc4/0x3e4)
[<c0211204>] (do_signal) from [<c02116cc>] (do_work_pending+0xb4/0xc4)
[<c02116cc>] (do_work_pending) from [<c020e938>] (work_pending+0xc/0x20)

We can break this chain if we don't hold the prepare_lock while
creating debugfs directories. We only hold the prepare_lock right
now because we're traversing the clock tree recursively and we
don't want the hierarchy to change during the traversal.
Replacing this traversal with a simple linked list walk allows us
to only grab a list lock instead of the prepare_lock, thus
breaking the lock chain.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-10 14:36:20 -07:00
Heiko Stübner 2fed71e57a clk: rockchip: also protect hclk_peri as critical
The dwc2 usb controller also uses agressive clock gating, which in this
case leads to hclk_peri getting disabled and hanging the system.
Therefore move it to the critical clocks until we also control that
part of the system.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-10 10:42:02 -07:00
Heiko Stübner feaefa0ea1 clk: fractional-divider: cast parent_rate to u64 before multiplying
On 32bit architectures, like ARM calculating the fractional rate will
do the multiplication before converting the value to u64 when it gets
assigned to ret, which can produce overflows.

The error in question happened with a parent_rate of 386MHz, m = 3000,
n = 60000, which resulted in a wrong rate value of 15812Hz.

Therefore cast parent_rate to u64 to make sure the multiplication
happens in a 64bit space and produces the correct 192MHz in the example.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-10 09:42:37 -07:00
Javier Martinez Canillas 83ccf16cb9 clk: Add driver for Maxim 77802 PMIC clocks
The MAX77802 PMIC has two 32.768kHz Buffered Clock Outputs with
Low Jitter Mode. This patch adds support for these two clocks.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:55:59 -07:00
Javier Martinez Canillas 1887d69308 clk: max77686: Convert to the generic max clock driver
Clocks drivers for Maxim PMIC are very similar so they can
be converted to use the generic Maxim clock driver.

Also, while being there use module_platform_driver() helper
macro to eliminate more boilerplate code.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:55:49 -07:00
Javier Martinez Canillas 5dbbb00f71 clk: Add generic driver for Maxim PMIC clocks
Maxim Integrated Power Management ICs are very similar with
regard to their clock outputs. Most of the clock drivers for
these chips are duplicating code and are simpler enough that
can be converted to use a generic driver to consolidate code
and avoid duplication.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:55:44 -07:00
Javier Martinez Canillas a8a76f563c clk: max77686: Add DT include for MAX77686 PMIC clock
This patch adds a dt-binding include for Maxim 77686
PMIC clock IDs that can be used by both the max77686
clock driver and Device Tree source files.

Signed-off-by: Javier Martinez Canillas <javier.martinez@collabora.co.uk>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:55:38 -07:00
Uwe Kleine-König 8ce8ebeb57 clk/efm32gg: fix dt init prototype
Since commit 54196ccbe0 (of: consolidate linker section OF match table
declarations) which went into 3.16-rc1 the following compiler warning is
generated:

	In file included from drivers/clk/clk-efm32gg.c:12:0: include/linux/of.h:772:20:
	warning: comparison of distinct pointer types lacks a cast [enabled by default]
		.data = (fn == (fn_type)NULL) ? fn : fn  }
			    ^
	include/linux/of.h:785:3: note: in expansion of macro '_OF_DECLARE'
	   _OF_DECLARE(table, name, compat, fn, of_init_fn_1)
	   ^
	include/linux/clk-provider.h:545:42: note: in expansion of macro 'OF_DECLARE_1'
	 #define CLK_OF_DECLARE(name, compat, fn) OF_DECLARE_1(clk, name, compat, fn)
						  ^
	drivers/clk/clk-efm32gg.c:81:1: note: in expansion of macro 'CLK_OF_DECLARE'
	 CLK_OF_DECLARE(efm32ggcmu, "efm32gg,cmu", efm32gg_cmu_init);
	 ^

Fix it by making efm32gg_cmu_init return void.

Cc: Rob Herring <robh@kernel.org>
Reported-by: Bryan Hundven <bryanhundven@gmail.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 13:52:18 -07:00
Soren Brinkmann 8eaf503480 clk: zynq: Move const initdata into correct code section
Use __initconst instead of __initdata for constant init data.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 12:18:20 -07:00
Soren Brinkmann 034cc6ebae clk: zynq: Remove pointless return at end of void function
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 12:18:20 -07:00
Soren Brinkmann 88cebf5e09 clk: zynq: Remove unnecessary OOM message
As checkpatch suggests:
  WARNING: Possible unnecessary 'out of memory' message,
remove an error message after failing kmalloc() from the PLL driver.

Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-09 12:18:20 -07:00
Gregory CLEMENT ceac26c642 clk: mvebu: armada-375: Fix the description of the SAR in the comment
For dealing with the code we use the SAR1 and not the SAR0. The code
was correct, and now the comments too.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-5-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09 15:15:22 +00:00
Gregory CLEMENT 5e1a63f5f5 clk: mvebu: armada-370: Fix timer drift caused by the SSCG deviation
This commit activates the SSCG deviation correction for the Armada
370. It uses the optional function introduced by the commit "clk:
mvebu: Fix clk frequency value if SSCG is enabled".

Without this fix the deviation measured on a Mirabox was of a few
second each hour, whereas with this fix it was reduced at around
50ppm (around 4s per day).

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-3-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09 15:15:03 +00:00
Gregory CLEMENT 15917b1602 clk: mvebu: Fix clk frequency value if SSCG is enabled
When the SSCG (Spread Spectrum Clock Generator) is enabled, it shifts
the frequency of the clock. The percentage is no more than 1% but when
the clock is used for a timer it leads to a clock drift.

This patch allows to correct the affected clock when the SSCG is
enabled. The check is done in an new optional function related to each
SoC: is_sscg_enabled(). The fix is done with the other new optional
function related to each SoC: fix_sscg_deviation. If one these
functions are not present then no correction is done on the clock
frequency.

Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Tested-by: Leigh Brown <leigh@solinno.co.uk>
Link: https://lkml.kernel.org/r/1409645719-20003-2-git-send-email-gregory.clement@free-electrons.com
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
2014-09-09 15:14:47 +00:00
Tero Kristo 067bb1741c clk: prevent erronous parsing of children during rate change
In some cases, clocks can switch their parent with clk_set_rate, for
example clk_mux can do this in some cases. Current implementation of
clk_change_rate uses un-safe list iteration on the clock children, which
will cause wrong clocks to be parsed in case any of the clock children
change their parents during the change rate operation. Fixed by using
the safe list iterator instead.

The problem was detected due to some divide by zero errors generated
by clock init on dra7-evm board, see discussion under
http://article.gmane.org/gmane.linux.ports.arm.kernel/349180 for details.

Fixes: 71472c0c06 ("clk: add support for clock reparent on set_rate")
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-03 12:09:14 -07:00
Doug Anderson f4ee3c8446 clk: rockchip: Fix the clocks for i2c1 and i2c2
The clocks for i2c1 and i2c2 are flipped.  The clock tree matched the
Technical Reference Manual (TRM) but the TRM was wrong.  Swap them in
the clock tree.  This was determined experimentally (by Addy) and
confirmed by the Rockchip IC team.

Signed-off-by: Doug Anderson <dianders@chromium.org>
Reported-by: Addy Ke <addy.ke@rock-chips.com>
Reviewed-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-03 11:24:50 -07:00
Mike Turquette 7cd4375117 Merge branch 'for-v3.17-rc/ti-clk-driver' of github.com:t-kristo/linux-pm into clk-fixes 2014-09-03 10:07:14 -07:00
Stephen Boyd d8210e28e5 clk: qcom: Fix sdc 144kHz frequency entry
The pre-divider for the sdc clocks only has 2 bits in it, so we
can't possibly divide by anything larger than 4 here.
Furthermore, we program the value of ~(n - m) and the n value is
larger than 8 bits (max of 256). Replace this entry with 200kHz
which is close enough to 144kHz to be usable.

Cc: Kumar Gala <galak@codeaurora.org>
Cc: Andy Gross <agross@codeaurora.org>
Fixes: 24d8fba44a "clk: qcom: Add support for IPQ8064's global clock controller (GCC)"
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 16:52:28 -07:00
Boris BREZILLON 16eeaec779 clk: at91: fix div by zero in USB clock driver
Test rate value before calculating the div value to avoid div by zero.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:37:26 -07:00
Boris BREZILLON 13a6073d4c clk: at91: rework rm9200 USB clock to propagate set_rate to the parent clk
The RM9200 USB clock is actually connected to a single parent (the PLLB)
on which we can apply a specific divider.
The USB clock divider does not allow for fine grained control on the USB
clock frequency, hence propagating the set_rate request to the parent is
the only choice we have to properly configure the USB clock rate.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:37:22 -07:00
Boris BREZILLON 87e2ed338f clk: at91: fix recalc_rate implementation of PLL driver
Use the cached values to calculate PLL rate instead of the register values.
This is required to prevent erroneous PLL rate return when the PLL rate
has been configured but the PLL is not prepared yet.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:37:17 -07:00
Boris BREZILLON 3ef9dd2bab clk: at91: rework PLL rate calculation
The AT91 PLL rate configuration is done by configuring a multiplier/divider
pair.
The previous calculation was over-complicated (and apparently buggy).
Simplify the implementation and add some comments to explain what is done
here.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:37:11 -07:00
Boris BREZILLON 078a3eb519 clk: at91: fix PLL_MAX_COUNT macro definition
Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Reported-by: Gaël PORTAY <gael.portay@gmail.com>
Tested-by: Gaël PORTAY <gael.portay@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:36:56 -07:00
Heiko Stübner fe94f974e9 clk: rockchip: protect critical clocks from getting disabled
The clock-tree contains clocks that should never get disabled automatically.
One example are the base ACLKs, the base supplies for all peripherals.

Therefore add a structure similar to the sunxi clock-tree to protect these
special clocks from being disabled.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Doug Anderson <dianders@chromium.org>
Tested-by: Kever Yang <kever.yang@rock-chips.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:18 -07:00
Heiko Stübner 1a4b181995 clk: rockchip: make rockchip_clk_register_branch static
It is only used locally in clk/rockchip/clk.c and thus can be static.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:17 -07:00
Heiko Stübner b2155a71a7 clk: rockchip: implement the fraction divider branch type
Rockchip SoCs may provide fraction dividers for some clocks, mostly for
i2s and uarts. In contrast to the other registers, these do not use
the hiword-mask paradigm, but instead split the register into the upper
16 bit for the nominator and the lower 16 bit for the denominator.

The common clock framework got a generic fractional divider clock type
recently that can accomodate this setting easily. All currently known
fraction dividers have a separate gate too, therefore implement the
divider as composite using the ops-struct from fractional_divider clock
and add the gate if necessary.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:17 -07:00
Kuninori Morimoto 4abe240878 clk: shmobile: add missing 0x0100 for SDCKCR
10cdfe9f32
(clk: shmobile: Add R-Car Gen2 clocks support)
added R-Car Gen2 clock support via DT for v3.14.

But, cpg_sd01_div_table is missing
"0x0100: x 1/8" division ratio.
This patch fixes hidden bug.
It is based on R-Car H2 v0.7, R-Car M2 v0.9.

Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Acked-by: Simon Horman <horms+renesas@verge.net.au>
Reported-by: Yusuke Goda <yusuke.goda.sx@renesas.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:03:16 -07:00
Mike Turquette 105299381d cpufreq: kirkwood: use the powersave multiplexer
The powersave clock acts like a multiplexer for the cpu, selecting
either the clock signal derived from the cpu pll or from the ddr clock.
This patch changes powersave from a gate clock to a mux clock to better
reflect this behavior.

This is a cleaner approach whereby the frequency of the cpu always
matches the rate of powersave_clk. The cpufreq driver for the kirkwood
platform no longer must parse this behavior out of various calls to
clk_enable and clk_disable, but can instead simply select the parent cpu
it wants when changing rate. Likewise when requesting the cpu rate we
need only query powersave_clk's rate through the usual call to
clk_get_rate.

The new clock data and corresponding changes to the cpufreq driver are
combined into this single commit to avoid a git bisect issue where this
cpufreq driver fails to work properly between the commit that updates
the kirkwood clock driver and the commit that changes how the cpufreq
driver uses that clock.

Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 15:02:54 -07:00
Boris BREZILLON e8531ac8b2 clk: at91: fix num_parents test in at91sam9260 slow clk implementation
The slow clk block provided by at91sam9260 and derived SoCs should always
have 2 parents.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-02 14:44:41 -07:00
Mike Turquette e8e8a9b0d8 clk: mvebu: powersave clock is a multiplexer
Kirkwood is unique among the mvebu SoCs for having a clock multiplexer
that feeds into the cpu. This multiplexer can select either the cpu pll
or the ddr clock as its input signal, allowing for a choice between
performance and power savings.

This patch introduces the code needed to register the clock multiplexer
on Kirkwood SoCs but does not include the clock data to actually
register the clock. That will be done in a follow-up patch which is
necessary to prevent breaking git bisect.

Cc: Tomeu Vizoso <tomeu.vizoso@collabora.com>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-01 17:43:52 -07:00
Mike Turquette 87e392164a clk: mvebu: share locks between gate clocks
Refactor mvebu_clk_gating_setup() to use a common spinlock instead of a
unique lock for every instance of a struct clk_gating_ctrl object. This
will be used later for a separate mux clock type that shares a register
with gate clock types and needs to use the same lock to protect access
to the register.

Cc: Andrew Lunn <andrew@lunn.ch>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-09-01 17:43:52 -07:00
Hisashi Nakamura 8de078f189 clk: shmobile: Add r8a7794 support
Signed-off-by: Hisashi Nakamura <hisashi.nakamura.ak@renesas.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2014-08-27 08:40:54 +09:00
Nicolas Ferre e657ce689a AT91 reset, poweroff and ram drivers
This tag holds the various new drivers introduced to move code that used to be
 in mach-at91 over to the proper frameworks.
 
 These files are the reboot and poweroff code for all AT91 SoCs but the RM9200,
 and the ram controller driver is not doing much at the time, except for grabing
 the RAM clock in order to leave it always enabled.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1
 
 iQIcBAABAgAGBQJTx4LlAAoJEBx+YmzsjxAggooP/0xIMF568hWNLWMOBLNyeXLP
 SJUCBZw1kLqhw8K3nPV5GAmfGxgCCZ3uvUfMdIgJzSN+NtcuvQR2+ui2Bj1nzRRQ
 y6ZAmoHEJHveNd3SoLpuE5s4KFwTBFblcBXHVSwIZzMcCioBxFWtcPupkIVoqt/z
 s/gN5w9BsSCvqjtmYSTp8XTza9y7hx9Pmdpc1uzkP/WJbXtxyQX50NlpILQ1r7WW
 WNOMRXOpv/JH+EHFtS7vMMvn+fQ94RVI209+Z2wez13H87C8MZF4N972vRHkmBuG
 Uv2ZowFRo8T0YjJZfmyfWyg3C9fMOcQeOURAGO/FIavf0WJ+7/hmdZ9jymTpaA3b
 WwZ+qgajMMdOk2ojW36vfueOqeuXx7bxGKWocXO/Rk00ZpN8Y2qFqmsJL5WNYVoN
 SDod+nzYHA4ShyZFDiXoAf3R/+gjb9RvCJ0ZvjkdHUeU8GYHhXjDLPp1Ng7oDBut
 szDE8FfWGpb5UsjFSdKfSsU2Xp3lqZ6fv89qiGYGwz7OqKRz2E0d8zm/EHoD87RR
 jx9e4pWvk++Vouk/zCRZVb+HrGtN9FbZKfRq6xx1pAO+V2NCmq8ttcPH2BuN1K3T
 quFRb6YBTfNfgVKPjbPsQ4QOuCR4juIZSubRhQEi7/Uie5aR/9q6Lz/pYbzitYjJ
 qHR5nj7sL/WwJlfgFgbi
 =YBPz
 -----END PGP SIGNATURE-----

Merge tag 'at91-drivers-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux

Pull AT91 reset, poweroff and ram drivers from Maxime Ripard:
 "This tag holds the various new drivers introduced to move code that used to be
  in mach-at91 over to the proper frameworks.

  These files are the reboot and poweroff code for all AT91 SoCs but the RM9200,
  and the ram controller driver is not doing much at the time, except for grabing
  the RAM clock in order to leave it always enabled."

Conflicts:
	arch/arm/mach-at91/Kconfig
2014-08-25 15:35:26 +02:00
Nishanth Menon 20411dad75 clk: ti: dra7-atl: Provide error check for incoming parameters in set_rate
Check for valid parameters in check rate. Else, we end up getting
errors.

This occurs as part of the inital clock tree update of child clock
nodes where new_rate could be 0 for non functional clocks.

Fixes: 9ac33b0ce8 (" CLK: TI: Driver for DRA7 ATL (Audio Tracking Logic)")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-08-21 18:04:16 +03:00
Nishanth Menon 2f10325176 clk: ti: divider: Provide error check for incoming parameters in set_rate
Check for valid parameters in check rate. Else, we end up getting errors
like:
[    0.000000] Division by zero in kernel.
[    0.000000] CPU: 0 PID: 0 Comm: swapper/0 Not tainted 3.17.0-rc1 #1
[    0.000000] [<c0015160>] (unwind_backtrace) from [<c0011978>] (show_stack+0x10/0x14)
[    0.000000] [<c0011978>] (show_stack) from [<c055f5f4>] (dump_stack+0x78/0x94)
[    0.000000] [<c055f5f4>] (dump_stack) from [<c02e17cc>] (Ldiv0+0x8/0x10)
[    0.000000] [<c02e17cc>] (Ldiv0) from [<c047d228>] (ti_clk_divider_set_rate+0x14/0x14c)
[    0.000000] [<c047d228>] (ti_clk_divider_set_rate) from [<c047a938>] (clk_change_rate+0x138/0x180)
[    0.000000] [<c047a938>] (clk_change_rate) from [<c047a908>] (clk_change_rate+0x108/0x180)

This occurs as part of the inital clock tree update of child clock nodes
where new_rate could be 0 for non functional clocks.

Fixes: b4761198bf ("CLK: ti: add support for ti divider-clock")
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tero Kristo <t-kristo@ti.com>
2014-08-21 18:04:16 +03:00
Linus Torvalds b3345d7c57 ARM: SoC platform changes for 3.17
This is the bulk of new SoC enablement and other platform changes for 3.17:
 
 * Samsung S5PV210 has been converted to DT and multiplatform
 * Clock drivers and bindings for some of the lower-end i.MX 1/2 platforms
 * Kirkwood, one of the popular Marvell platforms, is folded into the
   mvebu platform code, removing mach-kirkwood.
 * Hwmod data for TI AM43xx and DRA7 platforms.
 * More additions of Renesas shmobile platform support
 * Removal of plat-samsung contents that can be removed with S5PV210 being
   multiplatform/DT-enabled and the other two old platforms being removed.
 
 New platforms (most with only basic support right now):
 
 * Hisilicon X5HD2 settop box chipset is introduced
 * Mediatek MT6589 (mobile chipset) is introduced
 * Broadcom BCM7xxx settop box chipset is introduced
 
 + as usual a lot other pieces all over the platform code.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5Dp+AAoJEIwa5zzehBx3w1sP/0vjT/LQOmC8Lv8RW2Ley2ua
 hNu3HcNPnT/N40JEdU9YNv3q0fdxGgcfKj011CNN+49zPSUf1xduk2wfCAk9yV50
 8Sbt1PfDGm1YyUugGN420CzI431pPoM1OGXHZHkAmg+2J286RtUi3NckB//QDbCY
 QhEjhpYc9SXhAOCGwmB4ab7thOljOFSPzKTLMTu3+PNI5zRPRgkDkt6w9XlsAYmB
 nuR271BnzsROkMzAjycwaJ3kdim7wqrMRfk8g96o0jHSF5qf4zsT5uWYYAjTxdUQ
 8Ajz6zjeHe4+95TwTDcq+lCX6rDLZgwkvCAc6hFbeg0uR7Dyek0h6XMEYtwdjaiU
 KNPwOENrYdENNDAGRpkFp1x4h/rY9Plfru0bBo5o6t7aPBvmNeCDzRtlTtLiUNDV
 dG8sfDMtrS/wFHVjylDSQ60Mb+wuW0XneC8D7chY/iRhIllUYi6YXXvt+/tH5C20
 oYDOWqqcDFSb0sJhE5pn4KBV82ZaHx9jMBWGLl+erg2sDX/SK8SxOkLqKYZKtKB5
 0leOGE3Y+C70xt3G9HftLz2sAvvt+C8UPsApPT+dHNE401TWJOYx6LphPkQKjeeK
 P1iwKi+It3l+FaBypgJy/LeMQRy7EyvDBK2I5WoVL/R2qq14EmP1ui3Tthjj0bhq
 tBBof6P9c8OnRVj1Lz3R
 =5TJ6
 -----END PGP SIGNATURE-----

Merge tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC platform changes from Olof Johansson:
 "This is the bulk of new SoC enablement and other platform changes for
  3.17:

   - Samsung S5PV210 has been converted to DT and multiplatform
   - Clock drivers and bindings for some of the lower-end i.MX 1/2
     platforms
   - Kirkwood, one of the popular Marvell platforms, is folded into the
     mvebu platform code, removing mach-kirkwood
   - Hwmod data for TI AM43xx and DRA7 platforms
   - More additions of Renesas shmobile platform support
   - Removal of plat-samsung contents that can be removed with S5PV210
     being multiplatform/DT-enabled and the other two old platforms
     being removed

  New platforms (most with only basic support right now):

   - Hisilicon X5HD2 settop box chipset is introduced
   - Mediatek MT6589 (mobile chipset) is introduced
   - Broadcom BCM7xxx settop box chipset is introduced

  + as usual a lot other pieces all over the platform code"

* tag 'soc-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (240 commits)
  ARM: hisi: remove smp from machine descriptor
  power: reset: move hisilicon reboot code
  ARM: dts: Add hix5hd2-dkb dts file.
  ARM: debug: Rename Hi3716 to HIX5HD2
  ARM: hisi: enable hix5hd2 SoC
  ARM: hisi: add ARCH_HISI
  MAINTAINERS: add entry for Broadcom ARM STB architecture
  ARM: brcmstb: select GISB arbiter and interrupt drivers
  ARM: brcmstb: add infrastructure for ARM-based Broadcom STB SoCs
  ARM: configs: enable SMP in bcm_defconfig
  ARM: add SMP support for Broadcom mobile SoCs
  Documentation: arm: misc updates to Marvell EBU SoC status
  Documentation: arm: add URLs to public datasheets for the Marvell Armada XP SoC
  ARM: mvebu: fix build without platforms selected
  ARM: mvebu: add cpuidle support for Armada 38x
  ARM: mvebu: add cpuidle support for Armada 370
  cpuidle: mvebu: add Armada 38x support
  cpuidle: mvebu: add Armada 370 support
  cpuidle: mvebu: rename the driver from armada-370-xp to mvebu-v7
  ARM: mvebu: export the SCU address
  ...
2014-08-08 11:14:29 -07:00
Linus Torvalds 44c916d58b ARM: SoC cleanups for 3.17
This merge window brings a good size of cleanups on various
 platforms. Among the bigger ones:
 
 * Removal of Samsung s5pc100 and s5p64xx platforms. Both of these have
   lacked active support for quite a while, and after asking around nobody
   showed interest in keeping them around. If needed, they could be
   resurrected in the future but it's more likely that we would prefer
   reintroduction of them as DT and multiplatform-enabled platforms
   instead.
 * OMAP4 controller code register define diet. They defined a lot of registers
   that were never actually used, etc.
 * Move of some of the Tegra platform code (PMC, APBIO, fuse, powergate)
   to drivers/soc so it can be shared with 64-bit code. This also converts them
   over to traditional driver models where possible.
 * Removal of legacy gpio-samsung driver, since the last users have been
   removed (moved to pinctrl)
 
 Plus a bunch of smaller changes for various platforms that sort of
 dissapear in the diffstat for the above. clps711x cleanups, shmobile
 header file refactoring/moves for multiplatform friendliness, some misc
 cleanups, etc.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT5DYPAAoJEIwa5zzehBx37egQAIiatNiLLqZnfo3rwGADRz/a
 POfPovktj68aPcobyzoyhFtToMqGvi9PpysyFTIQD2HJFG+5BtiIAuqtg0875zDe
 EpBWgsfugrm0YktJWAtUerj60oAmNPbKfaEm1cOOWuM2lb2mV+QkRrwSTAgsqkT7
 927BzMXKKBRPOVLL0RYhoF8EXa0Eg8kCqAHP8fJrzVYkRp+UrZJDnGiUP1XmWJN+
 VXQMu5SEjcPMtqT7+tfX455RfREHJfBcJ1ZN/dPF8HMWDwClQG0lyc6hifh1MxwO
 8DjIZNkfZeKqgDqVyC17re7pc7p8md5HL8WXbrKpK0A9vQ5bRexbPHxcwJ1T/C2Y
 465H+st5XXbuzV1gbMwjK1/ycsH0tCyffckk8Yl/2e1Fs7GgPNbAELtTdl+5vV1Y
 xmDXkyo/9WlRM3LQ23IGKwW7VzN86EfWVuShssfro0fO7xDdb4OOYLdQI+4bCG+h
 ytQYun1vU32OEyNik5RVNQuZaMrv2c93a3bID4owwuPHPmYOPVUQaqnRX/0E51eA
 aHZYbk2GlUOV3Kq5aSS4iyLg1Yj+I9/NeH9U+A4nc+PQ5FlgGToaVSCuYuw4DqbP
 AAG+sqQHbkBMvDPobQz/yd1qZbAb4eLhGy11XK1t5S65rApWI55GwNXnvbyxqt8x
 wpmxJTASGxcfuZZgKXm7
 =gbcE
 -----END PGP SIGNATURE-----

Merge tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC cleanups from Olof Johansson:
 "This merge window brings a good size of cleanups on various platforms.
  Among the bigger ones:

   - Removal of Samsung s5pc100 and s5p64xx platforms.  Both of these
     have lacked active support for quite a while, and after asking
     around nobody showed interest in keeping them around.  If needed,
     they could be resurrected in the future but it's more likely that
     we would prefer reintroduction of them as DT and
     multiplatform-enabled platforms instead.

   - OMAP4 controller code register define diet.  They defined a lot of
     registers that were never actually used, etc.

   - Move of some of the Tegra platform code (PMC, APBIO, fuse,
     powergate) to drivers/soc so it can be shared with 64-bit code.
     This also converts them over to traditional driver models where
     possible.

   - Removal of legacy gpio-samsung driver, since the last users have
     been removed (moved to pinctrl)

  Plus a bunch of smaller changes for various platforms that sort of
  dissapear in the diffstat for the above.  clps711x cleanups, shmobile
  header file refactoring/moves for multiplatform friendliness, some
  misc cleanups, etc"

* tag 'cleanup-for-3.17' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (117 commits)
  drivers: CCI: Correct use of ! and &
  video: clcd-versatile: Depend on ARM
  video: fix up versatile CLCD helper move
  MAINTAINERS: Add sdhci-st file to ARCH/STI architecture
  ARM: EXYNOS: Fix build breakge with PM_SLEEP=n
  MAINTAINERS: Remove Kirkwood
  ARM: tegra: Convert PMC to a driver
  soc/tegra: fuse: Set up in early initcall
  ARM: tegra: Always lock the CPU reset vector
  ARM: tegra: Setup CPU hotplug in a pure initcall
  soc/tegra: Implement runtime check for Tegra SoCs
  soc/tegra: fuse: fix dummy functions
  soc/tegra: fuse: move APB DMA into Tegra20 fuse driver
  soc/tegra: Add efuse and apbmisc bindings
  soc/tegra: Add efuse driver for Tegra
  ARM: tegra: move fuse exports to soc/tegra/fuse.h
  ARM: tegra: export apb dma readl/writel
  ARM: tegra: Use a function to get the chip ID
  ARM: tegra: Sort includes alphabetically
  ARM: tegra: Move includes to include/soc/tegra
  ...
2014-08-08 11:00:26 -07:00
Linus Torvalds e4ca4308c0 The clock framework changes for 3.17 are mostly additions of new clock
drivers and fixes/enhancements to existing clock drivers. There are also
 some non-critical fixes and improvements to the framework core.
 
 Changes to the clock framework core include:
 * improvements to printks on errors
 * flattening the previously hierarchal structure of per-clock entries
   in debugfs
 * allow per-clock debugfs entries that are specific to a particular
   clock driver
 * configure initial clock parent and/or initial clock rate from Device
   Tree
 * several feature enhancements to the composite clock type
 * misc fixes
 
 New clock drivers added include:
 * TI Palmas PMIC
 * Allwinner A23 SoC
 * Qualcomm APQ8084 and IPQ8064 SoCs
 * Rockchip rk3188, rk3066 and rk3288 SoCs
 * STMicroelectronics STiH407 SoC
 * Cirrus Logic CLPS711X SoC
 
 Many fixes, feature enhancements and further clock tree support for
 existing clock drivers also were merged, such as Samsung's "ARMCLK down"
 power saving feature for their Exynos4 & Exynos5 SoCs.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJT38lmAAoJEDqPOy9afJhJh9YQAKROq+lrKaf+YAk22E0GCF30
 Q+KZ9EcePdxWvcDPKsMIf/wAIYdtGDoI6wgyw1tcSWeLKwwyHMfVdOCExWig2gwl
 /4LU2tACKe+Xa0HJnsbNwQGj2n4qMGOUsDeRRmK4rcbuHZhTP15IscmFCbL+sUia
 z3uaYf7ty3a1tSXBl3NY4EpYAXGiE+MMVBoU08ATYOOjvGcxNNfu50JSltGXarqv
 BFBjpv0oikN3RvbVyuUUvEF8m6AeNYhbqxI0IuNmoE+mAkgB2n221CK4Qv6a3oDb
 QJebzRdeprcak8HrK76Ik6Dd9itcs03u6G1qwLc30JH5wUHYcgqA5bvqDIx+2W0J
 Z7NPi3tFTry1aeXnZPk7DbWruzXLQkXkgRM4xHXsmezRnO7zDvuoDgUT0pIrS9+v
 +BRIyfPiBL9Lp1J17R0I1K76O7YnvyQhX+0CdZx0SOJNGPl+SIwTI4q+gQoDIZqP
 0ubpuaH4v6gZiEol2HXKYN9ASWyRtX7PfiexQgmts1aewlPopWfuc7LdxhHQIv3B
 3O/7jbhdhXsf7VaTvx7xkFEMxjY7IwEF4pN0F+ulwWj/rLK3vLCnTwxgv8IrNHit
 Dkzt4kVzLW/GSWa3irTnISvsg+bHkRc7aPuW/i0km7RYUuL2dcaJLEBPYuka/AdH
 1xIMaGNpkA3HrS+8CQYf
 =48y9
 -----END PGP SIGNATURE-----

Merge tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux

Pull clock framework updates from Mike Turquette:
 "The clock framework changes for 3.17 are mostly additions of new clock
  drivers and fixes/enhancements to existing clock drivers.  There are
  also some non-critical fixes and improvements to the framework core.

  Changes to the clock framework core include:
   - improvements to printks on errors
   - flattening the previously hierarchal structure of per-clock entries
     in debugfs
   - allow per-clock debugfs entries that are specific to a particular
     clock driver
   - configure initial clock parent and/or initial clock rate from
     Device Tree
   - several feature enhancements to the composite clock type
   - misc fixes

  New clock drivers added include:
   - TI Palmas PMIC
   - Allwinner A23 SoC
   - Qualcomm APQ8084 and IPQ8064 SoCs
   - Rockchip rk3188, rk3066 and rk3288 SoCs
   - STMicroelectronics STiH407 SoC
   - Cirrus Logic CLPS711X SoC

  Many fixes, feature enhancements and further clock tree support for
  existing clock drivers also were merged, such as Samsung's "ARMCLK
  down" power saving feature for their Exynos4 & Exynos5 SoCs"

* tag 'clk-for-linus-3.17' of git://git.linaro.org/people/mike.turquette/linux: (86 commits)
  clk: Add missing of_clk_set_defaults export
  clk: checking wrong variable in __set_clk_parents()
  clk: Propagate any error return from debug_init()
  clk: clps711x: Add DT bindings documentation
  clk: Add CLPS711X clk driver
  clk: st: Use round to closest divider flag
  clk: st: Update frequency tables for fs660c32 and fs432c65
  clk: st: STiH407: Support for clockgenA9
  clk: st: STiH407: Support for clockgenD0/D2/D3
  clk: st: STiH407: Support for clockgenC0
  clk: st: Add quadfs reset handling
  clk: st: Add polarity bit indication
  clk: st: STiH407: Support for clockgenA0
  clk: st: STiH407: Support for A9 MUX Clocks
  clk: st: STiH407: Support for Flexgen Clocks
  clk: st: Adds Flexgen clock binding
  clk: st: Remove uncessary (void *) cast
  clk: st: use static const for clkgen_pll_data tables
  clk: st: use static const for stm_fs tables
  clk: st: Update ST clock binding documentation
  ...
2014-08-04 11:44:20 -07:00
Sylwester Nawrocki b11a6face1 clk: Add missing of_clk_set_defaults export
The of_clk_set_defaults() function is used in subsystems which can
be built as module. Add the missing symbol export entry so there
is no build errors like:
"ERROR: "of_clk_set_defaults" [drivers/i2c/i2c-core.ko] undefined!".

Fixes commit: 86be408bfb
"clk: Support for clock parents and rates assigned from device tree"

Reported-by: kbuild test robot <fengguang.wu@intel.com>
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Acked-by: Wolfram Sang <wsa@the-dreams.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-04 09:48:39 -07:00
Dan Carpenter 6ba19bf066 clk: checking wrong variable in __set_clk_parents()
There is a cut and paste bug so we check "pclk" instead of "clk".

Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
2014-08-01 10:47:26 -07:00