The keyboard on Venice2 is attached to the ChromeOS embedded controller.
Add the corresponding device tree nodes and use the MATRIX_KEY define to
encode keycodes.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
From Uwe Kleine-König:
* efm32/soc: (1003 commits)
ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs
+Linux 3.13-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Enable USB2 on Beaver, exposed via the mini-PCIe connector.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify Tegra30 default USB2 phy_type to UTMI; this matches
power-on-reset defaults and is expected to be the common case.
The current implementation is likely an incorrect
carry-over from Tegra20, where USB2 does default to ULPI.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We want to follow the name style of DTS that is SoC-board.dts.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 2120 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 104 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 102 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add HDMI node to the Dalmore device tree and hook up the VDD and PLL
regulators as well as the I2C adapter used for DDC and the GPIO used
for hotplug detection.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore has a 10.1" WUXGA panel connected to one of the DSI outputs of
the Tegra114.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the gr3d device tree node. The gr3d block on Tegra114 is backwards-
compatible with the one on Tegra20.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the device tree for the gr2d hardware found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add device tree nodes for the DSI controllers found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add host1x, DC (display controller) and HDMI devices to Tegra114
device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a device node for the MIPI calibration block on Tegra114. There is
no need to disable it by default because it only enables the clock while
performing calibration and therefore shouldn't be consuming any power
when unused.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, add unit address to new DT node name]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The d6 and d7 is connected to PWM, we can use PWM to control it,
so switch to PWM leds.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add backlight and panel nodes for the Harmony TFT LCD panel.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add ams AS3722 entry for gpio/pincontrol and regulators
to venice2 DT.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Compare the initial population of default pinmux configuration of Venice2
with the chrome branch and add/fix the missing configurations.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
- kirkwood
- use symbolic names for gpios and key inputs
- mvebu
- add the pxa nand controller to the ReadyNAS and A370-RD boards
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Merge tag 'mvebu-dt-3.14-3' of git://git.infradead.org/linux-mvebu into next/dt
From Jason Cooper:
mvebu DT changes for v3.14 (incr. #3)
- kirkwood
- use symbolic names for gpios and key inputs
- mvebu
- add the pxa nand controller to the ReadyNAS and A370-RD boards
* tag 'mvebu-dt-3.14-3' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Enable NAND controller in A370 Reference Design board
ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file
ARM: DT: Kirkwood: Use symbolic names from gpio.h
ARM: DT: Kirkwood: Use symbolic names from input.h
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Drop 0x prefixes
- Get rid of explicit GPIO management
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Merge tag 'nomadik-dt-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Some Nomadik Device Tree updates for the v3.14 cycle:
- Drop 0x prefixes
- Get rid of explicit GPIO management
* tag 'nomadik-dt-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: get rid of explicit ethernet GPIO management
ARM: nomadik: Remove '0x's from nomadik stn8815 DTS file
Now that the DTS file r8a7790-lager.dts can be used with board-lager.c
and board-lager-reference.c, proceed with removing
r8a7790-lager-reference.dts.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The external crystal frequency is 20MHz on the Koelsch board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The external crystal frequency is 20MHz on the Lager board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Copy the device nodes from Koelsch reference into the Koeslch device
tree file. This will allow us to use a single DTS file regarless of
kernel configuration. In case of legacy C board code the device nodes
may or may not be used, but in the multiplatform case all the DT device
nodes are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Copy the device nodes from Lager reference into the Lager device tree
file. This will allow us to use a single DTS file regarless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7791 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7790 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The board had 4 buttons connected to GPIOs, add a corresponding
gpio-keys device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Armadillo 800 EVA panel module has a backlight enable signal
connected to GPIO 61. Report this in the backlight DT node.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 22ceeee16e ("pwm-backlight: Add
power supply support") added a mandatory power supply for the PWM
backlight. Add a fixed 5V regulator and reference it for the backlight
power supply.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Koelsch support boot with the legacy DTS for
Koelsch as well as the Koelsch reference DTS.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Lager support boot with the legacy DTS for Lager
as well as the Lager reference DTS.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that r8a7790 has CCF support remove the legacy Lager reference
Kconfig bits CONFIG_MACH_LAGER_REFERENCE for the non-multiplatform
case.
Starting from this commit Lager board support is always enabled via
CONFIG_MACH_LAGER, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-lager.c and board-lager-reference.c
The file board-lager-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable multiplaform ARM architecture support for the Lager reference
board. Common clock framework initialization will be handled by the
rcar_gen2_init_timer() call, we just need to remove the legacy clock
code initialization.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7790.dtsi file has four sdhi nodes which the first two have the wrong
resource size for their register block. This causes the sh_modbile_sdhi driver
to fail to communicate with card at-all.
Change sdhi{0,1} node size from 0x100 to 0x200 to correct these nodes
as per Kuninori Morimoto's response to the original patch where all four
nodes where changed. sdhi{2,3} are the correct size.
This bug has been present since sdhi resources were added to the r8a7790 by
8c9b1aa418 ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT
templates") in v3.11-rc2.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: William Towle <william.towle@codethink.co.uk>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This adds support for CompuLab SBC-T3530, also known as cm-t3730:
http://compulab.co.il/products/sbcs/sbc-t3530/
It seems that with the sbc-3xxx mainboard is also used on
SBC-T3517 and SBC-T3730 with just a different CPU module:
http://compulab.co.il/products/sbcs/sbc-t3517/http://compulab.co.il/products/sbcs/sbc-t3730/
So let's add a common omap3-sb-t35.dtsi and then separate SoC
specific omap3-sbc-t3730.dts, omap3-sbc-t3530.dts and
omap3-sbc-t3517.dts.
I've tested this with SBC-T3730 as that's the only one I have.
At least serial, both Ethernet controllers, MMC, and wl12xx WLAN
work.
Note that WLAN seems to be different for SBC-T3530. And SBC-T3517
may need some changes for the EMAC Ethernet if that's used
instead of the smsc911x.
Cc: devicetree@vger.kernel.org
Cc: Mike Rapoport <mike@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable Hisilicon Hi4511 development platform with device tree support.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This pin needs to be configured in pull-down, non-tristate mode in order
for the backlight to work correctly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Other boards use PULL_NONE for their debug UART pins, and without this
change, the board doesn't accept any serial input.
Don't set the I2S port pins to tristate mode, or no audio signal will
be sent out.
Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Set the parent of the regulators LDO2 to LDO9 according to the
schematic. Set the base voltage to 3.3V, there is only 3.3V on the
module itself.
Set the Core and CPU voltage to the specified voltages of 1.2V and
1.0V respectivly.
LDO6 should deliver 2.85V. The attached peripherals were not in
use so far.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The PWM controller on Tegra124 is the same as the one on earlier SoC
generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, added reset properties]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 contains a similar set of audio devices to previous Tegra chips.
Specifically, there is an AHUB device which contains DMA FIFOs and audio
routing, and which hosts various audio-related components such as I2S
controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 has 6 I2C controllers. The first 5 have identical configuration
to Tegra114, but the sixth obviously has different interrupt/... IDs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT.
power-gpios property suggested by Thierry Reding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Instantiate the APB DMA controller in the Tegra124 DT, and add all
DMA-related properties to other DT nodes that rely on (reference) the
DMA controller's node.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
The DT bindings now require module resets to be specified. The earlier
patches which added these nodes were originally written before that
requirement.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
This patch adds clock properties for devices in the DT for basic support
of Tegra124 SoC.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
[swarren, added missing unit address to "clock" node]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
For Tegra DT files, I've been attempting to keep the nodes sorted in
the order:
1) Nodes with reg, in order of reg.
2) Nodes without reg, alphabetically.
This patch fixes a few escapees that I missed:-(
The diffs look larger than they really are, because sometimes when one
node was moved up or down, diff chose to represent this as many other
nodes being moved the other way!
Signed-off-by: Stephen Warren <swarren@nvidia.com>
DT node names should include a unit address iff the node has a reg
property. For Tegra DTs at least, we were previously applying a different
rule, namely that node names only needed to include a unit address if it
was required to make the node name unique. Consequently, many unit
addresses are missing. Add them.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The A13-OLinuXino-MICRO is a small dev-board with the Allwinner A13 SoC:
https://www.olimex.com/Products/OLinuXino/A13/A13-OLinuXino-MICRO/
Features:
A13 Cortex A8 processor at 1GHz, 3D Mali400 GPU
256 MB RAM (128Mbit x 16)
5VDC input power supply with own ICs, noise immune design
1 USB host
1 USB OTG which can power the board
SD-card connector for booting the Linux image
VGA video output
LCD signals available on connector so you still can use LCD if you disable VGA/HDMI
Audio output
Microphone input pads (no connector)
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Fix the name as per DT node naming convention.
- rename the node to syscon which is a more generic name.
- append the register value to the node name.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The minimum recommended ARM voltage for Exynos5250 at 200MHz
on Arndale board is 0.9125V. Update accordingly.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5420 is octa-core SoC from Samsung.
Hence populate all the CPU node entries.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5420 is octa-core SoC from Samsung. Hence extend exynos-mct clocksource
driver to support 8 local interrupts.
Also extend dts entries for 8 interrupts.
Signed-off-by: Chander Kashyap <chander.kashyap@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Adds G-Scaler device nodes to the DT device list
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds the mmc device tree node entries for exynos5420 SOC.
Exynos5420 has a different version of DWMMC controller,so a new
compatible string is used to distinguish it from the prior SOC's.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch rename's the device tree mmc node's from "dwmmc" to "mmc".
According to ePAPR chapter 2.2.2 generic node name recommendation,
it has been opted change from dwmmc to mmc.Also this patch remove the
instance index from the node name.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
As fifo-depth property in dw_mmc device tree node is SOC
specific, move this property to exynos5250 SOC specific
file.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
[kgene.kim@samsung.com: squashed fifo-depth patch for cros5250-common]
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
As per the timing information for supported panel, the value should
be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate.
Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152
Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683
Target pixel clock rate for refresh rate @60 Hz
= 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
As per the timing information for supported panel, the value should
be between 47.2 MHz to 47.9 MHz for 60Hz refresh rate.
Total horizontal pixels = 1024 (x-res) + 80 (margin) + 48 (hsync) = 1152
Total vertical pixels = 600 (y-res) + 80 (margin) + 3 (vsync) = 683
Target pixel clock rate for refresh rate @60 Hz
= 1152 * 683 * 60 = 47208960 Hz ~ 47.5 MHz
Signed-off-by: Tushar Behera <tushar.behera@linaro.org>
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
According to ePAPR, chapter 2.3.4, the status property has
defined that it should be set to "disabled" when "the device
is not presently operational, but it might become operational
in the future".
So this patch disable dwmmc node by "status = disabled" in SOC
dts file and enable dwmmc node by "status = okay" in board specific
dts file.
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add GPIO DT node and pinmux entries for DA850 EVM. GPIO is
configurable differently on different boards. So add GPIO
pinmuxing in dts file.
Signed-off-by: KV Sujith <sujithkv@ti.com>
Signed-off-by: Philip Avinash <avinashphilip@ti.com>
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This adds very basic device tree files for the Marvell Armada
1500-mini SoC (Berlin BG2CD) and the Google Chromecast. Currently,
SoC only has nodes for cpu, some clocks, l2 cache controller, local
timer, apb timers, uart, and interrupt controllers.
The Google Chromecast is a consumer device comprising the Armada
1500-mini SoC above.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
This adds very basic device tree files for the Marvell Armada 1500 SoC
(Berlin BG2) and the Sony NSZ-GS7 GoogleTV board. Currently, SoC only has
nodes for cpus, some clocks, l2 cache controller, local timer, apb timers,
uart, and interrupt controllers. The Sony NSZ-GS7 is a GoogleTV consumer
device comprising the Armada 1500 SoC above.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Jason Cooper <jason@lakedaemon.net>
Reviewed-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Reviewed-by: Arnd Bergmann <arnd@arndb.de>
Reviewed-by: Jisheng Zhang <jszhang@marvell.com>
To be able to enable SDR12|25 for SD-cards, we needed to fixup the
configuration in DT of the gpio regulator, which handles the signal
voltage level. Some configuration were missing and some were wrong.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Remove duplicated configurations and move specific details into
each corresponding dtsi file for the href versions.
Cc: Lee Jones <lee.jones@linaro.org>
Cc: devicetree@vger.kernel.org
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Added device tree support for TI's Keystone USB driver and updated the
Documentation with device tree binding information.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Added device tree support for TI's Keystone USB PHY driver and updated the
Documentation with device tree binding information.
Signed-off-by: WingMan Kwok <w-kwok2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Update the Keystone gic device tree entry to add the maintenance
interrupt information.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Update the Keystone gic node to add the GICV and GIGH address space
needed by the KVM.
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
PA subsystem has a fixed factor clock at the input which is
input clock divided by 3. This patch adds this clock node to dts
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
This patch adds K2 Kepler/Hawking evm (k2hk-evm) specific dts file.
To enable re-use of bindings across multiple evms of this family,
rename current keystone.dts to keystone.dtsi and include it in the
evm specific dts file.
K2 SoC has separate ref clock inputs for various clocks. So add
separate ref clock nodes for ARM, DDR3A, DDR3B and PA PLL input
clocks in k2hk-evm.dts. While at it, rename refclkmain to
refclksys based on device User Guide naming convention
Signed-off-by: Murali Karicheri <m-karicheri2@ti.com>
Signed-off-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Marvell's Armada 370 Reference Design has a NAND flash, so enable it in
the devicetree and add the partitions as prepared in the factory images.
In order to skip the driver's custom device detection and use only ONFI
detection, the "marvell,keep-config" parameter is used. This is needed
because we have no support for setting the timings parameters yet.
Signed-off-by: Ezequiel Garcia <ezequiel.garcia@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The board has 7 buttons connected to GPIOs, add a corresponding
gpio-keys device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch support FSI-AK4648 with simple audio card
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add a 'cpus' node to describe the CPU cores of Zynq.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The bindings for the TTC changed in commit 'arm: zynq: Use standard
timer binding' (e932900a32). That change
removed possible subnodes from this driver rendering the 'clock-ranges'
property invalid for this node.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Peter Crosthwaite <peter.crosthwaite@xilinx.com>
Acked-by: Daniel Lezcano <daniel.lezcano@linaro.org>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The zynq includes a Cadence GEM IP core. This is compatible with the macb driver.
Add it to the zynq-7000 DT.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Cc: Michal Simek <michal.simek@xilinx.com>
Cc: Josh Cartwright <josh.cartwright@ni.com>
[soren: rebased to current Linus tree, added zc706 + zed support, moved phy-mode property to board level dtses]
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
The Allwinner A31 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A31 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org # 3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
The Allwinner A20 uses the ARM GIC as its internal interrupts controller. The
GIC can work on several interrupt triggers, and the A20 was actually setting it
up to use a rising edge as a trigger, while it was actually a level high
trigger, leading to some interrupts that would be completely ignored if the
edge was missed.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Hans de Goede <hdegoede@redhat.com>
Cc: stable@vger.kernel.org #3.12+
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds PWM nodes for each of the four channels present on the
pxa270.
Signed-off-by: Mike Dunn <mikedunn@newsguy.com>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
Now that all Tegra drivers have been converted to use DMA APIs which
retrieve DMA channel information from standard DMA DT properties, we can
remove all the legacy DT DMA-related properties.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Now that all Tegra drivers have been converted to use the common reset
framework, we can remove all the legacy DT clocks/clock-names entries for
"clocks" that were only used with the old custom Tegra module reset API.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
This patch switches the Tegra DT files to use the standard DMA DT bindings
rather than custom properties. Note that the legacy properties are not yet
removed; the drivers must be updated to use the new properties first.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
An earlier patch updated the Tegra DT bindings to require resets and
reset-names properties to be filled in. This patch updates the DT files
to include those properties.
Note that any legacy clocks and clock-names entries that are replaced by
reset properties are not yet removed; the drivers must be updated to use
the new resets and reset-names properties first.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Many of the Tegra DT binding documents say nothing about the clocks or
clock-names properties, yet those are present and required in DT files.
This patch simply updates the documentation file to match the implicit
definition of the binding, based on real-world DT content.
All Tegra bindings that mention clocks are updated to have consistent
wording and formatting of the clock-related properties.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Acked-By: Terje Bergstrom <tbergstrom@nvidia.com>
Added missing clock frequency property to CPU node to avoid
boot time warnings.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Though the default value is 1, add it explicitly to avoid
unnecessary boot warnings and for consistency.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
- Delete some static core module mappings.
- Move EBI location to the device tree.
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Merge tag 'integrator-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
From Linus Walleij:
Two integrator device tree patches for v3.14:
- Delete some static core module mappings.
- Move EBI location to the device tree.
* tag 'integrator-v3.14-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: integrator: move EBI to the device tree
ARM: integrator: delete static core module mappings
Signed-off-by: Kevin Hilman <khilman@linaro.org>
The Allwinner A20 has support for four high speed timers. Apart for the
number of timers (4 vs 2), it's basically the same logic than the high
speed timers found in the sun5i chips.
Now that we have a driver to support it, we can enable them in the
device tree.
[dlezcano] : Fixed conflict with 428abbb8 "Enable the I2C controllers"
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner A13 has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
The Allwinner A10s has support for two high speed timers. Now that we
have a driver to support it, we can enable them in the device tree.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Tested-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
- many little corrections and documentation updates
- LCD FB Device Tree for at91sam9263 and at91sam9g45 boards
- crypto peripherals DT entries + DMA specification
- new Cosino board
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Merge tag 'at91-dt' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
First DT pull-request for 3.14
- many little corrections and documentation updates
- LCD FB Device Tree for at91sam9263 and at91sam9g45 boards
- crypto peripherals DT entries + DMA specification
- new Cosino board
* tag 'at91-dt' of git://github.com/at91linux/linux-at91: (21 commits)
ARM: at91/at91rm9200ek.dts: rearrange nodes in address ascending order
ARM: at91: dt: at91rm9200ek: add emac and nor flash support
ARM: at91: add uart aliases to sama5d3 dtsi
ARM: at91: add i2c2 pinctrl speficifation to sama5d3 DT
ARM: at91: Animeo IP: fix mtd partition table
ARM: at91: at91sam9g45: add i2c pinctrl
ARM: at91: at91sam9g45: set default mmc pinctrl-names
ARM: at91: sama5d3: enable qt1070 as a wakeup source
ARM: at91: add support for Cosino board series by HCE Engineering
ARM: at91/dt/sama5d3: add DMA information to SHA/AES/TDES nodes
ARM: at91/dt/trivial: before sama5d3, Atmel MPU were using at91 prefix
ARM: at91/dt/trivial: use macro for AES irq type
ARM: at91: sam9263ek: add dt lcd support
ARM: at91: at9sam9m10g45ek: add dt lcd support
ARM: at91: sam9263: add fb dt support
ARM: at91: sam9g45: add fb dt support
ARM: at91/dt: binding: add missing compatibility string in SDRAM/DDR documentation
ARM: at91/dt: binding: add precision to AIC documentation
ARM: at91/dt: add atmel,pullup-gpio to at91rm9200ek usb1 definition
ARM: at91/dt: add ethernet phy to at91rm9200ek board
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Add .dts and .dtsi file to support sama5d36ek board.
Also update the the comments for sama5d36 in sama5d3.dtsi.
Signed-off-by: Josh Wu <josh.wu@atmel.com>
Acked-by: Boris BREZILLON <b.brezillon@overkiz.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Based on work for the bockw board by Kuninori Morimoto.
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Based on work for the r8a7778 SoC by Kuninori Morimoto.
Cc: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,intc-irqpin-r8a7779" to the compatible string for the
IRQ pins in case of r8a7779 INTC. This makes the INTC irqpin follow
the same style as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,intc-irqpin-r8a7778" to the compatible string for the
IRQ pins in case of r8a7778 INTC. This makes the INTC irqpin follow
the same style as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,intc-irqpin-r8a7740" to the compatible string for the
IRQ pins in case of r8a7740 INTC. This makes the INTC irqpin follow
the same style as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,intc-irqpin-sh73a0" to the compatible string for the
IRQ pins in case of sh73a0 INTC. This makes the INTC irqpin follow
the same style as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This patch support FSI-WM8978 with simple audio card
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Interrupts generated by SoC internal devices are currently marked as
IRQ_TYPE_NONE. As they're level-triggered and active-high, mark them as
such.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7791 GPIO resources are currently incorrect. Fix that
by making them match the English r8a7791 v0.31 data sheet.
Tested with GPIO LED using Koelsch DT reference.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms@verge.net.au>
Add 2GiB of DRAM at 0x1_8000_0000 to support the full 4GiB
of Lager system memory in case of DT Reference.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add 2GiB of DRAM at 0x1_8000_0000 to support the full 4GiB
of Lager system memory.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add 1GiB of DRAM at 0x2_0000_0000 to support the full 2GiB
of APE6EVM system memory.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add 1GiB of DRAM at 0x2_0000_0000 to support the full 2GiB
of APE6EVM system memory also in case of DT reference.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add led6, led7 and led8 to the Koelsch DT reference board support.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Use the gpio-keys driver to support the 4 pins on the
dip switch DSW2 which is mounted on the KZM9D board.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device is configured to generate an active-low interrupt signal that
needs to be acknowledged by the host. Configure the IRQ to trigger on
low level.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,irqc-r8a7790" to the compatible string for IRQC
in case of r8a7790. This makes the IRQC follow the same style
as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,mmcif-r8a7790" to the compatible string for MMCIF
in case of r8a7790. This makes the MMCIF follow the same style
as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the r8a7791 thermal sensor to the DTS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Hook up the r8a7790 thermal sensor to the DTS.
Signed-off-by: Magnus Damm <damm@opensource.se>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Configure the "D" set of data signals for SCIF0 and SCIF1
on the Koelsch board to setup pinctrl serial console bits.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add "renesas,irqc-r8a7791" to the compatible string for IRQC
in case of r8a7791. This makes the IRQC follow the same style
as the other devices and also makes it more future proof.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
WP pin is not implemented on Marzen
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device is configured to generate an active-low interrupt signal that
is automatically deasserted without requiring any action from the host.
Configure the IRQ to trigger on falling edge.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device is configured to generate an active-low interrupt signal that
is automatically deasserted without requiring any action from the host.
Configure the IRQ to trigger on falling edge.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The device is configured to generate an active-low interrupt signal that
is automatically deasserted without requiring any action from the host.
Use falling edge trigger as that is the configuration currently used on
the board.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
In order to allow usage of the preprocessor in the SoC device tree
sources, switch from /include/ to #include.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add minimum clock tree description to .dts file.
This provides same set of clocks as current sh-clkfwk version .c
code does.
Signed-off-by: Takashi Yoshii <takasi-y@ops.dti.ne.jp>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name.
This patch removed un-used "touchscreen" label
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
According to ePAPR spec,
this patch tidies up DT node name and related clock.
This patch also adds missing SDHI2 entry
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
SCIF0 PFC setting is needed as default
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The PFC device is erroneously declared at address 0xfffc000 instead of
0xfffc0000. Fix it.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Tested-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add DTS for the DT reference version of the Koelsch board support.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add GPIO controllers to the r8a7791 DTSI file.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
SCIF0/SCIF1 PFC setting is needed as default
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add the DT bits for r7s72100 Genmai DT reference support.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add Koelsch and r8a7791 to CONFIG_SHMOBILE_MULTI. At this
point CCF is not yet supported so you cannot run this code
yet. For CCF support to happen several different components
are needed, and this is one simple portion that moves us
forward. Other patches need to build on top of this one.
Koelsch board support exists in 3 flavors:
1) SHMOBILE_MULTI, MACH_KOELSCH - board-koelsch-reference.c (CCF + DT)
2) SHMOBILE, MACH_KOELSCH_REFERENCE - board-koelsch-reference.c (DT)
3) SHMOBILE, MACH_KOELSCH - board-koelsch.c (legacy C code)
When CCF is done then 2) will be removed. When 1) includes same features
as 3) then 3) will be removed.
Signed-off-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
SH-Mobile platforms are transitioning from non-multiplatform to
multiplatform kernel. A new ARCH_SHMOBILE_MULTI configuration symbol has
been created to group all multiplatform-enabled SH-Mobile SoCs. The
existing ARCH_SHMOBILE configuration symbol groups SoCs that haven't
been converted yet.
This arrangement works fine for the arch/ code, but lots of drivers
needed on both ARCH_SHMOBILE and ARCH_SHMOBILE_MULTI depend on
ARCH_SHMOBILE only. In order to avoid changing them, rename
ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY, and create a new boolean
ARCH_SHMOBILE configuration symbol that is selected by both
ARCH_SHMOBILE_LEGACY and ARCH_SHMOBILE_MULTI.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre@atmel.com: remove one macb node too many]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Update to production one.
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable qt1070 keyboard as a wakeup source on sama5d3xek board.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This patch adds the Cosino at91sam9g35 based CPU module and the
Cosino Mega 2560 extension board.
Web site: http://www.cosino.it
Signed-off-by: Rodolfo Giometti <giometti@linux.it>
[plagnioj@jcrosoft.com: added "at91-" to files, pinctrl fixed, removed unneeded stuff]
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
[nicolas.ferre@atmel.com: adapted to newer kernel, modified commit message]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Change the sha/aes/tdes compatibility string to match common
case for the at91sam9g45 family which is to keep the at91 prefix.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Add ethernet phy node in at91rm9200ek.dts.
The reg register is not specified, as it may differ depending on the init
process of the board:
ADDR0/1 phy pins are connected to PA13/14 rm9200 pins. Which means the phy
will take its address from these pins during the reset process.
The macb driver will launch a full scan on the mdio bus to discover the phy
address.
Signed-off-by: Boris BREZILLON <b.brezillon@overkiz.com>
[nicolas.ferre@atmel.com: changed to IRQ_TYPE_EDGE_BOTH as asked by Boris]
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Swap names as they were improperly defined.
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Let's add the Ethernet so NFSroot works and the first MMC card
so people can patch in more support easily.
Signed-off-by: Tony Lindgren <tony@atomide.com>
Now that NAND controller support is available for Armada XP
(cb28e2537a6f: ARM: mvebu: Add support for NAND controller in
Armada 370/XP), this patch enables support for ReadyNAS 2120
and defines default partition layout as delivered by NETGEAR.
As described in similar commits 2be2bc39c6 (ARM: mvebu: Enable
NAND controller in Armada XP GP board) and d8c552dddf (ARM:
mvebu: Enable NAND controller in Armada 370 Mirabox),
"marvell,keep-config" parameter is used as current support does
not allow for setting of timing parameters yet.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that NAND controller support is available for Armada 370
(cb28e2537a6f: ARM: mvebu: Add support for NAND controller in
Armada 370/XP), this patch enables support for ReadyNAS 104 and
defines default partition layout as delivered by NETGEAR.
As described in similar commits 2be2bc39c6 (ARM: mvebu: Enable
NAND controller in Armada XP GP board) and d8c552dddf (ARM:
mvebu: Enable NAND controller in Armada 370 Mirabox),
"marvell,keep-config" parameter is used as current support does
not allow for setting of timing parameters yet.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that NAND controller support is available for Armada 370
(cb28e2537a6f: ARM: mvebu: Add support for NAND controller in
Armada 370/XP), this patch enables support for ReadyNAS 102 and
defines default partition layout as delivered by NETGEAR.
As described in similar commits 2be2bc39c6 (ARM: mvebu: Enable
NAND controller in Armada XP GP board) and d8c552dddf (ARM:
mvebu: Enable NAND controller in Armada 370 Mirabox),
"marvell,keep-config" parameter is used as current support does
not allow for setting of timing parameters yet.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Use GPIO_ACTIVE_HIGH and GPIO_ACTIVE_LOW instead of 0 and 1.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Replace the numeric key value with a symbolic name from
<bt-bindings/input/input.h>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The am3517 is wrongly booting as omap3 which means that the am3517
specific devices like Ethernet won't work when booted with device
tree. Now with the new devices defined in am3517.dtsi, let's use
that instead of the omap3.dtsi, and add a separate machine entry
for am3517 so am3517-evm can use it.
Signed-off-by: Nishanth Menon <nm@ti.com>
[tony@atomide.com: updated comments and fixed build without omap3]
Signed-off-by: Tony Lindgren <tony@atomide.com>
On am3517 there are some extra devices compared to omap3.dtsi that
we currently have not defined. Let's fix that by adding am3517.dtsi
file.
Signed-off-by: Tony Lindgren <tony@atomide.com>
From Srinivas Handagatla, DT updates for STi platforms.
* tag 'DT-for-v3.14-part-1' of http://git.stlinux.com/devel/kernel/linux-sti:
ARM: STi: Add I2C config to B2000 and B2020 boards
ARM: STi: Supply I2C configuration to STiH415 SoC
ARM: STi: Supply I2C configuration to STiH416 SoC
ARM: STi: OF: Fix a typo in pincfg header
Signed-off-by: Olof Johansson <olof@lixom.net>
This is the first step to move AT91 to the CCF.
- core CCF and drivers for most of the clocks
- use of CCF for sama5d3 (100% DT-based)
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Merge tag 'at91-cleanup' of git://github.com/at91linux/linux-at91 into next/cleanup
From Nicolas Ferre:
AT91: Move to Common Clock Framework and sama5d3 implementation
This is the first step to move AT91 to the CCF.
- core CCF and drivers for most of the clocks
- use of CCF for sama5d3 (100% DT-based)
* tag 'at91-cleanup' of git://github.com/at91linux/linux-at91: (22 commits)
ARM: at91/dt: remove old clk material
ARM: at91: move sama5d3 SoC to common clk
ARM: at91/dt: define sama5d3xek's main clk frequency
ARM: at91/dt: define sama5d3 clocks
ARM: at91: prepare common clk transition for sama5d3 SoC
ARM: at91: prepare sama5 dt boards transition to common clk
ARM: at91: add new compatible strings for pmc driver
ARM: at91: move pit timer to common clk framework
dt: binding: add at91 clks dt bindings documentation
clk: at91: add PMC smd clock
clk: at91: add PMC usb clock
clk: at91: add PMC utmi clock
clk: at91: add PMC programmable clocks
clk: at91: add PMC peripheral clocks
clk: at91: add PMC system clocks
clk: at91: add PMC master clock
clk: at91: add PMC pll clocks
clk: at91: add PMC main clock
clk: at91: add PMC macro file for dt definitions
clk: at91: add PMC base support
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This moves the External Bus Interface (EBI) over to a device
tree node and deletes the static mappings from the platform.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
OMAP5 devices can reach high temperatures and thus
needs to have cpufreq-cooling on systems running on it.
This patch adds the required cooling device properties
so that cpufreq-cpu0 driver loads the cooling device.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
This patch changes the dtsi entry on omap5 to contain
the thermal data. This data will enable the passive
cooling with CPUfreq cooling device at 100C. The
system will do a thermal shutdown at 125C whenever
any of its sensors sees this level.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
This patch changes a dtsi file to contain the thermal data
for CORE domain on OMAP5 and later SoCs. This data will
enable a thermal shutdown at 125C.
This thermal data can be reused across TI SoC devices.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
This patch changes a dtsi file to contain the thermal data
for GPU domain on OMAP5 and later SoCs. This data will
enable a thermal shutdown at 125C.
This thermal data can be reused across TI SoC devices.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
OMAP4460 devices can reach high temperatures and thus
needs to have cpufreq-cooling on systems running on it.
This patch adds the required cooling device properties
so that cpufreq-cpu0 driver loads the cooling device.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
OMAP4430 devices can reach high temperatures and thus
needs to have cpufreq-cooling on systems running on it.
This patch adds the required cooling device properties
so that cpufreq-cpu0 driver loads the cooling device.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
This patch changes the dtsi entry on omap4460 to contain
the thermal data. This data will enable the passive
cooling with CPUfreq cooling device at 100C and the
system will do a thermal shutdown at 125C.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Ian Campbell <ian.campbell@citrix.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
This patch changes the dtsi entry on omap4430 to contain
the thermal data. This data will enable the passive
cooling with CPUfreq cooling device at 100C and the
system will do a thermal shutdown at 125C.
Cc: "Benoît Cousson" <bcousson@baylibre.com>
Cc: Tony Lindgren <tony@atomide.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: linux-omap@vger.kernel.org
Cc: devicetree-discuss@lists.ozlabs.org
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Eduardo Valentin <eduardo.valentin@ti.com>
Thierry Reding