Workaround a hardware bug in MSENC during clock enable.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
We will need some tegra peripheral clocks with the CLK_IGNORE_UNUSED flag,
most notably mselect, which is a bridge between AXI and most peripherals.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114 introduces new PLL types. This requires new clocktypes as well
as some new fields in the pll structure.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
PLLC2 and PLLC3 on Tegra114 have separate phaselock and frequencylock bits.
So switch to a lock mask to be able to test both at the same time.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Some PLLs in Tegra114 don't use a power of 2 mapping for the post divider.
Introduce a table based approach and switch PLLU to it.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra114 PLLC2 and PLLC3 don't have a lock enable bit. The lock bits are
always functional.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Not all PLLs in Tegra114 have a bypass bit. Adapt the common code to only use
this bit when available.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Refactor the PLL programming code to make it useable by the new PLL types
introduced by Tegra114.
The following changes were done:
* Split programming the PLL into updating m,n,p and updating cpcon
* Move locking from _update_pll_cpcon() to clk_pll_set_rate()
* Introduce _get_pll_mnp() helper
* Move check for identical m,n,p values to clk_pll_set_rate()
* struct tegra_clk_pll_freq_table will always contain the values as defined
by the hardware.
* Simplify the arguments to clk_pll_wait_for_lock()
* Split _tegra_clk_register_pll()
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
tegra_boot_secondary() relies on some of the car ops. This means having an
uninitialized tegra_cpu_car_ops will lead to an early boot panic.
Providing a dummy struct avoids this and makes adding Tegra114 clock support
in a bisectable way a lot easier.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The Tegra clock driver is initialized during the ARM machine descriptor's
.init_irq() hook. It can't be initialized earlier, since dynamic memory
usage is required. It can't be initialized later, since the .init_timer()
hook needs the clocks initialized. However, at this time, udelay()
doesn't work.
The Tegra clock initialization table may enable some PLLs. Enabling a PLL
may require usage of udelay(). Hence, this can't happen right when the
clock driver is initialized.
To solve this, separate the clock driver initialization from the clock
table processing, so they can execute at separate times.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Correct IDs for cdev1 and cdev2 are 94 and 93 respectively.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: split into separate driver and device-tree patches]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
By default these clocks are children of pll_m, but in downstream kernels
they are reparented to pll_c. While at it, decrease their frequencies to
300 MHz because the defaults aren't in the specified range.
gr2d can reportedly run at much higher frequencies, but 300 MHz works
and is a more conservative default.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The tegra_periph_reset_assert() and tegra_periph_reset_deassert()
functions can be used by drivers to reset peripherals. In order to allow
such drivers to be built as modules, export the functions.
Note that this restores the status quo as the functions were exported
before the move to the drivers/clk tree.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The parameter name should be "gate", not "periph". This worked, however,
because it happens that everywhere periph_clk_to_bit is called, "gate" was
in the local scope.
Signed-off-by: Yen Lin <yelin@nvidia.com>
Signed-off-by: Andrew Chew <achew@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
clk_register will copy this information, so we can just use a normal
array and do one less dynamic allocation.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This flag was in place to prevent important clocks from getting gated
while they had no users. Now that the UART driver supports clocks
properly, we can drop this.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patchset adds DT support for all the AXI, AHB, APB0 and APB1
gates present on sunxi SoCs.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Reviewed-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add gate clocks for fimd, mie, dsim, dp, mixer and hdmi.
Register it to common clock framework.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch extends suspend/resume support for SoC-specific registers to
handle differences in register sets on particular SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing clock control registers to the list of registers
that should be saved across system suspend.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This register is present on all Exynos4 SoCs and so the prefix is
misleading.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This definition is specific for Exynos4210 (which has another location
than the same register on Exynos4x12 SoCs) and so needs appropriate
prefix.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds E4210 prefix to all registers related to LCD1 clock
domain, because they are present only on Exynos4210.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Current clock save list is shared for all Exynos4 SoCs, so it must
contain only registers present in all supported SoCs, because accessing
unavailable registers might have undefined effect.
This patch removes registers specific for particular SoCs from shared
save list, as they should be supported by separate SoC-specific lists.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There are definitions of SRC_MASK_PERIL0 and SRC_MASK_PERIL1 registers,
but they are not used for clock definitions. This patch modifies related
clock definitions to use defined macros instead of numeric offsets.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds preprocessor definitions of EPLL and VPLL registers and
replaces all occurences of offsets of related registers with new
definitions.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing mout_sata that is a parent of div_sata clock.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The patch adds missing clocks to TOP and ISP clock domains.
It also adds clock gates for ISP sub-blocks.
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds clocks needed for G3D block present on Exynos 4 SoCs.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds several gate and mux clocks related to camera and ISP
blocks.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Andrzej Hajda <a.hajda@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch enables clock lookup registration for mout_core clock used in
Exynos4210 cpufreq driver.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Unimplemented clock operations should be simply omitted instead of returning
error values.
This patch removes unimplemented PLL operations to fix problems caused
by returning error code in round_rate callback.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch exports clocks used by Exynos cpufreq drivers to allow lookup
using device tree. (Support to cpufreq drivers will be added in further
patches.)
Signed-off-by: Lukasz Majewski <l.majewski@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The sclk_dac and sclk_mixer clocks are not present on Exynos4x12.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This clock is used by PCM interface 0.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This clock is a parent of mout_spdif and sclk_pcm0.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds missing output of mux MIPIHSI which is needed for
div_mipihsi clock.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Many clock muxes of Exynos 4x12 uses mout_mpll_user_* clocks instead of
sclk_mpll as one of their parents.
This patch moves such clocks from common array into SoC-specific arrays
and adjusts their parent lists respectively.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This clock must be exported to allow lookup using device tree.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Dividers which have CLK_DIVIDER_ONE_BASED set have a redundant state,
being a divider value of zero. Some hardware implementations allow a
zero divider which simply doesn't alter the frequency. I.e. it acts like
a divide by one or bypassing the divider.
This flag is used to handle such HW in the clk-divider model.
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The use common of_clk_init() function simplifies the clock initialization
and adds handling of the DT "fixed-clock".
Signed-off-by: Jean-Francois Moine <moinejf@free.fr>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed $SUBJECT to reflect correct file path]
Reentrancy into the clock framework is necessary for clock operations
that result in nested calls to the clk api. A common example is a clock
that is prepared via an i2c transaction, such as a clock inside of a
discrete audio chip or a power management IC. The i2c subsystem itself
will use the clk api resulting in a deadlock:
clk_prepare(audio_clk)
i2c_transfer(..)
clk_prepare(i2c_controller_clk)
The ability to reenter the clock framework prevents this deadlock.
Other use cases exist such as allowing .set_rate callbacks to call
clk_set_parent to achieve the best rate, or to save power in certain
configurations. Yet another example is performing pinctrl operations
from a clk_ops callback. Calls into the pinctrl subsystem may call
clk_{un}prepare on an unrelated clock. Allowing for nested calls to
reenter the clock framework enables both of these use cases.
Reentrancy is implemented by two global pointers that track the owner
currently holding a global lock. One pointer tracks the owner during
sleepable, mutex-protected operations and the other one tracks the owner
during non-interruptible, spinlock-protected operations.
When the clk framework is entered we try to hold the global lock. If it
is held we compare the current task against the current owner; a match
implies a nested call and we reenter. If the values do not match then
we block on the lock until it is released.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Create locking helpers for the global mutex and global spinlock. The
definitions of these helpers will be expanded upon in the next patch
which introduces reentrancy into the locking scheme.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Rajagopal Venkat <rajagopal.venkat@linaro.org>
Cc: David Brown <davidb@codeaurora.org>
Tested-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Reviewed-by: Ulf Hansson <ulf.hansson@linaro.org>
Under some circumstances the PLLE needs to be retrained, in which case
access to the PMC registers is required. Fix this by passing a pointer
to the PMC registers instead of NULL when registering the PLLE clock.
Signed-off-by: Thierry Reding <thierry.reding@avionic-design.de>
Acked-By: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
It removes the use of mach level IO accessor __mxs_setl/clrl, and hence
removes mach header inclusion from clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Instead of using the static definitions, get clkctrl and digctl base
addresses with mapping from device tree.
Use macro on variable is not nice, but it's done here to save huge
pointless diff stat.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Change call clk_get_sys() to of_clk_get() to look up timrot clock from
device tree, so that the clk_register_clkdev() call for timrot can be
saved in clock driver.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Select CLKSRC_OF and use clocksource_of_init() to initialize timer, so
that the call to mxs_timer_init() in clock driver can be removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This is required so that code such as Tegra's PCIe and clock drivers
can still access this header file once Tegra is converted to
multiplatform, and <mach/> no longer exists.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The current code adds aliases, if necessary, directly when adding
the clock, limiting the number of possible aliases to one.
Some platforms need more than one alias, like the hsmmc pclocks on
s3c2416 which need a "hsmmc" and "mmc_busclk.0" alias for the s3c-
sdhci driver.
Therefore add the possibility to separately add clock aliases for
previously created clocks.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This is needed to allow looking up previous created clocks when
adding separate aliases to them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The clock_init function checked for a dt node, returning immediately
for non-dt machines. This let to the suspend init never being reached
on those non-DT machines.
So fix this by moving the pm init code above the check.
Signed-off-by: Heiko Stueber <heiko@sntech.de>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
On some Samsung platforms divider clocks only use specific divider
combinations like the armdiv on s3c2443 and s3c2416. For these
usecases the generic divider clock already provides the option of
providing a lookup table mapping register values to divider values.
Therefore add a new field to samsung_div_clock and if filled with a
table, use clk_register_divider_table instead of clk_register_divider
to register a divider clock
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Include zynq clk header where init function is declared.
It removes this sparse warning:
drivers/clk/clk-zynq.c:373:13: warning: symbol
'xilinx_zynq_clocks_init' was not declared. Should it be static?
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
During the introduction of the Allwinner SoC platforms, sunxi was
initially meant as a generic name for all the variants of the Allwinner
SoC.
It was ok at the time of the support of only the A10 and A13 that
look pretty much the same; but it's beginning to be troublesome with
the future addition of the Allwinner A31 (sun6i) that is quite
different, and would introduce some weird logic, where sunxi would
actually mean in some case sun4i and sun5i but without sun6i...
Moreover, it makes the compatible strings naming scheme not consistent
with other architectures, where usually for this kind of compability, we
just use the oldest SoC name that has this IP, so let's do just this.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In clk_reg_prcmu(), clk->hw.init field is assigned with a
reference local to clk_reg_prcmu() function.
This patch replaces references to clk->hw.init with calls
to __clk_get_name when called after clock registration.
This patch applies on top of v3.9-rc4.
Signed-off-by: Maxime Coquelin <maxime.coquelin@st.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: resolved trivial merge issues]
Not all clocks are required to be decomposed into basic clock
types but at the same time want to use the functionality
provided by these basic clock types instead of duplicating.
For example, Tegra SoC has ~100 clocks which can be decomposed
into Mux -> Div -> Gate clock types making the clock count to
~300. Also, parent change operation can not be performed on gate
clock which forces to use mux clock in driver if want to change
the parent.
Instead aggregate the basic clock types functionality into one
clock and just use this clock for all operations. This clock
type re-uses the functionality of basic clock types and not
limited to basic clock types but any hardware-specific
implementation.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The Exynos5440 clocks are statically listed and registered using the
Samsung specific common clock helper functions.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos5250 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree based
clock lookup and clkdev based clock lookups are supported.
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The Exynos4 clocks are statically listed and registered using the
Samsung specific common clock helper functions. Both device tree
based clock lookup and clkdev based clock lookups are supported.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There are several types of pll clocks used in Samsung SoC's and these
pll clocks can be represented as Samsung specific pll clock types and
registered with the common clock framework. Add support for pll35xx,
pll36xx, pll45xx, pll46xx and pll2550x clock types and helper functions
to register them.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
All Samsung platforms include different types of clock including
fixed-rate, mux, divider and gate clock types. There are typically
hundreds of such clocks on each of the Samsung platforms. To enable
Samsung platforms to register these clocks using the common clock
framework, a bunch of utility functions are introduced here which
simplify the clock registration process. The clocks are usually
statically instantiated and registered with common clock framework.
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Tested-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Reviewed-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Thomas Abraham <thomas.abraham@linaro.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add a table lookup feature to the mux clock. Also allow arbitrary masks
instead of the width. This will be used by some clocks on Tegra114. Also
adapt the tegra periph clk because it uses struct clk_mux directly.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Tested-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Return type of function clk_propagate_rate_change is a pointer.
But 0 was being returned. Change it to NULL.
Silences the following warning:
drivers/clk/clk.c:977:24: warning: Using plain integer as NULL pointer
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Pankaj Jangra <jangra.pankaj9@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In case of error, the function clk_get() returns ERR_PTR()
not NULL. The NULL test in the return value check should
be replaced with IS_ERR().
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Barry Song <21cnbao@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added missing parenthesis to fix compile break]
Devices on the Intel Lynxpoint Low Power Subsystem (LPSS) have some
common features that aren't shared with any other platform devices,
including the clock and LTR (Latency Tolerance Reporting) registers.
It is better to handle those features in common code than to bother
device drivers with doing that (I/O functionality-wise the LPSS
devices are generally compatible with other devices that don't
have those special registers and may be handled by the same drivers).
The clock registers of the LPSS devices are now taken care of by
the special clk-x86-lpss driver, but the MMIO mappings used for
accessing those registers can also be used for accessing the LTR
registers on those devices (LTR support for the Lynxpoint LPSS is
going to be added by a subsequent patch). Thus it is convenient
to add a special ACPI scan handler for the Lynxpoint LPSS devices
that will create the MMIO mappings for accessing the clock (and
LTR in the future) registers and will register the LPSS devices'
clocks, so the clk-x86-lpss driver will only need to take care of
the main Lynxpoint LPSS clock.
Introduce a special ACPI scan handler for Intel Lynxpoint LPSS
devices as described above. This also reduces overhead related to
browsing the ACPI namespace in search of the LPSS devices before the
registration of their clocks, removes some LPSS-specific (and
somewhat ugly) code from acpi_platform.c and shrinks the overall code
size slightly.
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
This patch corrects wrongly configured parent clock for following
devices:
* Video enc/decoder
* Video ip
* Pin control
* ACP
* camx
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Reviewed-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This driver adds support for the AXI clkgen pcore to the common clock framework.
The AXI clkgen pcore is a AXI front-end to the MMCM_ADV frequency synthesizer
commonly found in Xilinx FPGAs.
The AXI clkgen pcore is used in Analog Devices' reference designs targeting
Xilinx FPGAs.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
To be able to gate unused prcmu clocks from the clk_disable_unused sequence,
clk-prcmu now implements the is_prepared callback.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
An unprepare_unused callback is introduced due to the same reasons to
why the disable_unused callback was added.
During the clk_disable_unused sequence, those clk_hw that needs specific
treatment with regards to being unprepared, shall implement the
unprepare_unused callback.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The unused ungated fast clocks are already being disabled from
clk_disable_unused at late init. This patch extend this sequence
to the slow unused prepared clocks to be unprepared.
Unless the optional .is_prepared callback is implemented by a
clk_hw the clk_disable_unused sequence will not unprepare any
unused clocks, since it will fall back to use the software
prepare counter.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: fixed hlist accessors per b67bfe0d]
To reflect whether a clk_hw is prepared the clk_hw may implement
the optional is_prepared callback. If not implemented we fall back
to use the software prepare counter.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Fix the following sparse warnings:
drivers/clk/mxs/clk.c:17:1: warning: symbol 'mxs_lock' was not declared. Should it be static?
drivers/clk/mxs/clk.c:19:5: warning: symbol 'mxs_clk_wait' was not declared. Should it be static?
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Patch 72480014b8 "Fix device clock divisor calculations" was apparently
rebased incorrectly before it got upstream, causing a build error.
Replacing the "prate" pointer with the local parent_rate is most
likely the correct solution.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Tony Prisk <linux@prisktech.co.nz>
Cc: Mike Turquette <mturquette@linaro.org>
Device drivers should not access MMIO registers through hardcoded
platform specific address constants. Instead, we can pass the
MMIO token to the spear clock driver in the initialization routine
to contain that knowledge in the platform code itself.
Ideally, the clock driver would use of_iomap() or similar to
get the address, and that can be used later, but for now, this
is the minimal change.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Unlike Tegra30, Tegra20 does not have a 7.1 divider for the CPU superclk.
Remove the clocks related to the divider.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Remove duplicate smp_twd clocks as these clocks are accessed using
DT now.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
In the case of some of the ux500 platforms, an Ethernet chip is
placed on an extended bus which is traditionally used as a NAND
flash chip placeholder. The p3_pclk0 clock is used to control it,
so we are required to provide and easy way to access it from the
SMSC911x driver. We do this using an alias provided by this patch.
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The FMSC clock is traditionally used for NAND flash devices when
used on the ux500 series platforms. This patch makes it searchable
during a clock-name search.
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
I'm not sure why, but the hlist for each entry iterators were conceived
list_for_each_entry(pos, head, member)
The hlist ones were greedy and wanted an extra parameter:
hlist_for_each_entry(tpos, pos, head, member)
Why did they need an extra pos parameter? I'm not quite sure. Not only
they don't really need it, it also prevents the iterator from looking
exactly like the list iterator, which is unfortunate.
Besides the semantic patch, there was some manual work required:
- Fix up the actual hlist iterators in linux/list.h
- Fix up the declaration of other iterators based on the hlist ones.
- A very small amount of places were using the 'node' parameter, this
was modified to use 'obj->member' instead.
- Coccinelle didn't handle the hlist_for_each_entry_safe iterator
properly, so those had to be fixed up manually.
The semantic patch which is mostly the work of Peter Senna Tschudin is here:
@@
iterator name hlist_for_each_entry, hlist_for_each_entry_continue, hlist_for_each_entry_from, hlist_for_each_entry_rcu, hlist_for_each_entry_rcu_bh, hlist_for_each_entry_continue_rcu_bh, for_each_busy_worker, ax25_uid_for_each, ax25_for_each, inet_bind_bucket_for_each, sctp_for_each_hentry, sk_for_each, sk_for_each_rcu, sk_for_each_from, sk_for_each_safe, sk_for_each_bound, hlist_for_each_entry_safe, hlist_for_each_entry_continue_rcu, nr_neigh_for_each, nr_neigh_for_each_safe, nr_node_for_each, nr_node_for_each_safe, for_each_gfn_indirect_valid_sp, for_each_gfn_sp, for_each_host;
type T;
expression a,c,d,e;
identifier b;
statement S;
@@
-T b;
<+... when != b
(
hlist_for_each_entry(a,
- b,
c, d) S
|
hlist_for_each_entry_continue(a,
- b,
c) S
|
hlist_for_each_entry_from(a,
- b,
c) S
|
hlist_for_each_entry_rcu(a,
- b,
c, d) S
|
hlist_for_each_entry_rcu_bh(a,
- b,
c, d) S
|
hlist_for_each_entry_continue_rcu_bh(a,
- b,
c) S
|
for_each_busy_worker(a, c,
- b,
d) S
|
ax25_uid_for_each(a,
- b,
c) S
|
ax25_for_each(a,
- b,
c) S
|
inet_bind_bucket_for_each(a,
- b,
c) S
|
sctp_for_each_hentry(a,
- b,
c) S
|
sk_for_each(a,
- b,
c) S
|
sk_for_each_rcu(a,
- b,
c) S
|
sk_for_each_from
-(a, b)
+(a)
S
+ sk_for_each_from(a) S
|
sk_for_each_safe(a,
- b,
c, d) S
|
sk_for_each_bound(a,
- b,
c) S
|
hlist_for_each_entry_safe(a,
- b,
c, d, e) S
|
hlist_for_each_entry_continue_rcu(a,
- b,
c) S
|
nr_neigh_for_each(a,
- b,
c) S
|
nr_neigh_for_each_safe(a,
- b,
c, d) S
|
nr_node_for_each(a,
- b,
c) S
|
nr_node_for_each_safe(a,
- b,
c, d) S
|
- for_each_gfn_sp(a, c, d, b) S
+ for_each_gfn_sp(a, c, d) S
|
- for_each_gfn_indirect_valid_sp(a, c, d, b) S
+ for_each_gfn_indirect_valid_sp(a, c, d) S
|
for_each_host(a,
- b,
c) S
|
for_each_host_safe(a,
- b,
c, d) S
|
for_each_mesh_entry(a,
- b,
c, d) S
)
...+>
[akpm@linux-foundation.org: drop bogus change from net/ipv4/raw.c]
[akpm@linux-foundation.org: drop bogus hunk from net/ipv6/raw.c]
[akpm@linux-foundation.org: checkpatch fixes]
[akpm@linux-foundation.org: fix warnings]
[akpm@linux-foudnation.org: redo intrusive kvm changes]
Tested-by: Peter Senna Tschudin <peter.senna@gmail.com>
Acked-by: Paul E. McKenney <paulmck@linux.vnet.ibm.com>
Signed-off-by: Sasha Levin <sasha.levin@oracle.com>
Cc: Wu Fengguang <fengguang.wu@intel.com>
Cc: Marcelo Tosatti <mtosatti@redhat.com>
Cc: Gleb Natapov <gleb@redhat.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
These are device tree conversions for a number of platforms,
with the intention of turning code from board files into
device tree descriptions. Notable changes are:
* davinci bindings for pinctrl, MTD, RTC, watchdog and i2c
* nomadik bindings for all devices, removing the board files
* bcm2835 bindings for mmc and i2c
* tegra bindings for hdmi, keyboard, audio, as well as some updates
* at91 bindings for hardware ecc and for devices on RM9200
* mxs bindings for cfa100xx
* sunxi support for Miniand Hackberry board
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree conversions from Arnd Bergmann:
"These are device tree conversions for a number of platforms, with the
intention of turning code from board files into device tree
descriptions. Notable changes are:
- davinci bindings for pinctrl, MTD, RTC, watchdog and i2c
- nomadik bindings for all devices, removing the board files
- bcm2835 bindings for mmc and i2c
- tegra bindings for hdmi, keyboard, audio, as well as some updates
- at91 bindings for hardware ecc and for devices on RM9200
- mxs bindings for cfa100xx
- sunxi support for Miniand Hackberry board"
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (72 commits)
Revert "sunxi: a10-cubieboard: Add user LEDs to the device tree"
Revert "sunxi: a13-olinuxino: Add user LED to the device tree"
clk: tegra: initialise parent of uart clocks
ARM: tegra: remove clock-frequency properties from serial nodes
clk: tegra: fix driver to match DT binding
clk: tegra: local arrays should be static
clk: tegra: Add missing spinlock for hclk and pclk
clk: tegra: Implement locking for super clock
clk: tegra: fix wrong clock index between se to sata_cold
sunxi: a13-olinuxino: Add user LED to the device tree
ARM: davinci: da850 DT: add support for machine reboot
ARM: davinci: da850: add wdt DT node
ARM: davinci: da850: add DT node for I2C0
ARM: at91: at91sam9n12: add DT parameters to enable PMECC
ARM: at91: at91sam9x5: add DT parameters to enable PMECC
ARM: at91: add EMAC bindings to RM9200 DT
ARM: at91: add SSC bindings to RM9200 DT
ARM: at91: add MMC bindings to RM9200 DT
ARM: at91: Animeo IP: enable watchdog support
ARM: nomadik: fix OF compilation regression
...
This is a larger set of new functionality for the existing SoC families,
including:
* vt8500 gains support for new CPU cores, notably the Cortex-A9 based wm8850
* prima2 gains support for the "marco" SoC family, its SMP based cousin
* tegra gains support for the new Tegra4 (Tegra114) family
* socfpga now supports a newer version of the hardware including SMP
* i.mx31 and bcm2835 are now using DT probing for their clocks
* lots of updates for sh-mobile
* OMAP updates for clocks, power management and USB
* i.mx6q and tegra now support cpuidle
* kirkwood now supports PCIe hot plugging
* tegra clock support is updated
* tegra USB PHY probing gets implemented diffently
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC-specific updates from Arnd Bergmann:
"This is a larger set of new functionality for the existing SoC
families, including:
- vt8500 gains support for new CPU cores, notably the Cortex-A9 based
wm8850
- prima2 gains support for the "marco" SoC family, its SMP based
cousin
- tegra gains support for the new Tegra4 (Tegra114) family
- socfpga now supports a newer version of the hardware including SMP
- i.mx31 and bcm2835 are now using DT probing for their clocks
- lots of updates for sh-mobile
- OMAP updates for clocks, power management and USB
- i.mx6q and tegra now support cpuidle
- kirkwood now supports PCIe hot plugging
- tegra clock support is updated
- tegra USB PHY probing gets implemented diffently"
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (148 commits)
ARM: prima2: remove duplicate v7_invalidate_l1
ARM: shmobile: r8a7779: Correct TMU clock support again
ARM: prima2: fix __init section for cpu hotplug
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 3/3)
ARM: OMAP: Consolidate OMAP USB-HS platform data (part 1/3)
arm: socfpga: Add SMP support for actual socfpga harware
arm: Add v7_invalidate_l1 to cache-v7.S
arm: socfpga: Add entries to enable make dtbs socfpga
arm: socfpga: Add new device tree source for actual socfpga HW
ARM: tegra: sort Kconfig selects for Tegra114
ARM: tegra: enable ARCH_REQUIRE_GPIOLIB for Tegra114
ARM: tegra: Fix build error w/ ARCH_TEGRA_114_SOC w/o ARCH_TEGRA_3x_SOC
ARM: tegra: Fix build error for gic update
ARM: tegra: remove empty tegra_smp_init_cpus()
ARM: shmobile: Register ARM architected timer
ARM: MARCO: fix the build issue due to gic-vic-to-irqchip move
ARM: shmobile: r8a7779: Correct TMU clock support
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
...
* Updates to the ux500 cpufreq code
* Moving the u300 DMA controller driver to drivers/dma
* Moving versatile express drivers out of arch/arm for sharing with arch/arm64
* Device tree bindings for the OMAP General Purpose Memory Controller
There is a simple conflict in drivers/cpufreq/dbx500-cpufreq.c, because
the mach/id.h header and the cpu_is_u8500_family() function in it are
now gone.
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Merge tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC driver specific changes from Arnd Bergmann:
- Updates to the ux500 cpufreq code
- Moving the u300 DMA controller driver to drivers/dma
- Moving versatile express drivers out of arch/arm for sharing with arch/arm64
- Device tree bindings for the OMAP General Purpose Memory Controller
* tag 'drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (27 commits)
ARM: OMAP2+: gpmc: Add device tree documentation for elm handle
ARM: OMAP2+: gpmc: add DT bindings for OneNAND
ARM: OMAP2+: gpmc-onenand: drop __init annotation
mtd: omap-onenand: pass device_node in platform data
ARM: OMAP2+: Prevent potential crash if GPMC probe fails
ARM: OMAP2+: gpmc: Remove unneeded of_node_put()
arm: Move sp810.h to include/linux/amba/
ARM: OMAP: gpmc: add DT bindings for GPMC timings and NAND
ARM: OMAP: gpmc: enable hwecc for AM33xx SoCs
ARM: OMAP: gpmc-nand: drop __init annotation
mtd: omap-nand: pass device_node in platform data
ARM: OMAP: gpmc: don't create devices from initcall on DT
dma: coh901318: cut down on platform data abstraction
dma: coh901318: merge header files
dma: coh901318: push definitions into driver
dma: coh901318: push header down into the DMA subsystem
dma: coh901318: skip hard-coded addresses
dma: coh901318: remove hardcoded target addresses
dma: coh901318: push platform data into driver
dma: coh901318: create a proper platform data file
...
- Rework of the ACPI namespace scanning code from Rafael J. Wysocki
with contributions from Bjorn Helgaas, Jiang Liu, Mika Westerberg,
Toshi Kani, and Yinghai Lu.
- ACPI power resources handling and ACPI device PM update from
Rafael J. Wysocki.
- ACPICA update to version 20130117 from Bob Moore and Lv Zheng
with contributions from Aaron Lu, Chao Guan, Jesper Juhl, and
Tim Gardner.
- Support for Intel Lynxpoint LPSS from Mika Westerberg.
- cpuidle update from Len Brown including Intel Haswell support, C1
state for intel_idle, removal of global pm_idle.
- cpuidle fixes and cleanups from Daniel Lezcano.
- cpufreq fixes and cleanups from Viresh Kumar and Fabio Baltieri
with contributions from Stratos Karafotis and Rickard Andersson.
- Intel P-states driver for Sandy Bridge processors from
Dirk Brandewie.
- cpufreq driver for Marvell Kirkwood SoCs from Andrew Lunn.
- cpufreq fixes related to ordering issues between acpi-cpufreq and
powernow-k8 from Borislav Petkov and Matthew Garrett.
- cpufreq support for Calxeda Highbank processors from Mark Langsdorf
and Rob Herring.
- cpufreq driver for the Freescale i.MX6Q SoC and cpufreq-cpu0 update
from Shawn Guo.
- cpufreq Exynos fixes and cleanups from Jonghwan Choi, Sachin Kamat,
and Inderpal Singh.
- Support for "lightweight suspend" from Zhang Rui.
- Removal of the deprecated power trace API from Paul Gortmaker.
- Assorted updates from Andreas Fleig, Colin Ian King,
Davidlohr Bueso, Joseph Salisbury, Kees Cook, Li Fei,
Nishanth Menon, ShuoX Liu, Srinivas Pandruvada, Tejun Heo,
Thomas Renninger, and Yasuaki Ishimatsu.
/
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Merge tag 'pm+acpi-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm
Pull ACPI and power management updates from Rafael Wysocki:
- Rework of the ACPI namespace scanning code from Rafael J. Wysocki
with contributions from Bjorn Helgaas, Jiang Liu, Mika Westerberg,
Toshi Kani, and Yinghai Lu.
- ACPI power resources handling and ACPI device PM update from Rafael
J Wysocki.
- ACPICA update to version 20130117 from Bob Moore and Lv Zheng with
contributions from Aaron Lu, Chao Guan, Jesper Juhl, and Tim Gardner.
- Support for Intel Lynxpoint LPSS from Mika Westerberg.
- cpuidle update from Len Brown including Intel Haswell support, C1
state for intel_idle, removal of global pm_idle.
- cpuidle fixes and cleanups from Daniel Lezcano.
- cpufreq fixes and cleanups from Viresh Kumar and Fabio Baltieri with
contributions from Stratos Karafotis and Rickard Andersson.
- Intel P-states driver for Sandy Bridge processors from Dirk
Brandewie.
- cpufreq driver for Marvell Kirkwood SoCs from Andrew Lunn.
- cpufreq fixes related to ordering issues between acpi-cpufreq and
powernow-k8 from Borislav Petkov and Matthew Garrett.
- cpufreq support for Calxeda Highbank processors from Mark Langsdorf
and Rob Herring.
- cpufreq driver for the Freescale i.MX6Q SoC and cpufreq-cpu0 update
from Shawn Guo.
- cpufreq Exynos fixes and cleanups from Jonghwan Choi, Sachin Kamat,
and Inderpal Singh.
- Support for "lightweight suspend" from Zhang Rui.
- Removal of the deprecated power trace API from Paul Gortmaker.
- Assorted updates from Andreas Fleig, Colin Ian King, Davidlohr Bueso,
Joseph Salisbury, Kees Cook, Li Fei, Nishanth Menon, ShuoX Liu,
Srinivas Pandruvada, Tejun Heo, Thomas Renninger, and Yasuaki
Ishimatsu.
* tag 'pm+acpi-3.9-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/rafael/linux-pm: (267 commits)
PM idle: remove global declaration of pm_idle
unicore32 idle: delete stray pm_idle comment
openrisc idle: delete pm_idle
mn10300 idle: delete pm_idle
microblaze idle: delete pm_idle
m32r idle: delete pm_idle, and other dead idle code
ia64 idle: delete pm_idle
cris idle: delete idle and pm_idle
ARM64 idle: delete pm_idle
ARM idle: delete pm_idle
blackfin idle: delete pm_idle
sparc idle: rename pm_idle to sparc_idle
sh idle: rename global pm_idle to static sh_idle
x86 idle: rename global pm_idle to static x86_idle
APM idle: register apm_cpu_idle via cpuidle
cpufreq / intel_pstate: Add kernel command line option disable intel_pstate.
cpufreq / intel_pstate: Change to disallow module build
tools/power turbostat: display SMI count by default
intel_idle: export both C1 and C1E
ACPI / hotplug: Fix concurrency issues and memory leaks
...
None are dire enough to be Cc'd to stable which may be interpreted to
mean that users of the framework are reaching stability. Lots of new
adoption of this framework is via DeviceTree data and that comes through
the respective architecture and platform trees instead of through the
clk framework tree. Two new features are improved debugfs output and an
improvement to how DT clocks are initialized by reusing a common method.
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Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clock framework update from Michael Turquette:
"The common clock framework changes for 3.9 are almost entirely fixes.
None are dire enough to be Cc'd to stable which may be interpreted to
mean that users of the framework are reaching stability. Lots of new
adoption of this framework is via DeviceTree data and that comes
through the respective architecture and platform trees instead of
through the clk framework tree.
Two new features are improved debugfs output and an improvement to how
DT clocks are initialized by reusing a common method."
* tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (25 commits)
clk: sunxi: remove stale Makefile entry
clk: vexpress: Use common of_clk_init() function
clk: zynq: Use common of_clk_init() function
clk: vt8500: Use common of_clk_init() function
clk: highbank: Use common of_clk_init() function
clk: sunxi: Use common of_clk_init() function
clk: add common of_clk_init() function
clk: Deduplicate exit code in clk_set_rate
clk: beautify Makefile
clk-divider: fix macros
clk: prima2: enable dt-binding clkdev mapping
clk: mxs: Index is always positive
clk: max77686: Avoid double free at remove time
clk: remove exported function from __init section
clk: vt8500: Add support for WM8750/WM8850 PLL clocks
clk: vt8500: Fix division-by-0 when requested rate=0
clk: vt8500: Fix device clock divisor calculations
clk: vt8500: Fix error in PLL calculations on non-exact match.
clk: max77686: Remove unnecessary NULL checking for container_of()
clk: JSON debugfs clock tree summary
...
A number of small fixes are included to the new Tegra common clock
driver. These are: Missing locking, definition of device tree clock IDs
not matching the binding, a static cleanup, missing initialization of
some UART clocks.
This branch is based on Tegra's previous pull request tegra-for-3.9-dt.
This dependency is caused by the one patch that edits the device tree.
If this causes a problem, I can drop the final two patches in this pull
request for now, and rebase it onto previous tegra-for-3.9-soc-ccf
instead.
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Merge tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/dt
ARM: tegra: common clock framework fixes
A number of small fixes are included to the new Tegra common clock
driver. These are: Missing locking, definition of device tree clock IDs
not matching the binding, a static cleanup, missing initialization of
some UART clocks.
This branch is based on Tegra's previous pull request tegra-for-3.9-dt.
This dependency is caused by the one patch that edits the device tree.
If this causes a problem, I can drop the final two patches in this pull
request for now, and rebase it onto previous tegra-for-3.9-soc-ccf
instead.
* tag 'tegra-for-3.9-soc-ccf-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
clk: tegra: initialise parent of uart clocks
ARM: tegra: remove clock-frequency properties from serial nodes
clk: tegra: fix driver to match DT binding
clk: tegra: local arrays should be static
clk: tegra: Add missing spinlock for hclk and pclk
clk: tegra: Implement locking for super clock
clk: tegra: fix wrong clock index between se to sata_cold
(applied to next/dt branch rather than next/soc because of the
dependency)
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
* pm-cpufreq: (55 commits)
cpufreq / intel_pstate: Fix 32 bit build
cpufreq: conservative: Fix typos in comments
cpufreq: ondemand: Fix typos in comments
cpufreq: exynos: simplify .init() for setting policy->cpus
cpufreq: kirkwood: Add a cpufreq driver for Marvell Kirkwood SoCs
cpufreq/x86: Add P-state driver for sandy bridge.
cpufreq_stats: do not remove sysfs files if frequency table is not present
cpufreq: Do not track governor name for scaling drivers with internal governors.
cpufreq: Only call cpufreq_out_of_sync() for driver that implement cpufreq_driver.target()
cpufreq: Retrieve current frequency from scaling drivers with internal governors
cpufreq: Fix locking issues
cpufreq: Create a macro for unlock_policy_rwsem{read,write}
cpufreq: Remove unused HOTPLUG_CPU code
cpufreq: governors: Fix WARN_ON() for multi-policy platforms
cpufreq: ondemand: Replace down_differential tuner with adj_up_threshold
cpufreq / stats: Get rid of CPUFREQ_STATDEVICE_ATTR
cpufreq: Don't check cpu_online(policy->cpu)
cpufreq: add imx6q-cpufreq driver
cpufreq: Don't remove sysfs link for policy->cpu
cpufreq: Remove unnecessary use of policy->shared_type
...
Patch 85a18198 "clk: sunxi: Use common of_clk_init() function"
removed the clk-sunxi.c file but left the Makefile entry, which
causes a build error in multi_v7_defconfig:
make[4]: *** No rule to make target `drivers/clk/clk-sunxi.o', needed by `drivers/clk/built-in.o'.
The obvious fix is to remove the extraneous line from the
Makefile.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Cc: Maxime Ripard <maxime.ripard@anandra.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Initialise the parent of UARTs to PLLP and disabling clock by
default.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
enum tegra*_clk is intended to match the IDs listed in the Tegra clock
bindings. There are a few mismatches, which this patch fixes:
1) pll_s and cop were left out of the Tegra20 enum.
2) spdif_in and spdif_out were swapped relative to the Tegra30 binding.
3) i2cslow was misnamed as i2c_slow, and a duplicate i2cslow clock added
to the Tegra30 enum.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <thierry.reding@avionic-design.de>
Tested-by: Thierry Reding <thierry.reding@avionic-design.de>
cclk_g_parents, cclk_lp_parents and sclk_parents are only accessed from within
clk-tegra30.c. Declare them static to avoid namespace polution.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The hclk and pclk clocks are controlled by the same register. Hence a lock is
required to avoid corruption.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Although tegra_clk_register_super_mux() has a lock parameter, the lock is not
actually used by the code. Fixed with this patch.
Signed-off-by: Peter De Schrijver <pdeschrijver@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Reviewed-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The index of se should be 127. And the previous clock index was 125. So
we need to set up the index for se to get the correct index between se
to sata_cold.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
* acpi-lpss:
ACPI / platform: create LPSS clocks if Lynxpoint devices are found during scan
clk: x86: add support for Lynxpoint LPSS clocks
x86: add support for Intel Low Power Subsystem
ACPI / platform: fix comment about the platform device name
ACPI: add support for CSRT table
- A couple of optimization on timer
- Some updates on mxs_defconfig
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Merge tag 'mxs-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/soc
From Shawn Guo:
mxs soc changes for 3.9
- A couple of optimization on timer
- Some updates on mxs_defconfig
* tag 'mxs-soc-3.9' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs_defconfig: Select CONFIG_DEVTMPFS_MOUNT
ARM: mxs: decrease mxs_clockevent_device.min_delta_ns to 2 clock cycles
ARM: mxs: use apbx bus clock to drive the timers on timrotv2
ARM: mxs: Update mxs_defconfig
The Marvell Kirkwood SoCs have simple cpufreq support in hardware. The
CPU can either use the a high speed cpu clock, or the slower DDR
clock. Add a driver to swap between these two clock sources.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
This pull request implements a new "LP2" cpuidle state for Tegra20,
which makes use of the couple cpuidle feature.
It is based on (most of) the previous pull request, with tag
tegra-for-3.9-soc-usb.
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Merge tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: cpuidle enhancements
This pull request implements a new "LP2" cpuidle state for Tegra20,
which makes use of the couple cpuidle feature.
It is based on (most of) the previous pull request, with tag
tegra-for-3.9-soc-usb.
* tag 'tegra-for-3.9-soc-cpuidle' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra:
ARM: tegra20: cpuidle: apply coupled cpuidle for powered-down mode
ARM: tegra20: flowctrl: add support for cpu_suspend_enter/exit
clk: tegra20: Implementing CPU low-power function for tegra_cpu_car_ops
ARM: tegra20: cpuidle: add powered-down state for secondary CPU
ARM: tegra: add pending SGI checking API
Signed-off-by: Olof Johansson <olof@lixom.net>
Tegra already supports the common clock framework, but had issues:
1) The clock driver was located in arch/arm/mach-tegra/ rather than
drivers/clk/.
2) A single "Tegra clock" type was implemented, rather than separate
clock types for PLL, mux, divider, ... type in HW.
3) Clock lookups by device drivers were still driven by device name
and connection ID, rather than through device tree.
This pull request solves all three issues. This required some DT changes
to add clocks properties, and driver changes to request clocks more
"correctly". Finally, this rework allows all AUXDATA to be removed from
Tegra board files, and various duplicate clock lookup entries to be
removed from the driver.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-cleanup.
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Merge tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra into next/soc
From Stephen Warren:
ARM: tegra: Common Clock Framework rework
Tegra already supports the common clock framework, but had issues:
1) The clock driver was located in arch/arm/mach-tegra/ rather than
drivers/clk/.
2) A single "Tegra clock" type was implemented, rather than separate
clock types for PLL, mux, divider, ... type in HW.
3) Clock lookups by device drivers were still driven by device name
and connection ID, rather than through device tree.
This pull request solves all three issues. This required some DT changes
to add clocks properties, and driver changes to request clocks more
"correctly". Finally, this rework allows all AUXDATA to be removed from
Tegra board files, and various duplicate clock lookup entries to be
removed from the driver.
This pull request is based on the previous pull request, with tag
tegra-for-3.9-cleanup.
* tag 'tegra-for-3.9-soc-ccf' of git://git.kernel.org/pub/scm/linux/kernel/git/swarren/linux-tegra: (31 commits)
clk: tegra30: remove unused TEGRA_CLK_DUPLICATE()s
clk: tegra20: remove unused TEGRA_CLK_DUPLICATE()s
ARM: tegra30: remove auxdata
ARM: tegra20: remove auxdata
ASoC: tegra: remove auxdata
staging: nvec: remove use of clk_get_sys
ARM: tegra: paz00: add clock information to DT
ARM: tegra: add clock properties to Tegra30 DT
ARM: tegra: add clock properties to Tegra20 DT
spi: tegra: do not use clock name to get clock
ARM: tegra: remove legacy clock code
ARM: tegra: migrate to new clock code
clk: tegra: add clock support for Tegra30
clk: tegra: add clock support for Tegra20
clk: tegra: add Tegra specific clocks
ARM: tegra: define Tegra30 CAR binding
ARM: tegra: define Tegra20 CAR binding
ARM: tegra: move tegra_cpu_car.h to linux/clk/tegra.h
ARM: tegra: add function to read chipid
ARM: tegra: fix compile error when disable CPU_IDLE
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Conflicts:
arch/arm/mach-tegra/board-dt-tegra20.c
arch/arm/mach-tegra/board-dt-tegra30.c
arch/arm/mach-tegra/common.c
arch/arm/mach-tegra/platsmp.c
drivers/clocksource/Makefile
timer resolution of ~32us is pretty low.
v2 has 32bits resolution, so we have quite some headroom, and
can use the 24MHz clock.
v1 has only 16bits, so we only increase v2.
So we just exchange the timrot clock in imx28.
On imx23 we have timrotv1 and everything stays the same.
Signed-off-by: Torben Hohn <torbenh@linutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The highbank clock will glitch with the current code if the
clock rate is reset without relocking the PLL. Program the PLL
correctly to prevent glitches.
Signed-off-by: Mark Langsdorf <mark.langsdorf@calxeda.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Since it is now used by code under drivers/clk/ it makes sense for this
file to be in a more generic location. This is required for building
vexpress support on arm64.
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Pawel Moll <pawel.moll@arm.com>
Cc: Shiraz Hashim <shiraz.hashim@st.com>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Implementing suspend, resume and rail_off_ready API for tegra_cpu_car_ops. These
functions were used for CPU powered-down state maintenance.
Signed-off-by: Joseph Lo <josephl@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
With device tree support added for Tegra clocks look up is done from
device tree, remove unused TEGRA_CLK_DUPLICATE()s.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Migrate Tegra clock support to drivers/clk/tegra, this involves
moving:
1. definition of tegra_cpu_car_ops to clk.c
2. definition of reset functions to clk-peripheral.c
3. change parent of cpu clock.
4. Remove legacy clock initialization.
5. Initialize clocks using DT.
6. Remove all instance of mach/clk.h
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: use to_clk_periph_gate().]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra30 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: ensure all OF lookups return valid cookies i.e. an explicit
error pointer or valid pointer not NULL, adapt to renames in earlier
patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra20 clock support based on common clock framework.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: s/1GHz/100MHz/ in call to tegra_clk_plle() to fix PCIe,
implemented KBC clock, ensure all OF lookups return valid cookies i.e.
an explicit error pointer or valid pointer not NULL, adapt to renames
in earlier patches, fixed some checkpatch issues.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add Tegra specific clocks, pll, pll_out, peripheral, frac_divider, super.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
[swarren: alloc sizeof(*foo) not sizeof(struct foo), add comments re:
storing pointers to stack variables, make a timeout loop more idiomatic,
use _clk_pll_disable() not clk_disable_pll() from _program_pll() to
avoid redundant lock operations, unified tegra_clk_periph() and
tegra_clk_periph_nodiv(), unified tegra_clk_pll{,e}, rename all clock
registration functions so they don't have the same name as the clock
structs, return -EINVAL from clk_plle_enable when matching table rate
not found, pass ops to _tegra_clk_register_pll rather than a bool.]
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use common of_clk_init() function for clock initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Use common of_clk_init() function for clock initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Reviewed-by: Josh Cartwright <josh.cartwright@ni.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Use common of_clk_init() function for clock initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: added entry for wm8750-pll-clock]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Use common of_clk_init() function for clocks initialization.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Use common of_clk_init() function to initialize clocks.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Acked-by: Maxime Ripard <maxime.ripard@anandra.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Modify of_clk_init function so that it will determine which
driver to initialize based on device tree instead of each driver
registering to it.
Based on a similar patch for drivers/irqchip by Thomas Petazzoni and
drivers/clocksource by Stephen Warren.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Tested-by: Tony Prisk <linux@prisktech.co.nz>
Tested-by: Pawel Moll <pawel.moll@arm.com>
Tested-by: Rob Herring <rob.herring@calxeda.com>
Tested-by: Josh Cartwright <josh.cartwright@ni.com>
Reviewed-by: Josh Cartwright <josh.cartwright@ni.com>
Acked-by: Maxime Ripard <maxime.ripard@anandra.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: merge conflict from missing CLKSRC_OF_TABLES()]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
- fix memory leak in mvebu/clk-cpu.c
- use devm_ to correct/simplify error paths in mvsdio
- add missing #interrupt-cells property in kirkwood
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Merge tag 'mvebu_fixes_for_v3.8-rc5' of git://git.infradead.org/users/jcooper/linux into fixes
From Jason Cooper:
mvebu fixes for v3.8-rc5
- fix memory leak in mvebu/clk-cpu.c
- use devm_ to correct/simplify error paths in mvsdio
- add missing #interrupt-cells property in kirkwood
* tag 'mvebu_fixes_for_v3.8-rc5' of git://git.infradead.org/users/jcooper/linux:
ARM: kirkwood: fix missing #interrupt-cells property
mmc: mvsdio: use devm_ API to simplify/correct error paths.
clk: mvebu/clk-cpu.c: fix memory leakage
Intel Lynxpoint Low Power Subsystem hosts peripherals like UART, I2C and
SPI controllers. For most of these there is a configuration register that
allows software to enable and disable the functional clock. Disabling the
clock while the peripheral is not used saves power.
In order to take advantage of this we add a new clock gate of type
lpss_gate that just re-uses the ordinary clk_gate but in addition is able
to enumerate the base address register of the device using ACPI.
We then create a clock tree that models the Lynxpoint LPSS clocks using
these gates and fixed clocks so that we can pass clock rate to the drivers
as well.
Signed-off-by: Heikki Krogerus <heikki.krogerus@linux.intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Reviewed-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
the variable cpuclk and clk_name should be properly freed when error happens.
Signed-off-by: Cong Ding <dinggnu@gmail.com>
Acked-by: Jason Cooper <jason@lakedaemon.net>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
On non-out case 'return ret;' is equivalent to 'return 0;' as the ret
variable is initialized at 0 and never changed.
Signed-off-by: Nestor Ovroy <novroy@riseup.net>
The list of common clock types was getting a bit unmanageable. This
patch puts only one file on each line and reorders the object files
alphabetically. Also a newline is added to separate the sections.
Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Cc: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The macro is_power_of_two() in clk-divider.c was defined as !(i & ~i)
which is always true. Instead use is_power_of_2() from log2.h.
Also add brackets around the macro arguments in div_mask to avoid any
future operator precedence problems.
Signed-off-by: James Hogan <james.hogan@imgtec.com>
Cc: Joe Perches <joe@perches.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: use log2.h per Joe Perches; update changelog]
this patche deletes hard code that registers clkdev by things like:
clk_register_clkdev(clk, NULL, "b0030000.nand");
clk_register_clkdev(clk, NULL, "b0040000.audio");
clk_register_clkdev(clk, NULL, "b0080000.usp");
prima2 clock controller becomes a clock provider and every dt node
just declares its clock sources by dt prop.
it also makes us easier to extend this driver to support both prima2
and marco as marco has different address mapping with prima2.
Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Fix the following warnings when building with W=1 option:
drivers/clk/mxs/clk-imx23.c: In function 'mx23_clocks_init':
drivers/clk/mxs/clk-imx23.c:149:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
drivers/clk/mxs/clk-imx23.c:165:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
...
drivers/clk/mxs/clk-imx28.c: In function 'mx28_clocks_init':
drivers/clk/mxs/clk-imx28.c:227:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
drivers/clk/mxs/clk-imx28.c:244:16: warning: comparison between signed and unsigned integer expressions [-Wsign-compare]
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The clk_lookup entry is dropped at remove time by a call to
clkdev_drop(). That function frees the entry, which is also freed by the
driver core as it has been allocated through devm_kzalloc(). This
results in a double free.
Use kzalloc() instead of devm_kzalloc() to fix this.
Signed-off-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The symbol of_fixed_clk_setup is exported and annotated __init.
This looks like section mismatch.
Fix this by removing the __init annotation of of_fixed_clk_setup.
Signed-off-by: Denis Efremov <yefremov.denis@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds support for the new PLL module found in WM8750 and
WM8850 SoCs.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
A request to vt8500_dclk_(round_rate/set_rate) with rate=0 results
in a division-by-0 in the kernel.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
When calculating device clock divisor values in set_rate and
round_rate, we do a simple integer divide. If parent_rate / rate
has a fraction, this is dropped which results in the device clock
being set too high.
This patch corrects the problem by adding 1 to the calculated
divisor if the division would have had a decimal result.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
When a PLL frequency calculation is performed and a non-exact match
is found the wrong multiplier and divisors are returned.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
container_of() never returns NULL, thus remove the NULL checking for it.
Also rename get_max77686_clk() to to_max77686_clk() for better readability.
Signed-off-by: Axel Lin <axel.lin@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This will allow fixed-clocks to be registered in device tree, which in
turn will allow clock clients to look up their clocks in device tree.
The first driver to use this feature will be the bcm2835 SDHCI/MMC
driver. In the long run, it is likely these fixed clocks will be
replaced with an actual clock implementation which speaks to the
VideoCore processor, but this change should be transparent to clock
consumers.
Cc: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Clock information is dumped in JSON format which is easy
for machines to parse.
Each clock is represented as an object which has same name as
clock and following properties
- enable_count
- prepare_count
- rate
Output is verified using online JSON editor.
Signed-off-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
clk->rate = parent->rate / div * mult
The formula is OK. But it may overflow while we do operate with
unsigned long. So use do_div instead.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improved $SUBJECT]
This fixes the following error when building for arm-imx:
> ERROR: "__clk_get_name" [drivers/staging/imx-drm/ipu-v3/imx-ipu-v3.ko] undefined!
> make[1]: *** [__modpost] Error 1
> make: *** [modules] Error 2
There are valid usecases to get the name of a clock, be it for debugging
purposes or to register a children of a clock like done in this IPU driver.
Therefore exporting __clk_get_name() and make it available for others makes
sense.
Reported-by: Peter Robinson <pbrobinson@gmail.com>
CC: Sascha Hauer <s.hauer@pengutronix.de>
CC: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Niels de Vos <ndevos@redhat.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removal of inline made redundant by 65800b2]
The helper functions that access the opaque struct clk should
not be marked inline since they are contained in clk.c, but expected
to be used by other compilation units. This causes compile errors
under gcc-4.7
In file included from arch/arm/mach-omap2/clockdomain.c:25:0:
arch/arm/mach-omap2/clockdomain.c: In function ‘clkdm_clk_disable’:
include/linux/clk-provider.h:338:12: error: inlining failed in call to always_inline ‘__clk_get_enable_count’: function body not available
arch/arm/mach-omap2/clockdomain.c:1001:28: error: called from here
make[1]: *** [arch/arm/mach-omap2/clockdomain.o] Error 1
make: *** [arch/arm/mach-omap2] Error 2
Signed-off-by: Russ Dill <Russ.Dill@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: removed fixes made redundant by commit 93532c8a]
[mturquette@linaro.org: improved $SUBJECT]
People are back from the holiday breaks, and it shows. Here are a bunch of
fixes for a number of platforms:
- A couple of small fixes for Nomadik
- A larger set of changes for kirkwood/mvebu
- uart driver selection, dt clocks, gpio-poweroff fixups,
a few __init annotation fixes and some error handling improvement
in their xor dma driver.
- i.MX had a couple of minor fixes (and a critical one for flexcan2
clock setup)
- MXS has a small board fix and a framebuffer bugfix
- A set of fixes for Samsung Exynos, fixing default bootargs and some
Exynos5440 clock issues
- A set of OMAP changes including PM fixes and a few sparse warning
fixups
All in all a bit more positive code delta than we'd ideally want to see
here, mostly from the OMAP PM changes, but nothing overly crazy.
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Merge tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"People are back from the holiday breaks, and it shows. Here are a
bunch of fixes for a number of platforms:
- A couple of small fixes for Nomadik
- A larger set of changes for kirkwood/mvebu
- uart driver selection, dt clocks, gpio-poweroff fixups, a few
__init annotation fixes and some error handling improvement in
their xor dma driver.
- i.MX had a couple of minor fixes (and a critical one for flexcan2
clock setup)
- MXS has a small board fix and a framebuffer bugfix
- A set of fixes for Samsung Exynos, fixing default bootargs and some
Exynos5440 clock issues
- A set of OMAP changes including PM fixes and a few sparse warning
fixups
All in all a bit more positive code delta than we'd ideally want to
see here, mostly from the OMAP PM changes, but nothing overly crazy."
* tag 'fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (44 commits)
ARM: clps711x: Fix bad merge of clockevents setup
ARM: highbank: save and restore L2 cache and GIC on suspend
ARM: highbank: add a power request clear
ARM: highbank: fix secondary boot and hotplug
ARM: highbank: fix typos with hignbank in power request functions
ARM: dts: fix highbank cpu mpidr values
ARM: dts: add device_type prop to cpu nodes on Calxeda platforms
ARM: mx5: Fix MX53 flexcan2 clock
ARM: OMAP2+: am33xx-hwmod: Fix wrongly terminated am33xx_usbss_mpu_irqs array
pinctrl: mvebu: make pdma clock on dove mandatory
ARM: Dove: Add pinctrl clock to DT
dma: mv_xor: fix error handling for clocks
dma: mv_xor: fix error handling of mv_xor_channel_add()
arm: mvebu: Add missing ; for cpu node.
arm: mvebu: Armada XP MV78230 has only three Ethernet interfaces
arm: mvebu: Armada XP MV78230 has two cores, not one
clk: mvebu: Remove inappropriate __init tagging
ARM: Kirkwood: Use fixed-regulator instead of board gpio call
ARM: Kirkwood: Fix missing sdio clock
ARM: Kirkwood: Switch TWSI1 of 88f6282 to DT clock providers
...
If the Orion WDT driver is built as a module, an opps occurs during
clk lookup when calling mvebu_clk_gating_get_src(). Remove the
inappropriate __init tag so the function is available for modules
after kernel init.
Signed-off-by: Joshua Coombs <josh.coombs@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
CONFIG_HOTPLUG is going away as an option. As a result, the __dev*
markings need to be removed.
This change removes the use of __devinit, __devexit_p, __devinitdata,
__devinitconst, and __devexit from these drivers.
Based on patches originally written by Bill Pemberton, but redone by me
in order to handle some of the coding style issues better, by hand.
Cc: Bill Pemberton <wfp5p@virginia.edu>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
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Merge tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd
Pull MTD updates from David Woodhouse:
- Various cleanups especially in NAND tests
- Add support for NAND flash on BCMA bus
- DT support for sh_flctl and denali NAND drivers
- Kill obsolete/superceded drivers (fortunet, nomadik_nand)
- Fix JFFS2 locking bug in ENOMEM failure path
- New SPI flash chips, as usual
- Support writing in 'reliable mode' for DiskOnChip G4
- Debugfs support in nandsim
* tag 'for-linus-20121219' of git://git.infradead.org/linux-mtd: (96 commits)
mtd: nand: typo in nand_id_has_period() comments
mtd: nand/gpio: use io{read,write}*_rep accessors
mtd: block2mtd: throttle writes by calling balance_dirty_pages_ratelimited.
mtd: nand: gpmi: reset BCH earlier, too, to avoid NAND startup problems
mtd: nand/docg4: fix and improve read of factory bbt
mtd: nand/docg4: reserve bb marker area in ecclayout
mtd: nand/docg4: add support for writing in reliable mode
mtd: mxc_nand: reorder part_probes to let cmdline override other sources
mtd: mxc_nand: fix unbalanced clk_disable() in error path
mtd: nandsim: Introduce debugfs infrastructure
mtd: physmap_of: error checking to prevent a NULL pointer dereference
mtg: docg3: potential divide by zero in doc_write_oob()
mtd: bcm47xxnflash: writing support
mtd: tests/read: initialize buffer for whole next page
mtd: at91: atmel_nand: return bit flips for the PMECC read_page()
mtd: fix recovery after failed write-buffer operation in cfi_cmdset_0002.c
mtd: nand: onfi need to be probed in 8 bits mode
mtd: nand: add NAND_BUSWIDTH_AUTO to autodetect bus width
mtd: nand: print flash size during detection
mted: nand_wait_ready timeout fix
...
This is a branch with updates for Marvell's mvebu/kirkwood platforms. They
came in late-ish, and were heavily interdependent such that it didn't
make sense to split them up across the cross-platform topic branches. So
here they are (for the second release in a row) in a branch on their own.
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Merge tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates for Marvell mvebu/kirkwood from Olof Johansson:
"This is a branch with updates for Marvell's mvebu/kirkwood platforms.
They came in late-ish, and were heavily interdependent such that it
didn't make sense to split them up across the cross-platform topic
branches. So here they are (for the second release in a row) in a
branch on their own."
* tag 'mvebu' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (88 commits)
arm: l2x0: add aurora related properties to OF binding
arm: mvebu: add Aurora L2 Cache Controller to the DT
arm: mvebu: add L2 cache support
dma: mv_xor: fix error handling path
dma: mv_xor: fix error checking of irq_of_parse_and_map()
dma: mv_xor: use request_irq() instead of devm_request_irq()
dma: mv_xor: clear the window override control registers
arm: mvebu: fix address decoding armada_cfg_base() function
ARM: mvebu: update defconfig with I2C and RTC support
ARM: mvebu: Add SATA support for OpenBlocks AX3-4
ARM: mvebu: Add support for the RTC in OpenBlocks AX3-4
ARM: mvebu: Add support for I2C on OpenBlocks AX3-4
ARM: mvebu: Add support for I2C controllers in Armada 370/XP
arm: mvebu: Add hardware I/O Coherency support
arm: plat-orion: Add coherency attribute when setup mbus target
arm: dma mapping: Export a dma ops function arm_dma_set_mask
arm: mvebu: Add SMP support for Armada XP
arm: mm: Add support for PJ4B cpu and init routines
arm: mvebu: Add IPI support via doorbells
arm: mvebu: Add initial support for power managmement service unit
...
This branch contains device-tree updates for the SPEAr platform.
They had dependencies on earlier branches from this merge window,
which is why they were broken out in a separate branch.
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Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device-tree updates, take 2, from Olof Johansson:
"This branch contains device-tree updates for the SPEAr platform. They
had dependencies on earlier branches from this merge window, which is
why they were broken out in a separate branch."
* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: SPEAr3xx: Shirq: Move shirq controller out of plat/
ARM: SPEAr320: DT: Add SPEAr 320 HMI board support
ARM: SPEAr3xx: DT: add shirq node for interrupt multiplexor
ARM: SPEAr3xx: shirq: simplify and move the shared irq multiplexor to DT
ARM: SPEAr1310: Fix AUXDATA for compact flash controller
ARM: SPEAr13xx: Remove fields not required for ssp controller
ARM: SPEAr1310: Move 1310 specific misc register into machine specific files
ARM: SPEAr: DT: Update device nodes
ARM: SPEAr: DT: add uart state to fix warning
ARM: SPEAr: DT: Modify DT bindings for STMMAC
ARM: SPEAr: DT: Fix existing DT support
ARM: SPEAr: DT: Update partition info for MTD devices
ARM: SPEAr: DT: Update pinctrl list
ARM: SPEAr13xx: DT: Add spics gpio controller nodes
Here are more patches in the progression towards multiplatform, sparse
irq conversions in particular.
Tegra has a handful of cleanups and general groundwork, but is
not quite there yet on full enablement.
Platforms that are enabled through this branch are VT8500 and Zynq. note
that i.MX was converted in one of the earlier cleanup branches as
well (before we started a separate topic for multiplatform). And both
new platforms for this merge window, sunxi and bcm, were merged with
multiplatform support enabled.
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Merge tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC multiplatform conversion patches from Olof Johansson:
"Here are more patches in the progression towards multiplatform, sparse
irq conversions in particular.
Tegra has a handful of cleanups and general groundwork, but is not
quite there yet on full enablement.
Platforms that are enabled through this branch are VT8500 and Zynq.
Note that i.MX was converted in one of the earlier cleanup branches as
well (before we started a separate topic for multiplatform). And both
new platforms for this merge window, sunxi and bcm, were merged with
multiplatform support enabled."
Fix up conflicts mostly as per Olof.
* tag 'multiplatform' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (29 commits)
ARM: zynq: Remove all unused mach headers
ARM: zynq: add support for ARCH_MULTIPLATFORM
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: remove TTC early mapping
ARM: tegra: move debug-macro.S to include/debug
ARM: tegra: don't include iomap.h from debug-macro.S
ARM: tegra: decouple uncompress.h and debug-macro.S
ARM: tegra: simplify DEBUG_LL UART selection options
ARM: tegra: select SPARSE_IRQ
ARM: tegra: enhance timer.c to get IO address from device tree
ARM: tegra: enhance timer.c to get IRQ info from device tree
ARM: timer: fix checkpatch warnings
ARM: tegra: add TWD to device tree
ARM: tegra: define DT bindings for and instantiate RTC
ARM: tegra: define DT bindings for and instantiate timer
clocksource/mtu-nomadik: use apb_pclk
clk: ux500: Register mtu apb_pclocks
ARM: plat-nomadik: convert platforms to SPARSE_IRQ
mfd/db8500-prcmu: use the irq_domain_add_simple()
mfd/ab8500-core: use irq_domain_add_simple()
...
Continued device tree conversion and enablement across a number of
platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
smaller series as well.
ux500 has seen continued conversion for platforms. Several platforms have
seen pinctrl-via-devicetree conversions for simpler multiplatform. Tegra
is adding data for new devices/drivers, and Exynos has a bunch of new
bindings and devices added as well.
So, pretty much the same progression in the right direction as the last
few releases.
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC device tree conversions and enablement from Olof Johansson:
"Continued device tree conversion and enablement across a number of
platforms; Kirkwood, tegra, i.MX, Exynos, zynq and a couple of other
smaller series as well.
ux500 has seen continued conversion for platforms. Several platforms
have seen pinctrl-via-devicetree conversions for simpler
multiplatform. Tegra is adding data for new devices/drivers, and
Exynos has a bunch of new bindings and devices added as well.
So, pretty much the same progression in the right direction as the
last few releases."
Fix up conflicts as per Olof.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (185 commits)
ARM: ux500: Rename dbx500 cpufreq code to be more generic
ARM: dts: add missing ux500 device trees
ARM: ux500: Stop registering the PCM driver from platform code
ARM: ux500: Move board specific GPIO info out to subordinate DTS files
ARM: ux500: Disable the MMCI gpio-regulator by default
ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
ARM: Kirkwood: Add support LED of OpenBlocks A6
ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
ARM: kirkwood: Add support DT of second I2C bus
ARM: kirkwood: Convert mplcec4 board to pinctrl
ARM: Kirkwood: Convert km_kirkwood to pinctrl
ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
ARM: Kirkwood: Convert IX2-200 to pinctrl.
ARM: Kirkwood: Convert lsxl boards to pinctrl.
ARM: Kirkwood: Convert ib62x0 to pinctrl.
ARM: Kirkwood: Convert GoFlex Net to pinctrl.
ARM: Kirkwood: Convert dreamplug to pinctrl.
ARM: Kirkwood: Convert dockstar to pinctrl.
...
This contains the bulk of new SoC development for this merge window.
Two new platforms have been added, the sunxi platforms (Allwinner A1x
SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
series of ARMv7 platforms from them, where the hope is that we can
keep the platform code generic enough to have them all share one mach
directory. The new Broadcom platform is contributed by Christian Daudt.
Highbank has grown support for Calxeda's next generation of hardware,
ECX-2000.
clps711x has seen a lot of cleanup from Alexander Shiyan, and he's also
taken on maintainership of the platform.
Beyond this there has been a bunch of work from a number of people on
converting more platforms to IRQ domains, pinctrl conversion, cleanup
and general feature enablement across most of the active platforms.
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC updates from Olof Johansson:
"This contains the bulk of new SoC development for this merge window.
Two new platforms have been added, the sunxi platforms (Allwinner A1x
SoCs) by Maxime Ripard, and a generic Broadcom platform for a new
series of ARMv7 platforms from them, where the hope is that we can
keep the platform code generic enough to have them all share one mach
directory. The new Broadcom platform is contributed by Christian
Daudt.
Highbank has grown support for Calxeda's next generation of hardware,
ECX-2000.
clps711x has seen a lot of cleanup from Alexander Shiyan, and he's
also taken on maintainership of the platform.
Beyond this there has been a bunch of work from a number of people on
converting more platforms to IRQ domains, pinctrl conversion, cleanup
and general feature enablement across most of the active platforms."
Fix up trivial conflicts as per Olof.
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (174 commits)
mfd: vexpress-sysreg: Remove LEDs code
irqchip: irq-sunxi: Add terminating entry for sunxi_irq_dt_ids
clocksource: sunxi_timer: Add terminating entry for sunxi_timer_dt_ids
irq: versatile: delete dangling variable
ARM: sunxi: add missing include for mdelay()
ARM: EXYNOS: Avoid early use of of_machine_is_compatible()
ARM: dts: add node for PL330 MDMA1 controller for exynos4
ARM: EXYNOS: Add support for secondary CPU bring-up on Exynos4412
ARM: EXYNOS: add UART3 to DEBUG_LL ports
ARM: S3C24XX: Add clkdev entry for camif-upll clock
ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
ARM: sunxi: Add missing sun4i.dtsi file
pinctrl: samsung: Do not initialise statics to 0
ARM i.MX6: remove gate_mask from pllv3
ARM i.MX6: Fix ethernet PLL clocks
ARM i.MX6: rename PLLs according to datasheet
ARM i.MX6: Add pwm support
ARM i.MX51: Add pwm support
ARM i.MX53: Add pwm support
ARM: mx5: Replace clk_register_clkdev with clock DT lookup
...
Cleanup patches for various ARM platforms and some of their associated
drivers. There's also a branch in here that enables Freescale i.MX to be
part of the multiplatform support -- the first "big" SoC that is moved
over (more multiplatform work comes in a separate branch later during
the merge window).
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Merge tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC cleanups on various subarchitectures from Olof Johansson:
"Cleanup patches for various ARM platforms and some of their associated
drivers. There's also a branch in here that enables Freescale i.MX to
be part of the multiplatform support -- the first "big" SoC that is
moved over (more multiplatform work comes in a separate branch later
during the merge window)."
Conflicts fixed as per Olof, including a silent semantic one in
arch/arm/mach-omap2/board-generic.c (omap_prcm_restart() was renamed to
omap3xxx_restart(), and a new user of the old name was added).
* tag 'cleanup' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (189 commits)
ARM: omap: fix typo on timer cleanup
ARM: EXYNOS: Remove unused regs-mem.h file
ARM: EXYNOS: Remove unused non-dt support for dwmci controller
ARM: Kirkwood: Use hw_pci.ops instead of hw_pci.scan
ARM: OMAP3: cm-t3517: use GPTIMER for system clock
ARM: OMAP2+: timer: remove CONFIG_OMAP_32K_TIMER
ARM: SAMSUNG: use devm_ functions for ADC driver
ARM: EXYNOS: no duplicate mask/unmask in eint0_15
ARM: S3C24XX: SPI clock channel setup is fixed for S3C2443
ARM: EXYNOS: Remove i2c0 resource information and setting of device names
ARM: Kirkwood: checkpatch cleanups
ARM: Kirkwood: Fix sparse warnings.
ARM: Kirkwood: Remove unused includes
ARM: kirkwood: cleanup lsxl board includes
ARM: integrator: use BUG_ON where possible
ARM: integrator: push down SC dependencies
ARM: integrator: delete static UART1 mapping
ARM: integrator: delete SC mapping on the CP
ARM: integrator: remove static CP syscon mapping
ARM: integrator: remove static AP syscon mapping
...
Here's the large driver core updates for 3.8-rc1.
The biggest thing here is the various __dev* marking removals. This is
going to be a pain for the merge with different subsystem trees, I know,
but all of the patches included here have been ACKed by their various
subsystem maintainers, as they wanted them to go through here.
If this is too much of a pain, I can pull all of them out of this tree
and just send you one with the other fixes/updates and then, after
3.8-rc1 is out, do the rest of the removals to ensure we catch them all,
it's up to you. The merges should all be trivial, and Stephen has been
doing them all in linux-next for a few weeks now quite easily.
Other than the __dev* marking removals, there's nothing major here, some
firmware loading updates and other minor things in the driver core.
All of these have (much to Stephen's annoyance), been in linux-next for
a while.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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Merge tag 'driver-core-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core
Pull driver core updates from Greg Kroah-Hartman:
"Here's the large driver core updates for 3.8-rc1.
The biggest thing here is the various __dev* marking removals. This
is going to be a pain for the merge with different subsystem trees, I
know, but all of the patches included here have been ACKed by their
various subsystem maintainers, as they wanted them to go through here.
If this is too much of a pain, I can pull all of them out of this tree
and just send you one with the other fixes/updates and then, after
3.8-rc1 is out, do the rest of the removals to ensure we catch them
all, it's up to you. The merges should all be trivial, and Stephen
has been doing them all in linux-next for a few weeks now quite
easily.
Other than the __dev* marking removals, there's nothing major here,
some firmware loading updates and other minor things in the driver
core.
All of these have (much to Stephen's annoyance), been in linux-next
for a while.
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>"
Fixed up trivial conflicts in drivers/gpio/gpio-{em,stmpe}.c due to gpio
update.
* tag 'driver-core-3.8-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/gregkh/driver-core: (93 commits)
modpost.c: Stop checking __dev* section mismatches
init.h: Remove __dev* sections from the kernel
acpi: remove use of __devinit
PCI: Remove __dev* markings
PCI: Always build setup-bus when PCI is enabled
PCI: Move pci_uevent into pci-driver.c
PCI: Remove CONFIG_HOTPLUG ifdefs
unicore32/PCI: Remove CONFIG_HOTPLUG ifdefs
sh/PCI: Remove CONFIG_HOTPLUG ifdefs
powerpc/PCI: Remove CONFIG_HOTPLUG ifdefs
mips/PCI: Remove CONFIG_HOTPLUG ifdefs
microblaze/PCI: Remove CONFIG_HOTPLUG ifdefs
dma: remove use of __devinit
dma: remove use of __devexit_p
firewire: remove use of __devinitdata
firewire: remove use of __devinit
leds: remove use of __devexit
leds: remove use of __devinit
leds: remove use of __devexit_p
mmc: remove use of __devexit
...
Some gate clocks have special needs which must be handled during the
disable-unused clocks sequence. These needs might be driven by software
due to the fact that we're disabling a clock outside of the normal
clk_disable path and a clk's enable_count will not be accurate. On the
other hand a specific hardware programming sequence might need to be
followed for this corner case.
This change is needed for the upcoming OMAP port to the common clock
framework. Specifically, it is undesirable to treat the disable-unused
path identically to the normal clk_disable path since other software
layers are involved. In this case OMAP's clockdomain code throws WARNs
and bails early due to the clock's enable_count being set to zero. A
custom callback mitigates this problem nicely.
Cc: Paul Walmsley <paul@pwsan.com>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This fixes a bit error in the U8500 clock implementation: the
unused p2_pclk12 registered at bit 12 in periphereral group 6
was defined as using bit 11 rather than bit 12.
When walking over and disabling the unused clocks in the tree
at late init time, p2_pclk12 was disabled, by effectively
clearing the but for p2_pclk11 instead of bit 12 as it should
have, thus disabling gpio block 6 and 7.
Reported-by: Lee Jones <lee.jones@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Cc: Philippe Begnic <philippe.begnic@st.com>
Cc: stable@kernel.org
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
From Kukjin Kim:
Just adding camif gpio setup and clkdev.
* 'next/cam-samsung' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C24XX: Add clkdev entry for camif-upll clock
ARM: SAMSUNG: Add s3c24xx/s3c64xx CAMIF GPIO setup helpers
+ Linux 3.7-rc6
Conflicts due to the 3.7-rc6 sync: arch/arm/mach-highbank/system.c
include/linux/clk-provider.h, resolved as in other branches.
Signed-off-by: Olof Johansson <olof@lixom.net>
CONFIG_HOTPLUG is going away as an option so __devexit is no
longer needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CONFIG_HOTPLUG is going away as an option so __devinit is no longer
needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
CONFIG_HOTPLUG is going away as an option so __devexit_p is no longer
needed.
Signed-off-by: Bill Pemberton <wfp5p@virginia.edu>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
When a clock, C is initialised any orphan clocks listing C as
a possible parent are reparented to it regardless of the
parent requested by the orphan's get_parent() operation.
This means that multiplexers registered before their parents
are reparented to the first parent subsequently declared,
regardless of the selection made by the hardware registers.
For example:
static const char *sel[] = { "srcA", "srcB", "dummy", "srcC" };
child = clk_register_mux(NULL, "child", sel, ARRAY_SIZE(sel), ...);
clk_register_fixed(NULL, "dummy", ...);
clk_register_fixed(NULL, "srcA", ...);
clk_register_fixed(NULL, "srcB", ...);
clk_register_fixed(NULL, "srcC", ...);
Causes child's parent to always be "dummy".
To fix this, when an orphanned clock has a get_parent() operation,
only reparent to the clock indicated by get_parent().
Signed-off-by: Martin Fuzzey <mfuzzey@parkeon.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
[mturquette@linaro.org: improve $SUBJECT]
The abx500 clock driver is a platform driver which will be initialized
during arch init. The platform device shall be added from the ab-core
driver as a mfd child device to maintain correct boot sequence.
Depending on what ab version we use, different clock definitions will
be added.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch moves some global macro definitions to the files where they are used.
Its a step towards removing spear.h completely later on.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
- ehci-orion dt binding
- gpio-poweroff
- use dt regulators
- move mpp to DT/pinctrl
Depends on:
- orion/boards
- merge conflicts
- keep all 'select's in Kconfig
- remove all #includes in board-*.c
- pinctrl/devel up to:
- 06763c7 pinctrl: mvebu: move to its own directory
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Merge tag 'orion_dt_for_3.8' of git://git.infradead.org/users/jcooper/linux into next/dt
From Jason Cooper:
orion dt for v3.8
- ehci-orion dt binding
- gpio-poweroff
- use dt regulators
- move mpp to DT/pinctrl
Depends on:
- orion/boards
- merge conflicts
- keep all 'select's in Kconfig
- remove all #includes in board-*.c
- pinctrl/devel up to:
- 06763c7 pinctrl: mvebu: move to its own directory
* tag 'orion_dt_for_3.8' of git://git.infradead.org/users/jcooper/linux: (211 commits)
ARM: Kirkwood: remove kirkwood_ehci_init() from new boards
ARM: Kirkwood: Add support LED of OpenBlocks A6
ARM: Kirkwood: Convert to EHCI via DT for OpenBlocks A6
ARM: kirkwood: Add NAND partiton map for OpenBlocks A6
ARM: kirkwood: Add support second I2C bus and RTC on OpenBlocks A6
ARM: kirkwood: Add support DT of second I2C bus
ARM: kirkwood: Convert mplcec4 board to pinctrl
ARM: Kirkwood: Convert km_kirkwood to pinctrl
ARM: Kirkwood: support 98DX412x kirkwoods with pinctrl
ARM: Kirkwood: Convert IX2-200 to pinctrl.
ARM: Kirkwood: Convert lsxl boards to pinctrl.
ARM: Kirkwood: Convert ib62x0 to pinctrl.
ARM: Kirkwood: Convert GoFlex Net to pinctrl.
ARM: Kirkwood: Convert dreamplug to pinctrl.
ARM: Kirkwood: Convert dockstar to pinctrl.
ARM: Kirkwood: Convert dnskw to pinctrl
ARM: Kirkwood: Convert iConnect to pinctrl.
ARM: Kirkwood: Convert TS219 to pinctrl.
ARM: Kirkwood: Add DTSI files for pinctrl
ARM: Kirkwood: Make use of mvebu pincltl and gpio drivers
...
Signed-off-by: Olof Johansson <olof@lixom.net>
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Merge tag 'v3.7-rc7' into next/cleanup
Merging in mainline back to next/cleanup since it has collected a few
conflicts between fixes going upstream and some of the cleanup patches.
Git doesn't auto-resolve some of them, and they're mostly noise so let's
take care of it locally.
Conflicts are in:
arch/arm/mach-omap2/omap_hwmod_44xx_data.c
arch/arm/plat-omap/i2c.c
drivers/video/omap2/dss/dss.c
Signed-off-by: Olof Johansson <olof@lixom.net>
From Michal Simek:
This branch depends on arm-soc devel/debug_ll_init branch because
we needed Rob's "ARM: implement debug_ll_io_init()"
(sha1: afaee03511ba8002b26a9c6b1fe7d6baf33eac86)
patch.
This branch also depends on zynq/dt branch because of previous major
zynq changes.
zynq/cleanup branch is subset of zynq/dt.
* 'zynq/multiplatform' of git://git.monstr.eu/linux-2.6-microblaze:
ARM: zynq: Remove all unused mach headers
ARM: zynq: add support for ARCH_MULTIPLATFORM
ARM: zynq: make use of debug_ll_io_init()
ARM: zynq: remove TTC early mapping
ARM: zynq: add clk binding support to the ttc
ARM: zynq: use zynq clk bindings
clk: Add support for fundamental zynq clks
ARM: zynq: dts: split up device tree
ARM: zynq: Allow UART1 to be used as DEBUG_LL console.
ARM: zynq: dts: add description of the second uart
ARM: zynq: move arm-specific sys_timer out of ttc
zynq: move static peripheral mappings
zynq: remove use of CLKDEV_LOOKUP
zynq: use pl310 device tree bindings
zynq: use GIC device tree bindings
Add/add conflict in arch/arm/Kconfig.debug.
Signed-off-by: Olof Johansson <olof@lixom.net>
Dummy clocks were added for ARM platforms, so that clk_get() for interface clk
doesn't fail for amba devices from amba_probe(). Because there is no amba device
for SPEAr that doesn't have a valid clock with dev_id for SPEAr, we don't need
these dummy clocks. Hence, remove them.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The patch corrects the case when the rate table is being scanned for a
given frequency, and the search frequency is beyond the maximum
frequency indexed in the table.
By default, the system should be set at max frequency present in the
rate table. This patch correctly returns the corresponding index value.
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Flag CLK_SET_RATE_PARENT is required for a clock, where we want to
propagate clk_set_rate to its parent. This patch adds this to multiple clocks.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Vijay Kumar Mishra <vijay.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch updates mux clock names of multiple clocks. It updates _clk with
_mclk to make it more readable.
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
dev_id & con_id names of multiple clocks are incorrect. This patch fixes these
names with the names that come via DT.
Signed-off-by: Rajeev Kumar <rajeev-dlh.kumar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Signed-off-by: Bhavna Yadav <bhavna.yadav@st.com>
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Deepak Sikri <deepak.sikri@st.com>
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The ARM IM-PD1 add-on module has a few clock of its own, let's
move also these down to the drivers/clk/versatile driver dir
and get rid of any remaining oldschool Integrator clocks.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
It turns out that all platforms using the ICST VCO are really
just touching two registers, and in the same way as well: one
register with the VCO configuration as such, and one lock register
that makes it possible to write to the VCO.
Factor this register read/write into the ICST driver so we can
reuse it in the IM-PD1 driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The GPLv2 headers were missing and the subsystem maintainer likes
them so put them in. I am the copyright holder, so explicitly
licensing these under the GPLv2.
Reported-by: Mike Turquette <mturquette@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
From Mike Turquette:
* depends/clk:
clk: Common clocks implementation for Versatile Express
clk: Versatile Express clock generators ("osc") driver
CLK: clk-twl6040: Initial clock driver for OMAP4+ McPDM fclk clock
clk: fix return value check in sirfsoc_of_clk_init()
clk: fix return value check in of_fixed_clk_setup()
clk: ux500: Update sdmmc clock to 100MHz for u8500
clk: ux500: Support prcmu ape opp voltage clock
mfd: dbx500: Export prmcu_request_ape_opp_100_voltage
clk: Don't return negative numbers for unsigned values with !clk
clk: Fix documentation typos
clk: Document .is_enabled op
clk: SPEAr: Vco-pll: Fix compilation warning
This driver allows to provide DT clocks for clock gates found on
Marvell Dove and Kirkwood SoCs. The clock gates are referenced by
the phandle index of the corresponding bit in the clock gating control
register to ease lookup in the datasheet.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Add Armada 370/XP specific CPU clocks
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Tested-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove & 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.
Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Tested-by Gregory CLEMENT <gregory.clement@free-electrons.com>
Use a better name for the USB PHY clock.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This fixes compile error if one of SPEAr3xx implementations is not selected.
CC drivers/clk/spear/spear3xx_clock.o
drivers/clk/spear/spear3xx_clock.c: In function 'spear3xx_clk_init':
drivers/clk/spear/spear3xx_clock.c:599:3: error: implicit declaration of function 'spear300_clk_init' [-Werror=implicit-function-declaration]
drivers/clk/spear/spear3xx_clock.c:601:3: error: implicit declaration of function 'spear310_clk_init' [-Werror=implicit-function-declaration]
drivers/clk/spear/spear3xx_clock.c:603:3: error: implicit declaration of function 'spear320_clk_init' [-Werror=implicit-function-declaration]
cc1: some warnings being treated as errors
make[3]: *** [drivers/clk/spear/spear3xx_clock.o] Error 1
make[2]: *** [drivers/clk/spear] Error 2
make[1]: *** [drivers/clk] Error 2
make: *** [drivers] Error 2
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The Nomadik NAND driver is really just a subset of the existing
FSMC driver, so let's switch over to using that driver instead,
since it handles more variants of this chip. The callbacks for
setting up the chip is doing stuff now handled by the FSMC
driver.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Alessandro Rubini <rubini@unipv.it>
Signed-off-by: Artem Bityutskiy <artem.bityutskiy@linux.intel.com>
Make the Zynq platform use the newly created zynq clk bindings.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Acked-by: Michal Simek <michal.simek@xilinx.com>
Provide simplified models for the necessary clocks on the zynq-7000
platform. Currently, the PLLs, the CPU clock network, and the basic
peripheral clock networks (for SDIO, SMC, SPI, QSPI, UART) are modelled.
OF bindings are also provided and documented.
Signed-off-by: Josh Cartwright <josh.cartwright@ni.com>
Signed-off-by: Soren Brinkmann <soren.brinkmann@xilinx.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Michal Simek <michal.simek@xilinx.com>
At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
At the same time the prcc bit for the kclk is corrected to
bit 8 instead of 3.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: Wolfram Sang <w.sang@pengutronix.de>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds some additional handling for the SDMMC special case
in round_rate and set_rate which results in invalid divisor messages
at boot time.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In case of error, the function clk_register_fixed_rate() returns
ERR_PTR() and never returns NULL. The NULL test in the return value
check should be replaced with IS_ERR().
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The new armss clk is a prcmu_scalable_rate clk which represents
the ARMSS clk. This then makes it possible to convert the smp_twd
clk to a fixed factor clock type, using a fixed divider of 2 and
with the armss clk as parent.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The prcmu_scalable_rate clock can change rate but is not gateable.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The ux500 clock driver file named u8500_clk.c does not compile
if it loose implicit dependencies to <mach/db8500-regs.h>
(I have no clue what files will include this) which manifests
itself as I'm experimenting with SPARSE_IRQ so make the
dependency explicit.
Cc: Mike Turquette <mturquette@linaro.org>
Acked-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move this driver to use devm_clk_register() to simplify some
error paths and reduce lines of code.
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Some clock drivers can be simplified if devres takes care of
unregistering any registered clocks along error paths. Introduce
devm_clk_register() so that clock drivers get unregistration for
free along with simplified error paths.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
clk_register() returns an ERR_PTR upon failure, not NULL. Fix
these error paths.
Acked-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds a DT and non-DT based implementation of
the common clock infrastructure for Versatile Express
platform. It registers (statically or using DT) all
required fixed clocks, initialises motherboard's SP810
cell (that provides clocks for SP804 timers) and
explicitly registers VE "osc" driver, to make the
clock generators available early.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This driver provides a common clock framework hardware driver
for Versatile Express clock generators (a.k.a "osc") controlled
via the config bus.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
On OMAP4+ platforms the functional clock for the McPDM IP is suplied by
the twl6040 codec (bit clock on the PDM bus).
This common clock driver for twl6040 will register the mcpdm_fclk clock to
be used by the McPDM driver to make sure that the needed clocks are
available when needed.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In case of error, the function clk_register() returns ERR_PTR()
and never returns NULL. The NULL test in the return value check
should be replaced with IS_ERR().
dpatch engine is used to auto generate this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In case of error, the function clk_register_fixed_rate() returns
ERR_PTR() not NULL pointer. The NULL test in the return value
check should be replaced with IS_ERR().
dpatch engine is used to auto generated this patch.
(https://github.com/weiyj/dpatch)
Signed-off-by: Wei Yongjun <yongjun_wei@trendmicro.com.cn>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
For u8500 and using 100MHz as the frequency also requires the ape opp 100
voltage, thus use the prcmu_opp_volt_scalable clock type.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Some scalable prcmu clocks needs to be handled in conjuction with the
ape opp 100 voltage. A new prcmu clock type clk_prcmu_opp_volt_scalable
is implemented to handle this.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Some of the helper functions return negative error codes if
passed a NULL clock. This can lead to confusing behavior when the
expected return value is unsigned. Fix up these accessors so that
they return unsigned values (or bool in the case of is_enabled).
This way we can't interpret NULL clocks as having valid and
interesting values.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Currently we are getting following warning for SPEAr clk-vco-pll.
"warning: i is used uninitialized in this function."
This is because we are getting value of i by passing its pointer to another
routine.
The variables here are really not used uninitialized.
Signed-off-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Fix typo in message reported when unable to lookup the uart1 clock.
Signed-off-by: Domenico Andreoli <domenico.andreoli@linux.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
No framework work here, only a bunch of driver updates of varying sizes:
- Factoring out of the core hardware support from the MXS MMC driver by
Marek Vasut to allow the hardware to also be used for SPI.
- Lots of error handling cleanups from Guenter Roeck
- Removal of the existing Tegra driver which is quite comprehensively
broken as detailed in the changelog for the removal.
- DT suppport for the PL022 and GPIO drivers.
- pinctrl support for OMAP and PL022.
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Merge tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc
Pull spi updates from Mark Brown:
"No framework work here, only a bunch of driver updates of varying
sizes:
- Factoring out of the core hardware support from the MXS MMC driver
by Marek Vasut to allow the hardware to also be used for SPI.
- Lots of error handling cleanups from Guenter Roeck
- Removal of the existing Tegra driver which is quite comprehensively
broken as detailed in the changelog for the removal.
- DT suppport for the PL022 and GPIO drivers.
- pinctrl support for OMAP and PL022."
Pulling from Mark Brown as Grant Likely is still busy moving.
* tag 'spi-3.7' of git://git.kernel.org/pub/scm/linux/kernel/git/broonie/misc: (53 commits)
spi: remove completely broken Tegra driver
spi/imx: set the inactive state of the clock according to the clock polarity
spi/pl022: get/put resources on suspend/resume
spi/pl022: use more managed resources
spi/pl022: Devicetree support w/o platform data
spi/s3c64xx: Don't free controller_data on non-dt platforms
spi: omap2-mcspi: add pinctrl support
spi/pl022: adopt pinctrl support
spi: omap2-mcspi: Cleanup the omap2_mcspi_txrx_dma function
spi/gpio: Fix stub for spi_gpio_probe_dt()
spi/mxs: Make the SPI block clock speed configurable via DT
spi: spi-sh-hspi: drop frees of devm_ alloc'd data
spi/pl022: Fix chipselects pointer computation
spi: spi-tle62x0: Use module_spi_driver macro
mxs/spi: Rework the mxs_ssp_timeout to be more readable
mxs/spi: Decrement the DMA/PIO border
mxs/spi: Increment the transfer length only if transfer succeeded
mxs/spi: Fix issues when doing long continuous transfer
spi: spi-gpio: Add DT bindings
spi: spi-gpio: store chipselect information in private structure
...
This branch converts the MXS Freescale platform to use irqdomains and
sparse IRQ, in preparation for DT probing and multiplatform kernels.
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc-specific updates, take 2 from Olof Johansson:
"This branch converts the MXS Freescale platform to use irqdomains and
sparse IRQ, in preparation for DT probing and multiplatform kernels."
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
ARM: mxs: remove mach/irqs.h
ARM: mxs: select SPARSE_IRQ
ARM: mxs: adopt irq_domain support for icoll driver
ARM: mxs: select MULTI_IRQ_HANDLER
ARM: mxs: retrieve timer irq from device tree
gpio/mxs: adopt irq_domain support for mxs gpio driver
Device tree conversion and enablement branch. Mostly a bunch of new
bindings and setup for various platforms, but the Via/Winchip VT8500
platform is also converted over from being 100% legacy to now use
device tree for probing. More of that will come for 3.8.
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Merge tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc device tree updates from Olof Johansson:
"Device tree conversion and enablement branch. Mostly a bunch of new
bindings and setup for various platforms, but the Via/Winchip VT8500
platform is also converted over from being 100% legacy to now use
device tree for probing. More of that will come for 3.8."
Trivial conflicts due to removal of vt8500 files, and one documentation
file that was added with slightly different contents both here and in
the USb tree.
* tag 'dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (212 commits)
arm: vt8500: Fixup for missing gpio.h
ARM: LPC32xx: LED fix in PHY3250 DTS file
ARM: dt: mmp-dma: add binding file
arm: vt8500: Update arch-vt8500 to devicetree support.
arm: vt8500: gpio: Devicetree support for arch-vt8500
arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
arm: vt8500: clk: Add Common Clock Framework support
video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
serial: vt8500: Add devicetree support for vt8500-serial
rtc: vt8500: Add devicetree support for vt8500-rtc
arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
ARM: tegra: Add Avionic Design Tamonten Evaluation Carrier support
ARM: tegra: Add Avionic Design Medcom-Wide support
ARM: tegra: Add Avionic Design Plutux support
ARM: tegra: Add Avionic Design Tamonten support
ARM: tegra: dts: Add pwm label
ARM: ux500: Fix SSP register address format
ARM: ux500: Apply tc3589x's GPIO/IRQ properties to HREF's DT
ARM: ux500: Remove redundant #gpio-cell properties from Snowball DT
ARM: ux500: Add all encompassing sound node to the HREF Device Tree
...
Most notable here is probably the addition of basic support for the
BCM2835, an SoC used in some of the Roku 2 players as well as the
much-hyped Raspberry Pi, cleaned up and contributed by Stephen
Warren. It's still early days on mainline support, with just the
basics working. But it has to start somewhere!
Beyond that there's some conversions of clock infrastructure on tegra
to common clock, misc updates for several other platforms, and OMAP
now has its own bus (under drivers/bus) to manage its devices through.
This branch adds two new directories outside of arch/arm:
drivers/irqchip for new irq controllers, and drivers/bus for the above
OMAP bus. It's expected that some of the other platforms will migrate
parts of their platforms to those directories over time as well.
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM soc-specific updates from Olof Johansson:
"Most notable here is probably the addition of basic support for the
BCM2835, an SoC used in some of the Roku 2 players as well as the
much-hyped Raspberry Pi, cleaned up and contributed by Stephen Warren.
It's still early days on mainline support, with just the basics
working. But it has to start somewhere!
Beyond that there's some conversions of clock infrastructure on tegra
to common clock, misc updates for several other platforms, and OMAP
now has its own bus (under drivers/bus) to manage its devices through.
This branch adds two new directories outside of arch/arm:
drivers/irqchip for new irq controllers, and drivers/bus for the above
OMAP bus. It's expected that some of the other platforms will migrate
parts of their platforms to those directories over time as well."
Fix up trivial conflicts with the clk infrastructure changes.
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (62 commits)
ARM: shmobile: add new __iomem annotation for new code
ARM: LPC32xx: Support GPI 28
ARM: LPC32xx: Platform update for devicetree completion of spi-pl022
ARM: LPC32xx: Board cleanup
irqchip: fill in empty Kconfig
ARM: SAMSUNG: Add check for NULL in clock interface
ARM: EXYNOS: Put PCM, Slimbus, Spdif clocks to off state
ARM: EXYNOS: Add bus clock for FIMD
ARM: SAMSUNG: Fix HDMI related warnings
ARM: S3C24XX: Add .get_rate callback for "camif-upll" clock
ARM: EXYNOS: Fix incorrect help text
ARM: EXYNOS: Turn off clocks for NAND, OneNAND and TSI controllers
ARM: OMAP: AM33xx hwmod: fixup SPI after platform_data move
MAINTAINERS: add an entry for the BCM2835 ARM sub-architecture
ARM: bcm2835: instantiate console UART
ARM: bcm2835: add stub clock driver
ARM: bcm2835: add system timer
ARM: bcm2835: add interrupt controller driver
ARM: add infra-structure for BCM2835 and Raspberry Pi
ARM: tegra20: add CPU hotplug support
...
ports to the framework along with one MIPS port, one MFD port, one minor
framework enhancement and one helper function for platforms expressing
their clock data through device tree.
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Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull clk framework update from Michael Turquette:
"The common clk framework changes for 3.7 are dominated by ARM platform
ports to the framework along with one MIPS port, one MFD port, one
minor framework enhancement and one helper function for platforms
expressing their clock data through device tree."
* tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux:
clk: add of_clk_src_onecell_get() support
clk: ux500: Define smp_twd clock for u8500
mfd: dbx500: Provide a more accurate smp_twd clock
clk: ux500: Support for prmcu_rate clock
clk: Provide option for clk_get_rate to issue hw for new rate
clock: max77686: Add driver for Maxim 77686 32Khz crystal oscillator.
ARM: ux500: Switch to use common clock framework
clk: ux500: Clock definitions for u8500
clk: ux500: First version of clock definitions for ux500
clk: ux500: Adapt PRCMU and PRCC clocks for common clk
clk: versatile: make config option boolean
clk: add Loongson1B clock support
arm: mmp: make all SOCs use common clock by default
clk: mmp: add clock definition for mmp2
clk: mmp: add clock definition for pxa910
clk: mmp: add clock definition for pxa168
clk: mmp: add mmp specific clocks
clk: convert ARM RealView to common clk
clk: prima2: move from arch/arm/mach to drivers/clk
ARM: PRIMA2: convert to common clk and finish full clk tree
remove existing non-dt code.
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Merge tag 'vt8500-for-next' of git://git.code.sf.net/p/linuxwmt/code into next/dt
From Tony Prisk:
Update arch-vt8500 and drivers to device tree and
remove existing non-dt code.
* tag 'vt8500-for-next' of git://git.code.sf.net/p/linuxwmt/code:
arm: vt8500: Update arch-vt8500 to devicetree support.
arm: vt8500: gpio: Devicetree support for arch-vt8500
arm: vt8500: doc: Add device tree bindings for arch-vt8500 devices
arm: vt8500: clk: Add Common Clock Framework support
video: vt8500: Add devicetree support for vt8500-fb and wm8505-fb
serial: vt8500: Add devicetree support for vt8500-serial
rtc: vt8500: Add devicetree support for vt8500-rtc
arm: vt8500: Add device tree files for VIA/Wondermedia SoC's
Resolved add/change conflict in drivers/clk/Makefile.
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds common clock framework support for arch-vt8500.
Support for PLL and device clocks on VT8500, WM8505 and WM8650
are included.
Signed-off-by: Tony Prisk <linux@prisktech.co.nz>
Acked-by: Mike Turquette <mturquette@linaro.org>
This patch adds a minimal stub clock driver for the BCM2835. Its sole
purpose is to allow the PL011 AMBA clk_get() API calls to provide
something that looks enough like a clock that the driver probes and
operates correctly.
This patch was extracted from git://github.com/lp0/linux.git branch
rpi-split as of 2012/09/08, and modified as follows:
* Reworked to call clk_register_fixed_rate(), and clk_register_clkdev()
rather than using static data to represent the clocks.
* Moved implementation to drivers/clk/.
* Modified .dev_id for UART clocks to match UART DT node names.
* s/bcm2708/bcm2835/.
* Modified device tree vendor prefix.
Signed-off-by: Chris Boot <bootc@bootc.net>
Signed-off-by: Simon Arlott <simon@fire.lp0.eu>
Signed-off-by: Dom Cobley <popcornmix@gmail.com>
Signed-off-by: Dom Cobley <dc4@broadcom.com>
Signed-off-by: Stephen Warren <swarren@wwwdotorg.org>
Acked-by: Mike Turquette <mturquette@linaro.org>
Surprisingly devres_destroy() doesn't call the destructor for the
resource it is destroying, use the newly added devres_release() instead
to fix this.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The managed clk functions are currently only available when the generic clk
lookup framework is build. But the managed clk functions are merely wrappers
around clk_get and clk_put and do not depend on any specifics of the generic
lookup functions and there are still quite a few custom implementations of the
clk API. So make the managed functions available whenever the clk API is
implemented.
The patch also removes the custom implementation of devm_clk_get for the
coldfire platform.
Signed-off-by: Lars-Peter Clausen <lars@metafoo.de>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
It replaces clk_register_clkdev in mxs clock driver with DT lookup.
The series depends on pull request mxs-dt-3.7 and Mike's clk branch
below.
git://git.linaro.org/people/mturquette/linux.git clk-3.7
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Merge tag 'mxs-clk-dt-lookup' of git://git.linaro.org/people/shawnguo/linux-2.6 into next/dt
It replaces clk_register_clkdev in mxs clock driver with DT lookup.
* tag 'mxs-clk-dt-lookup' of git://git.linaro.org/people/shawnguo/linux-2.6:
clk: mxs: replace imx23 clk_register_clkdev with clock DT lookup
clk: mxs: replace imx28 clk_register_clkdev with clock DT lookup
It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.
Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx23 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
It really becomes a maintenance issue that every time a device needs
to look up (clk_get) a clock we have to patch kernel clock file to call
clk_register_clkdev for that clock.
Since clock DT support which is meant to resolve clock lookup in device
tree is in place, the patch moves imx28 client devices' clock lookup
over to device tree, so that any new lookup to be added at later time
can just get done in DT instead of kernel.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For those SoCs that have hundreds of clock outputs, their clock
DT bindings could reasonably define #clock-cells as 1 and require
the client device specify the index of the clock it consumes in the
cell of its "clocks" phandle.
Add a generic of_clk_src_onecell_get() function for this purpose.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The smp_twd clock is based upon a prcmu_rate clock type
for the PRCMU_ARMSS clock.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The prmcu_rate clock is not gateable and has a rate which
only can be fetched.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
By using CLK_GET_RATE_NOCACHE flag, we tell the clk_get_rate API to
issue the hw for an updated clock rate. This can be used for a clock
which rate may be updated without a client necessary modifying it.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch supports max77686 mfd's clock driver using common clock frame work.
max77686 has 3 clock ouputs which all are generated from crystal oscillator and
SOC can enable/disable them via I2C bus. All clocks are fixed-rate clock sources
so that it doesn't supply interface for changing clock rate.
Driver uses regmap API to communicate with internal register.
Signed-off-by: Jonghwa Lee <jonghwa3.lee@samsung.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Remove machine specific clock implementation and switch to use
new common clock framework.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
First version of clock definitions of PRCMU and PRCC clocks
for the u8500 platform.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
In this first version of the clock definitions, the structure for
ux500 are set. Support for u8500, u9540 and u8540 are prepared.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
First version of common clock implementation of PRCMU clocks
and PRCC clocks for ux500 platforms.
Signed-off-by: Ulf Hansson <ulf.hansson@linaro.org>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
There is no choice to have the RealView clocks as module for sure,
so turn this config option into a boolean.
Reported-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Rather than using the static timer irq definition, we should retrieve
timer irq from device tree for better.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This adds clock support to Loongson1B SoC using the common clock
infrastructure.
Signed-off-by: Kelvin Cheung <keguang.zhang@gmail.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This converts the ARM RealView machine over to using the common
clock. The approach is similar to the one used for the Integrator,
and we're reusing the ICST wrapper code.
We have to put the clock intialization in the timer init function
for the clocks to be available when initializing the timer,
keeping them in early_init() is too early for the common clk.
Since we now have to go down and compile drivers/clk/versatile
a CONFIG_COMMON_CLK_VERSATILE symbol has been added so the proper
code gets compiled into the kernel for either machine. A leftover
CLK_VERSATILE in the Integrator Kconfig was fixed up to use
the new symbol as well.
Tested on ARM RealView PB1176.
Cc: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Pull out the MMC clock configuration function and make it
into SSP clock configuration function, so it can be used by
the SPI driver too.
Signed-off-by: Marek Vasut <marex@denx.de>
Acked-by: Chris Ball <cjb@laptop.org>
Acked-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
clk_get() returns -ENOENT on error and some careless caller might
dereference it without error checking:
In mxc_rnga_remove():
struct clk *clk = clk_get(&pdev->dev, "rng");
// ...
clk_disable(clk);
Since it's insane to audit the lots of existing and future clk users,
let's add a check in the callee to avoid kernel panic and warn about
any buggy user.
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Viresh Kumar <viresh.kumar@st.com>
Cc: viresh kumar <viresh.linux@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
menu "Common Clock Framework" has "depends on COMMON_CLK" and so configs
defined within menu don't require these "depends on COMMON_CLK again".
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Cc: Wolfram Sang <w.sang@pengutronix.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Jeff Garzik <jgarzik@redhat.com>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Bhupesh Sharma <bhupesh.sharma@st.com>
Cc: Giuseppe Cavallaro <peppe.cavallaro@st.com>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Mike Turquette <mturquette@linaro.org>
Cc: Sergei Shtylyov <sshtylyov@ru.mvista.com>
Cc: viresh kumar <viresh.linux@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
framework improvments, platform ports and new DT bindings.
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Merge tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux
Pull common clk framework changes from Michael Turquette:
"This includes a small number of core framework improvments, platform
ports and new DT bindings."
Fix up trivial conflicts in drivers/clk/Makefile
* tag 'clk-for-linus' of git://git.linaro.org/people/mturquette/linux: (21 commits)
clk: fix compile for OF && !COMMON_CLK
clk: fix clk_get on of_clk_get_by_name return check
clk: mxs: clk_register_clkdev mx28 usb clocks
clk: add highbank clock support
dt: add clock binding doc to primecell bindings
clk: add DT fixed-clock binding support
clk: add DT clock binding support
ARM: integrator: convert to common clock
clk: add versatile ICST307 driver
ARM: integrator: put symbolic bus names on devices
ARM: u300: convert to common clock
clk: cache parent clocks only for muxes
clk: wm831x: Add initial WM831x clock driver
clk: Constify struct clk_init_data
clk: Add CLK_IS_BASIC flag to identify basic clocks
clk: Add support for rate table based dividers
clk: Add support for power of two type dividers
clk: mxs: imx28: decrease the frequency of ref_io1 for SSP2 and SSP3
clk: mxs: add clkdev lookup for pwm
clk: mxs: Fix the GPMI clock name
...
This adds support for three new SoC types:
* The mvebu platform includes Marvell's Armada XP and Armada 370 chips,
made by the mvebu business unit inside of Marvell. Since the same
group also made the older but similar platforms we call "orion5x",
"kirkwood", "mv78xx0" and "dove", we plan to move all of them into
the mach-mvebu directory in the future.
* socfpga is Altera's platform based on Cortex-A9 cores and a lot of
FPGA space. This is similar to the Xilinx zynq platform we already
support. The code is particularly clean, which is helped by the fact
that the hardware doesn't do much besides the parts that are
expected to get added in the FPGA.
* The OMAP subarchitecture gains support for the latest generation,
the OMAP5 based on the new Cortex-A15 core. Support is rather
rudimentary for now, but will be extended in the future.
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Merge tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull support for three new arm SoC types from Arnd Bergmann:
- The mvebu platform includes Marvell's Armada XP and Armada 370 chips,
made by the mvebu business unit inside of Marvell. Since the same
group also made the older but similar platforms we call "orion5x",
"kirkwood", "mv78xx0" and "dove", we plan to move all of them into
the mach-mvebu directory in the future.
- socfpga is Altera's platform based on Cortex-A9 cores and a lot of
FPGA space. This is similar to the Xilinx zynq platform we already
support. The code is particularly clean, which is helped by the fact
that the hardware doesn't do much besides the parts that are expected
to get added in the FPGA.
- The OMAP subarchitecture gains support for the latest generation, the
OMAP5 based on the new Cortex-A15 core. Support is rather
rudimentary for now, but will be extended in the future.
* tag 'newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (25 commits)
ARM: socfpga: initial support for Altera's SOCFPGA platform
arm: mvebu: generate DTBs for supported SoCs
ARM: mvebu: MPIC: read number of interrupts from control register
arm: mach-mvebu: add entry to MAINTAINERS
arm: mach-mvebu: add compilation/configuration change
arm: mach-mvebu: add defconfig
arm: mach-mvebu: add documentation for new device tree bindings
arm: mach-mvebu: add support for Armada 370 and Armada XP with DT
arm: mach-mvebu: add source files
arm: mach-mvebu: add header
clocksource: time-armada-370-xp: Marvell Armada 370/XP SoC timer driver
ARM: Kconfig update to support additional GPIOs in OMAP5
ARM: OMAP5: Add the build support
arm/dts: OMAP5: Add omap5 dts files
ARM: OMAP5: board-generic: Add device tree support
ARM: omap2+: board-generic: clean up the irq data from board file
ARM: OMAP5: Add SMP support
ARM: OMAP5: Add the WakeupGen IP updates
ARM: OMAP5: l3: Add l3 error handler support for omap5
ARM: OMAP5: gpmc: Update gpmc_init()
...
Conflicts:
Documentation/devicetree/bindings/arm/omap/omap.txt
arch/arm/mach-omap2/Makefile
drivers/clocksource/Kconfig
drivers/clocksource/Makefile
This is stuff that does not fit well into another category and in
particular is not related to a particular board. The largest part
in here is extending the am33xx support in the omap platform.
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Merge tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm soc-specific updates from Arnd Bergmann:
"This is stuff that does not fit well into another category and in
particular is not related to a particular board. The largest part in
here is extending the am33xx support in the omap platform."
Fix up trivial conflicts in arch/arm/mach-{imx/mach-mx35_3ds.c, tegra/Makefile}
* tag 'soc' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (74 commits)
ARM: LPC32xx: Add PWM support
ARM: LPC32xx: Add PWM clock
ARM: LPC32xx: Set system serial based on cpu unique id
ARM: vexpress: Config option for early printk console
ARM: vexpress: Add Device Tree for V2P-CA15_CA7 core tile
ARM: vexpress: Convert V2P-CA15 Device Tree to 64 bit addresses
ARM: vexpress: Add fixed regulator for SMSC
ARM: vexpress: Add missing SP804 interrupt in motherboard's DTS files
ARM: vexpress: Initial common clock support
ARM: SAMSUNG: Introduce Kconfig variable for Samsung custom clk API
ARM: EXYNOS: Add missing static storage class specifier in pmu.c file
ARM: EXYNOS: Make combiner_init function static
ARM: EXYNOS: Update HSOTG PHY clock setting for EXYNOS4X12
ARM: versatile: Make plat-versatile clock optional
ARM: vexpress: Check master site in daughterboard's sysctl operations
ARM: vexpress: remove automatic errata workaround selection
ARM: LPC32xx: Adjust to pl08x DMA interface changes
ARM: EXYNOS: Clear SYS_WDTRESET bit to use watchdog reset
ARM: imx: fix mx51 ehci setup errors
ARM: imx: make ehci power/oc polarities configurable
...
With commit 766e6a4ec6 (clk: add DT clock binding support),
compiling with OF && !COMMON_CLK is broken.
Reported-by: Alexandre Pereira da Silva <aletes.xgr@gmail.com>
Reported-by: Prashant Gaikwad <pgaikwad@nvidia.com>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The commit 766e6a4 (clk: add DT clock binding support) plugs device
tree clk lookup of_clk_get_by_name into clk_get, and fall on non-DT
lookup clk_get_sys if DT lookup fails.
The return check on of_clk_get_by_name takes (clk != NULL) as a
successful DT lookup. But it's not the case. For any system that
does not define clk lookup in device tree, ERR_PTR(-ENOENT) will be
returned, and consequently, all the client drivers calling clk_get
in their probe functions will fail to probe with error code -ENOENT
returned.
Fix the issue by checking of_clk_get_by_name return with !IS_ERR(clk),
and update of_clk_get and of_clk_get_by_name for !CONFIG_OF build
correspondingly.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Rob Herring <rob.herring@calxeda.com>
Tested-by: Marek Vasut <marex@denx.de>
Tested-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
sys_clk has multiple parents and selection of parent depends on sys_clk_ctrl
register bit no. 23:25, with following possibilities
0XX: pll1_clk
10X: sys_synth_clk
110: pll2_clk
111: pll3_clk
Out of several possibilities (h/w wise) to select same clock parent for
sys_clk, current clock implementation was considering just one value.
When bootloader programmed different (valid) value to select a clock
parent then Linux breaks.
Here, we try to include all possibilities which can lead to same
clock selection thus making Linux independent of bootloader selection
values.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
This patch is to fix typing mistake of clk enable register of i2c1 and
uart1.
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
The max limit of con_id is 16 and dev_id is 20. As of now for spear6xx, many clk
ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
pll3_48m -> pll3_
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The max limit of con_id is 16 and dev_id is 20. As of now for spear3xx, many clk
ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
ras_gen1_synth_gate_clk -> ras_syn1_gclk
ras_pll3_48m -> ras_pll3_
pll3_48m -> pll3_
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The max limit of con_id is 16 and dev_id is 20. As of now for spear1310, many
clk ids are exceeding this predefined limit.
This patch is intended to rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
gmac_phy -> phy_
gmii_125m_pad -> gmii_pad
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
The max limit of con_id is 16 and dev_id is 20. As of now for spear1340, many
clk ids are exceeding this predefined limit.
This patch rename clk ids like:
mux_clk -> _mclk
gate_clk -> _gclk
synth_clk -> syn_clk
gmac_phy -> phy_
gmii_125m_pad_ -> gmii_pad
Signed-off-by: Vipul Kumar Samar <vipulkumar.samar@st.com>
Signed-off-by: Shiraz Hashim <shiraz.hashim@st.com>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
This adds real clock support to Calxeda Highbank SOC using the common
clock infrastructure.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
[mturquette@linaro.org: fixed up invalid writes to const struct member]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Add support for DT "fixed-clock" binding to the common fixed rate clock
support.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
[Rob Herring] Rework and move into common clock infrastructure
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Based on work 1st by Ben Herrenschmidt and Jeremy Kerr, then by Grant
Likely, this patch adds support to clk_get to allow drivers to retrieve
clock data from the device tree.
Platforms scan for clocks in DT with of_clk_init and a match table, and
the register a provider through of_clk_add_provider. The provider's
clk_src_get function will be called when a device references the
provider's OF node for a clock reference.
v6 (Rob Herring):
- Return error values instead of NULL to match clock framework
expectations
v5 (Rob Herring):
- Move from drivers/of into common clock subsystem
- Squashed "dt/clock: add a simple provider get function" and
"dt/clock: add function to get parent clock name"
- Rebase to 3.4-rc1
- Drop CONFIG_OF_CLOCK and just use CONFIG_OF
- Add missing EXPORT_SYMBOL to various functions
- s/clock-output-name/clock-output-names/
- Define that fixed-clock binding is a single output
v4 (Rob Herring):
- Rework for common clk subsystem
- Add of_clk_get_parent_name function
v3: - Clarified documentation
v2: - fixed errant ';' causing compile error
- Editorial fixes from Shawn Guo
- merged in adding lookup to clkdev
- changed property names to match established convention. After
working with the binding a bit it really made more sense to follow the
lead of 'reg', 'gpios' and 'interrupts' by making the input simply
'clocks' & 'clock-names' instead of 'clock-input-*', and to only use
clock-output* for the producer nodes. (Sorry Shawn, this will mean
you need to change some code, but it should be trivial)
- Add ability to inherit clocks from parent nodes by using an empty
'clock-ranges' property. Useful for busses. I could use some feedback
on the new property name, 'clock-ranges' doesn't feel right to me.
Signed-off-by: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Reviewed-by: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <kernel@pengutronix.de>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This converts the Integrator platform to use common clock
and the ICST driver. Since from this point not all ARM
reference platforms use the clock, we define
CONFIG_PLAT_VERSATILE_CLOCK and select it for all platforms
except the Integrator.
Open issue: I could not use the .init_early() field of the
machine descriptor to initialize the clocks, but had to
move them to .init_irq(), so presumably .init_early() is
so early that common clock is not up, and .init_machine()
is too late since it's needed for the clockevent/clocksource
initialization. Any suggestions on how to solve this is
very welcome.
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: use 'select' instead of versatile Kconfig]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The ICST307 VCO clock has a shared driver in the ARM
architecture. This patch provides a wrapper into the common
clock framework so we can use the implementation in the
ARM architecture without duplicating the code until all
ARM platforms using this VCO are moved over. At that point
we can merge the driver from the ARM platform into the
generic file altogether.
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: removed versatile Kconfig]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This converts the U300 clock implementation over to use the common
struct clk and moves the implementation down into drivers/clk.
Since VCO isn't used in tree it was removed, it's not hard to
put it back in if need be.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
[mturquette@linaro.org: trivial Makefile conflict]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
caching parent clocks makes sense only when a clock has more
than one parent (mux clocks).
Avoid doing this for every other clock.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
[mturquette@linaro.org: removed extra parentheses]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The WM831x and WM832x series of PMICs contain a flexible clocking
subsystem intended to provide always on and system core clocks. It
features:
- A 32.768kHz crystal oscillator which can optionally be used to pass
through an externally generated clock.
- A FLL which can be clocked from either the 32.768kHz oscillator or
the CLKIN pin.
- A CLKOUT pin which can bring out either the oscillator or the FLL
output.
- The 32.768kHz clock can also optionally be brought out on the GPIO
pins of the device.
This driver fully supports the 32.768kHz oscillator and CLKOUT. The FLL
is supported only in AUTO mode, the full flexibility of the FLL cannot
currently be used.
Due to a lack of access to systems where the core SoC has been converted
to use the generic clock API this driver has been compile tested only.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Most platforms end up using a mix of basic clock types and
some which use clk_hw_foo struct for filling in custom platform
information when the clocks don't fit into basic types supported.
In platform code, its useful to know if a clock is using a basic
type or clk_hw_foo, which helps platforms know if they can
safely use to_clk_hw_foo to derive the clk_hw_foo pointer from
clk_hw.
Mark all basic clocks with a CLK_IS_BASIC flag.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Some divider clks do not have any obvious relationship
between the divider and the value programmed in the
register. For instance, say a value of 1 could signify divide
by 6 and a value of 2 could signify divide by 4 etc.
Also there are dividers where not all values possible
based on the bitfield width are valid. For instance
a 3 bit wide bitfield can be used to program a value
from 0 to 7. However its possible that only 0 to 4
are valid values.
All these cases need the platform code to pass a simple
table of divider/value tuple, so the framework knows
the exact value to be written based on the divider
calculation and can also do better error checking.
This patch adds support for such rate table based
dividers and as part of the support adds a new
registration function 'clk_register_divider_table()'
and a new macro for static definition
'DEFINE_CLK_DIVIDER_TABLE'.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Quite often dividers and the value programmed in the
register have a relation of 'power of two', something like
value div
0 1
1 2
2 4
3 8...
Add support for such dividers as part of clk-divider.
The clk-divider flag 'CLK_DIVIDER_POWER_OF_TWO' should be used
to define such clocks.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
SSP0 and SSP1 use ref_io0 which has decreased frequency. Expand
the frequency fix for ref_io1 to get SSP2 and SSP3 to work.
Signed-off-by: Lauri Hintsala <lauri.hintsala@bluegiga.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The below commit introduced a bug in __clk_set_parent()
which could cause it to *skip* the parent validation
which makes sure the parent passed to the api is a valid
one.
commit 7975059db5
Author: Rajendra Nayak <rnayak@ti.com>
Date: Wed Jun 6 14:41:31 2012 +0530
clk: Allow late cache allocation for clk->parents
This was identified by the following compiler warning..
drivers/clk/clk.c: In function '__clk_set_parent':
drivers/clk/clk.c:1083:5: warning: 'i' may be used uninitialized in this function [-Wuninitialized]
.. as reported by Marc Kleine-Budde.
There were various options discussed on how to fix this, one
being initing 'i' to clk->num_parents, but the below approach
was found to be more appropriate as it also makes the 'parent
validation' code simpler to read.
Reported-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
The correct name for the GPMI clock is 'gpmi-nand'.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Acked-by: Marek Vasut <marex@denx.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
rename the clock name from `8000c000.gpmi` to `8000c000.gpmi-nand`.
Signed-off-by: Huang Shijie <b32955@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The struct clk_lookup are marked as __initdata, resulting in being
removed from memory after the kernel finished booting. However this
leads to a NULL pointer de-ref if loading a module which uses clk_get.
This patch removes the __initdata from the struct clk_lookup.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The definition of clocks ref_io0 and ref_io1 were inverted. It causes
a mmc regression on some boards right away. Fix the regression by
correcting the ref_io clock definition.
Reported-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
clk_change_rate() is accessing parent's rate without checking
if the parent exists at all. In case of root clocks this will
cause NULL pointer dereference.
This patch follows what clk_calc_new_rates() does in such
situation.
Signed-off-by: Pawel Moll <pawel.moll@arm.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
Parent clocks for muxes are cached in clk->parents to
avoid frequent lookups, however the cache allocation happens
only during clock registeration and later clk_set_parent()
assumes a cache space available and allocated.
This is not entirely true for platforms which do early clock
registerations wherein the cache allocation using kzalloc
could fail during clock registeration.
Allow cache allocation to happen later as part of clk_set_parent()
to help such cases and avoid crashes assuming a cache being
available.
While here also replace existing kmalloc() with kzalloc()
in the file.
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: stable@kernel.org
viresh.kumar@st.com email-id doesn't exist anymore as I have left the
company. Replace ST's id with viresh.linux@gmail.com.
It also updates .mailmap file to fix address for 'git shortlog'
Signed-off-by: Viresh Kumar <viresh.linux@gmail.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
Remove more custom stuff by simply converting the Nomadik machine
to use generic clocks and move the driver to drivers/clk.
Acked-by: Arnd Bergmann <arnd@arndb.de>
Cc: Mike Turquette <mturquette@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This adds support for the spear13xx platform, which has first been under
review a long time ago and finally been completed after generic spear
work has gone into the clock, dt and pinctrl branches.
Also a number of updates for the samsung socs are part of this branch.
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Merge tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc: soc specific changes (part 2) from Olof Johansson:
"This adds support for the spear13xx platform, which has first been
under review a long time ago and finally been completed after generic
spear work has gone into the clock, dt and pinctrl branches.
Also a number of updates for the samsung socs are part of this branch."
Fix up trivial conflicts in drivers/gpio/gpio-samsung.c that look much
worse than they are: the exonys5 init code was refactored in commit
fd454997d6 ("gpio: samsung: refactor gpiolib init for exynos4/5"), and
then commit f10590c983 ("ARM: EXYNOS: add GPC4 bank instance") added a
new gpio chip define and did tiny updates to the init code.
So the conflict diff looks like hell, but it's actually a fairly simple
change.
* tag 'soc2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (34 commits)
ARM: exynos: fix building with CONFIG_OF disabled
ARM: EXYNOS: Add AUXDATA for i2c controllers
ARM: dts: Update device tree source files for EXYNOS5250
ARM: EXYNOS: Add device tree support for interrupt combiner
ARM: EXYNOS: Add irq_domain support for interrupt combiner
ARM: EXYNOS: Remove a new bus_type instance for EXYNOS5
ARM: EXYNOS: update irqs for EXYNOS5250 SoC
ARM: EXYNOS: Add pre-divider and fout mux clocks for bpll and mpll
ARM: EXYNOS: add GPC4 bank instance
ARM: EXYNOS: Redefine IRQ_MCT_L0,1 definition
ARM: EXYNOS: Modify the GIC physical address for static io-mapping
ARM: EXYNOS: Add watchdog timer clock instance
pinctrl: SPEAr1310: Fix pin numbers for clcd_high_res
SPEAr: Update MAINTAINERS and Documentation
SPEAr13xx: Add defconfig
SPEAr13xx: Add compilation support
SPEAr13xx: Add dts and dtsi files
pinctrl: Add SPEAr13xx pinctrl drivers
pinctrl: SPEAr: Create macro for declaring GPIO PINS
SPEAr13xx: Add common clock framework support
...
These continue the device tree work from part 1, this set is for the
tegra, mxs and imx platforms, all of which have dependencies on clock
or pinctrl changes submitted earlier.
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Merge tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull arm-soc device tree conversions (part 2) from Olof Johansson:
"These continue the device tree work from part 1, this set is for the
tegra, mxs and imx platforms, all of which have dependencies on clock
or pinctrl changes submitted earlier."
Fix up trivial conflicts due to nearby changes in
drivers/{gpio/gpio,i2c/busses/i2c}-mxs.c
* tag 'dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (73 commits)
ARM: dt: tegra: invert status=disable vs status=okay
ARM: dt: tegra: consistent basic property ordering
ARM: dt: tegra: sort nodes based on bus order
ARM: dt: tegra: remove duplicate device_type property
ARM: dt: tegra: consistenly use lower-case for hex constants
ARM: dt: tegra: format regs properties consistently
ARM: dt: tegra: gpio comment cleanup
ARM: dt: tegra: remove unnecessary unit addresses
ARM: dt: tegra: whitespace cleanup
ARM: dt: tegra cardhu: fix typo in SDHCI node name
ARM: dt: tegra: cardhu: register core regulator tps62361
ARM: dt: tegra30.dtsi: Add SMMU node
ARM: dt: tegra20.dtsi: Add GART node
ARM: dt: tegra30.dtsi: Add Memory Controller(MC) nodes
ARM: dt: tegra20.dtsi: Add Memory Controller(MC) nodes
ARM: dt: tegra: Add device tree support for AHB
ARM: dts: enable audio support for imx28-evk
ARM: dts: enable i2c device for imx28-evk
i2c: mxs: add device tree probe support
ARM: dts: enable mmc for imx28-evk
...
* 'clk-next' of git://git.linaro.org/people/mturquette/linux:
clk: Fix CLK_SET_RATE_GATE flag validation in clk_set_rate().
clk: Provide dummy clk_unregister()
ARM: Kirkwood: Replace clock gating
ARM: Orion: Audio: Add clk/clkdev support
ARM: Orion: PCIE: Add support for clk
ARM: Orion: XOR: Add support for clk
ARM: Orion: CESA: Add support for clk
ARM: Orion: SDIO: Add support for clk.
ARM: Orion: NAND: Add support for clk, if there is one.
ARM: Orion: EHCI: Add support for enabling clocks
ARM: Orion: SATA: Add per channel clk/clkdev support.
ARM: Orion: UART: Get the clock rate via clk_get_rate().
ARM: Orion: WDT: Add clk/clkdev support
ARM: Orion: Eth: Add clk/clkdev support.
ARM: Orion: SPI: Add clk/clkdev support.
ARM: Orion: Add clocks using the generic clk infrastructure.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The clk_set_rate() code shouldn't check the clock's enable count when
validating CLK_SET_RATE_GATE flag since the enable count could change after
the validation. Similar to clk_set_parent(), it should instead check the
prepare count. The prepare count should go to zero only when the end user
expects the clock to not be enabled in the future. Since the code already
grabs the prepare count before validation, it's not possible for prepare
count to change after validation and by association not possible for a well
behaving end user to enable the clock while the set rate is in progress.
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
Reviewed-by: Richard Zhao <richard.zhao@freescale.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
While there's no actual implementation behind it having the call to use
in drivers makes them feel neater from a driver author point of view. An
actual implementation can wait for someone who needs to use the function
in a real system.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[mturquette@linaro.org: void return type instead of int -EINVAL]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch adds SPEAr1310 and SPEAr1340's clock framework support. It is based
on earlier support for SPEAr3xx family.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@ti.com>
The register HW_SSP_VERSION is broken for ssp version detection,
as the address of the register is different between imx23 and imx28.
Let's use platform_device_id to detect the device, so that the use
of cpu_is_xxx can be removed.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Chris Ball <cjb@laptop.org>
SPEAr SoCs used its own clock framework since now. From now on they will move to
use common clock framework.
This patch updates existing SPEAr machine support to adapt for common clock
framework.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Arnd Bergmann <arnd@arndb.de>
All SPEAr SoC's contain GPT Synthesizers. Their Fout is derived from
following equations:
Fout= Fin/((2 ^ (N+1)) * (M+1))
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
All SPEAr SoC's contain Fractional Synthesizers. Their Fout is derived from
following equations:
Fout = Fin / (2 * div) (division factor)
div is 17 bits:-
0-13 (fractional part)
14-16 (integer part)
div is (16-14 bits).(13-0 bits) (in binary)
Fout = Fin/(2 * div)
Fout = ((Fin / 10000)/(2 * div)) * 10000
Fout = (2^14 * (Fin / 10000)/(2^14 * (2 * div))) * 10000
Fout = (((Fin / 10000) << 14)/(2 * (div << 14))) * 10000
div << 14 is simply 17 bit value written at register.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
All SPEAr SoC's contain Auxiliary Synthesizers. Their Fout is derived based on
values of eq, x and y.
Fout from synthesizer can be given from two equations:
Fout1 = (Fin * X/Y)/2 EQ1
Fout2 = Fin * X/Y EQ2
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
All SPEAr SoC's contain PLLs. Their Fout is derived based on following equations
- In normal mode
vco = (2 * M[15:8] * Fin)/N
- In Dithered mode
vco = (2 * M[15:0] * Fin)/(256 * N)
pll_rate = vco/2^p
vco and pll are very closely bound to each other,
"vco needs to program: mode, m & n" and "pll needs to program p",
both share common enable/disable logic and registers.
This patch adds in support for this type of clock.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Reviewed-by: Mike Turquette <mturquette@linaro.org>
Rewrite mxs_dma_is_apbh and mxs_dma_is_apbx in order to support
other SoCs like imx6q and reform the platform_device_id for the
better further dt support.
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Huang Shijie <b32955@freescale.com>
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Acked-by: Vinod Koul <vinod.koul@intel.com>
It adds initial device tree support for imx23-evk board, and only
serial console is enabled.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
This patch includes basic dt support which can boot via nfs rootfs.
Signed-off-by: Dong Aisheng <dong.aisheng@linaro.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Acked-by: Marek Vasut <marex@denx.de>
Shawn Guo <shawn.guo@linaro.org> writes:
mxs common clk porting for v3.5. It depends on the following two branches.
[1] git://git.linaro.org/people/mturquette/linux.git clk-next
[2] http://ftp.arm.linux.org.uk/pub/linux/arm/kernel/git-cur/linux-arm.git clkdev
As the mxs device tree conversion will constantly touch clock files,
to save the conflicts, the updated mxs/dt branch coming later will
based on this pull-request.
* 'clk/mxs' of git://git.linaro.org/people/shawnguo/linux-2.6:
ARM: mxs: remove now unused timer_clk argument from mxs_timer_init
ARM: mxs: remove old clock support
ARM: mxs: switch to common clk framework
ARM: mxs: change the lookup name for fec phy clock
ARM: mxs: request clock for timer
clk: mxs: add clock support for imx28
clk: mxs: add clock support for imx23
clk: mxs: add mxs specific clocks
Includes an update to Linux 3.4-rc6
Conflicts:
drivers/clk/Makefile
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Having fixed factors/dividers in hardware is a common pattern, so
add a basic clock type doing this. It basically describes a fixed
factor clock using a nominator and a denominator.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
[mturquette@linaro.org: constify parent_names in static init macro]
[mturquette@linaro.org: copy/paste bug from mux in static init macro]
[mturquette@linaro.org: fix error handling in clk_register_fixed_factor]
[mturquette@linaro.org: improve division accuracy; thanks to Saravana]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The original conversion to struct clk_hw_init failed to add the pointer
assignment in clk_register_mux.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Reported-by: Sascha Hauer <s.hauer@pengutronix.de>
Exposing this option generates confusion and incorrect behavior for
single-image builds across platforms. Enable this behavior permanently.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Saravana Kannan <skannan@codeaurora.org>
Patch 'clk: always pass parent_rate into .round_rate' made a subtle
change to the semantics of .round_rate. It is now expected for the
parent's rate to always be passed in, simplifying the implemenation of
various .round_rate callback definitions.
However the patch also introduced a bug in clk_calc_new_rates whereby a
clock without the CLK_SET_RATE_PARENT flag set could still propagate a
rate change up to a parent clock if the the .round_rate callback
modified the &best_parent_rate value in any way.
This patch fixes the issue at the framework level (in
clk_calc_new_rates) by specifically handling the case where the
CLK_SET_RATE_PARENT flag is not set.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
With old mxs clock support removed, the timer_clk argument of
mxs_timer_init is unused now, so remove it.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
The common clock framework allocates clocks dynamically. Provide a
set of helpers to streamline the clkdev registration of the clock
lookups to avoid repetitive code sequences.
Reviewed-by: Viresh Kumar <viresh.kumar@st.com>
Tested-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This is well documented but isn't implemented. clk_set_rate() must check if
flags have CLK_SET_RATE_GATE bit set and is enabled too.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Create a struct clk_init_data to hold all data that needs to be passed from
the platfrom specific driver to the common clock framework during clock
registration. Add a pointer to this struct inside clk_hw.
This has several advantages:
* Completely hides struct clk from many clock platform drivers and static
clock initialization code that don't care for static initialization of
the struct clks.
* For platforms that want to do complete static initialization, it removed
the need to directly mess with the struct clk's fields while still
allowing to statically allocate struct clk. This keeps the code more
future proof even if they include clk-private.h.
* Simplifies the generic clk_register() function and allows adding optional
fields in the future without modifying the function signature.
* Simplifies the static initialization of clocks on all platforms by
removing the need for forward delcarations or convoluted macros.
Signed-off-by: Saravana Kannan <skannan@codeaurora.org>
[mturquette@linaro.org: kept DEFINE_CLK_* macros and __clk_init]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Cc: Andrew Lunn <andrew@lunn.ch>
Cc: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Using the common clock infrastructure without the common clkdev code makes
little sense, so select CLKDEV_LOOKUP for COMMON_CLK.
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
if (!clk->ops->round_rate && (clk->flags & CLK_SET_RATE_PARENT)) is true, then
we don't need to set clk->new_rate here, as we will call clk_calc_subtree()
afterwards and it also sets clk->new_rate.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch tries to remove duplicate code for clk_gate clocks. This creates
another routine clk_gate_endisable() which will take care of enable/disable
clock with knowledge of CLK_GATE_SET_TO_DISABLE flag.
It works on following logic:
For enabling clock, enable = 1
set2dis = 1 -> clear bit -> set = 0
set2dis = 0 -> set bit -> set = 1
For disabling clock, enable = 0
set2dis = 1 -> set bit -> set = 1
set2dis = 0 -> clear bit -> set = 0
So, result is always: enable xor set2dis.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Need to propagate round_rate call for the clk that has no .round_rate
operation but with flag CLK_SET_RATE_PARENT set.
For example, clk_mux is a clk with no .round_rate operation. However,
it could likely be in a clk_set_rate propagation path, saying it has
parent clk who has .round_rate and .set_rate operations.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
For most of .set_rate implementation, parent_rate will be used, so just
like passing parent_rate into .recalc_rate, let's pass parent_rate into
.set_rate too.
It also updates the kernel doc for .set_rate ops.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The parent_rate will likely be used by most .round_rate implementation
no matter whether flag CLK_SET_RATE_PARENT is set or not, so let's
always pass parent_rate into .round_rate.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch is the basic clk version of 'clk: core: copy parent_names &
return error codes'.
The registration functions are changed to allow the core code to copy
the array of strings and allow platforms to declare those arrays as
__initdata.
This patch also converts all of the basic clk registration functions to
return error codes which better aligns them with the existing clk.h api.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
This patch cleans up clk_register and solves a few bugs by teaching
clk_register and __clk_init to return error codes (instead of just NULL)
to better align with the existing clk.h api.
Along with that change this patch also introduces a new behavior whereby
clk_register copies the parent_names array, thus allowing platforms to
declare their parent_names arrays as __initdata.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Drivers should be able to declare their arrays of parent names as const
so the APIs need to accept const arguments.
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
[mturquette@linaro.org: constified gate]
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Most users of clk_get_rate() actually assume a non zero
return value as a valid rate returned. Returing -EINVAL
might confuse such users, so make it instead return zero
on error.
Besides the return value of clk_get_rate seems to be
'unsigned long'.
Signed-off-by: Rajendra nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
The clk_ops of basic clks should have "const" to match the definition
in "struct clk" and clk_register prototype.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
It makes no sense to have EXPORT_SYMBOL_GPL on static functions.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Change clk_register_mux to use kzalloc, just like what all other basic
clk registration functions do.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Documentation/clk.txt has some handsome ASCII art outlining which
clk_ops are mandatory for a given clock, given the capability of the
hardware. Enforce those mandates with sanity checks in __clk_init.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
It is possible to call clk_set_rate on a clock with a NULL parent. One
such example is an adjustable-rate root clock. Ensure that
clk_calc_new_rates does not dereference parent without checking first
and also handle the corner cases gracefully.
Reported-by: Rajendra Nayak <rnayak@ti.com>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Some static inline dummy functions were left over from before the clock
core was consolidated from several C files down to one. Remove them.
Reported-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Remove old and misleading documentation from the previous clk_set_rate
implementaion.
Reported-by: Shawn Guo <shawn.guo@linaro.org>
Signed-off-by: Mike Turquette <mturquette@linaro.org>
clk_find must return as soon as it gets the correct clock. Currently it check
all clocks until it found a lookup with both dev_id and con_id matching.
If only one of them is passed, then we don't actually need to wait for both of
them to match. We can quit as soon as the requested id (dev_id or con_id)
matches.
Signed-off-by: Viresh Kumar <viresh.kumar@st.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Allow clk API users to simplify their cleanup paths by providing a
managed version of clk_get() and clk_put().
Signed-off-by: Mark Brown <broonie@opensource.wolfsonmicro.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
All platforms that use the common clk infrastructure should select
COMMON_CLK from platform code, and on all other platforms, it must
not be enabled, so there is no point making the option visible to
users, and when it is visible, we break randconfig builds.
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
Many platforms support simple gateable clocks, fixed-rate clocks,
adjustable divider clocks and multi-parent multiplexer clocks.
This patch introduces basic clock types for the above-mentioned hardware
which share some common characteristics.
Based on original work by Jeremy Kerr and contribution by Jamie Iles.
Dividers and multiplexor clocks originally contributed by Richard Zhao &
Sascha Hauer.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <rob.herring@calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Jamie Iles <jamie@jamieiles.com>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The common clock framework defines a common struct clk useful across
most platforms as well as an implementation of the clk api that drivers
can use safely for managing clocks.
The net result is consolidation of many different struct clk definitions
and platform-specific clock framework implementations.
This patch introduces the common struct clk, struct clk_ops and an
implementation of the well-known clock api in include/clk/clk.h.
Platforms may define their own hardware-specific clock structure and
their own clock operation callbacks, so long as it wraps an instance of
struct clk_hw.
See Documentation/clk.txt for more details.
This patch is based on the work of Jeremy Kerr, which in turn was based
on the work of Ben Herrenschmidt.
Signed-off-by: Mike Turquette <mturquette@linaro.org>
Signed-off-by: Mike Turquette <mturquette@ti.com>
Reviewed-by: Thomas Gleixner <tglx@linutronix.de>
Tested-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Rob Herring <rob.herring <at> calxeda.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Jeremy Kerr <jeremy.kerr@canonical.com>
Cc: Arnd Bergman <arnd.bergmann@linaro.org>
Cc: Paul Walmsley <paul@pwsan.com>
Cc: Shawn Guo <shawn.guo@freescale.com>
Cc: Sascha Hauer <s.hauer@pengutronix.de>
Cc: Richard Zhao <richard.zhao@linaro.org>
Cc: Saravana Kannan <skannan@codeaurora.org>
Cc: Magnus Damm <magnus.damm@gmail.com>
Cc: Mark Brown <broonie@opensource.wolfsonmicro.com>
Cc: Linus Walleij <linus.walleij@stericsson.com>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Amit Kucheria <amit.kucheria@linaro.org>
Cc: Deepak Saxena <dsaxena@linaro.org>
Cc: Grant Likely <grant.likely@secretlab.ca>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
The commit 40d3e0f (clk: provide prepare/unprepare functions) provides
the config option HAVE_CLK_PREPARE for platforms that have
prepare/unprepare implementation to select. This patch adds the option
into drivers/clk/Kconfig, so that it can be actually selected.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Cc: Russell King <rmk+kernel@arm.linux.org.uk>
Now most of ARM machines has the alsmot same __clk_get/put() macro
So place it at the arch/arm/include/asm/clkdev.h and remove the reduntant header files
But some machines don't have the same form as above. It can use the machince specific clkdev file by HAVE_MACH_CLKDEV config
Now there are only 3 caese.
1) define the clk structure with clkdev macro => Need to move clk structure to proper header file
arch/arm/mach-versatile/include/mach/clkdev.h
arch/arm/mach-realview/include/mach/clkdev.h
arch/arm/mach-vexpress/include/mach/clkdev.h
arch/arm/mach-integrator/include/mach/clkdev.h
2) export the __clk_get/put function at clock.c
arch/arm/mach-shmobile/include/mach/clkdev.h
3) demuxing the clk source
arch/arm/mach-u300/include/mach/clkdev.h
Acked-by: Viresh Kumar <viresh.kumar@st.com>
Acked-by: H Hartley Sweeten <hsweeten@visionengravers.com>
Acked-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Signed-off-by: Kyungmin Park <kyungmin.park@samsung.com>
clkdev may incorrectly cause a clkdev entry with a NULL clk to return
-ENOENT. This is not the intention of this code; -ENOENT should only
be returned if the clock entry can not be found in the table. Fix
this.
Reported-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
factorise some generic infrastructure to assist looking up struct clks
for the ARM & SH architecture.
as the code is identical at 99%
put the arch specific code for allocation as example in asm/clkdev.h
Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj@jcrosoft.com>
Acked-by: Paul Mundt <lethal@linux-sh.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Peter De Schrijver