Commit Graph

295 Commits

Author SHA1 Message Date
Akshay Joshi 0206e353a0 Drivers: i915: Fix all space related issues.
Various issues involved with the space character were generating
warnings in the checkpatch.pl file. This patch removes most of those
warnings.

Signed-off-by: Akshay Joshi <me@akshayjoshi.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-09-19 18:01:47 -07:00
Keith Packard c3613de92e drm/i915: Can't do accurate vblank timestamps with UMS
Disable this feature when KMS is not running by setting the
driver->get_vblank_timestamp function pointer to NULL.

Signed-off-by: Keith Packard <keithp@keithp.com>
Tested-by: Justin P. Mattock <justinmattock@gmail.com>
2011-08-15 12:10:26 -07:00
Keith Packard 2c1756b12e Merge branch 'drm-intel-fixes' into drm-intel-next 2011-07-28 16:30:41 -07:00
Keith Packard 40ee3381dd drm/i915: Fixup for 'Hold mode_config->mutex during hotplug'
drm_helper_hpd_irq_event queues another work proc to go and deliver
the user-space event, and that function also wants to hold the config
mutex, so we shouldn't hold the mutex across the
drm_helper_hpd_irq_event call.

Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-28 15:41:51 -07:00
Keith Packard 887a82ee80 Merge branch 'drm-intel-fixes' into drm-intel-next 2011-07-25 14:57:41 -07:00
Keith Packard a65e34c79c drm/i915: Hold mode_config->mutex during hotplug processing
Hotplug detection is a mode setting operation and must hold the
struct_mutex or risk colliding with other mode setting operations.

In particular, the display port hotplug function attempts to re-train
the link if the monitor is supposed to be running when plugged back
in. If that happens while mode setting is underway, the link will get
scrambled, leaving it in an inconsistent state.

This is a special case -- usually the driver mode setting entry points
are covered by the upper level DRM code, but in this case the function
is invoked as a work function not under the control of DRM.

Signed-off-by: Keith Packard <keithp@keithp.com>
Cc: stable@kernel.org
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2011-07-25 14:54:22 -07:00
Keith Packard a7f08958d7 Merge branch 'drm-intel-fixes' into drm-intel-next 2011-07-01 13:33:49 -07:00
Jesse Barnes 2b1ecb7337 drm/i915: apply HWSTAM writes to Ivy Bridge as well
In an attempt to fix 38862 and 38863.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-07-01 13:28:53 -07:00
Keith Packard bee4d4acf5 Merge branch 'drm-intel-fixes' into drm-intel-next 2011-06-29 20:38:41 -07:00
Jesse Barnes f71d4af4cd drm/i915: move IRQ function table init to i915_irq.c
This lets us make the various IRQ functions static and helps avoid
problems like the one fixed in "drm/i915: Use chipset-specific irq
installers" where one of the exported functions was called rather than
the chipset specific version.

This also fixes a UMS-mode bug -- the correct irq functions for IRL
and later chips were only getting loaded in the KMS path.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-29 20:37:22 -07:00
Ben Widawsky 3e0dc6b01f drm/i915: hangcheck disable parameter
Provide a parameter to disable hanghcheck. This is useful mostly for
developers trying to debug known problems, and probably should not be
touched by normal users.

Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-29 10:32:08 -07:00
Chris Wilson ec6a890dfe drm/i915: Apply HWSTAM workaround for BSD ring on SandyBridge
...we need to apply exactly the same workaround for missing interrupts
from BSD as for the BLT ring, apparently.

See also commit 498e720b96
(drm/i915: Fix gen6 (SNB) missed BLT ring interrupts).

Reported-and-tested-by: nkalkhof@web.de
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=38529
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-21 10:57:23 -07:00
Daniel J Blueman 498e720b96 drm/i915: Fix gen6 (SNB) missed BLT ring interrupts.
The failure appeared in dmesg as:

[drm:i915_hangcheck_ring_idle] *ERROR* Hangcheck timer elapsed... blt
ring idle [waiting on 35064155, at 35064155], missed IRQ?

This works around that problem on by making the blitter command
streamer write interrupt state to the Hardware Status Page when a
MI_USER_INTERRUPT command is decoded, which appears to force the seqno
out to memory before the interrupt happens.

v1->v2: Moved to prior interrupt handler installation and RMW flags as
per feedback.
v2->v3: Removed RMW of flags (by anholt)

Cc: stable@kernel.org
Signed-off-by: Daniel J Blueman <daniel.blueman@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk> [v1]
Tested-by: Eric Anholt <eric@anholt.net> [v1,v3]
	   (incidence of the bug with a testcase went from avg 2/1000 to
	   0/12651 in the latest test run (plus more for v1))
Tested-by: Kenneth Graunke <kenneth@whitecape.org> [v1]
Tested-by: Robert Hooker <robert.hooker@canonical.com> [v1]
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=33394
Signed-off-by: Dave Airlie <airlied@redhat.com>
2011-06-18 08:25:16 +10:00
Dan Carpenter f6b07f45e2 drm/i915: fix if statement in ivybridge irq handler
The extra semicolon was not intended.

Signed-off-by: Dan Carpenter <error27@gmail.com>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-06-04 10:40:17 -07:00
Jesse Barnes 9e3c256d7d drm/i915: initialize gen6 rps work queue on Sandy Bridge and Ivy Bridge
It's not used on Ironlake, but is used on later generations, so make
sure it exists before we try to use it in the interrupt handlers.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-18 15:14:39 -07:00
Jesse Barnes b1f14ad01a drm/i915: interrupt & vblank support for Ivy Bridge
Add new interrupt handling functions for Ivy Bridge.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:09:52 -07:00
Jesse Barnes f796cf8f51 drm/i915: split enable/disable vblank code into chipset specific functions
This makes the Ironlake+ code trivial and generally simplifies things.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:03:10 -07:00
Jesse Barnes 4697995b98 drm/i915: split irq handling into per-chipset functions
Set the IRQ handling functions in driver load so they'll just be used
directly, rather than branching over most of the code in the chipset
functions.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Keith Packard <keithp@keithp.com>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-13 17:02:44 -07:00
Ben Widawsky 4912d04193 drm/i915: move gen6 rps handling to workqueue
The render P-state handling code requires reading from a GT register.
This means that FORCEWAKE must be written to, a resource which is shared
and should be protected by struct_mutex. Hence we can not manipulate
that register from within the interrupt handling and so must delegate
the task to a workqueue.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:47 -07:00
Ben Widawsky fcca792629 drm/i915: reference counted forcewake
Provide a reference count to track the forcewake state of the GPU and
give a safe mechanism for userspace to wake the GT. This also potentially
saves a UC read if the GT is known to be awake already.

The reference count is atomic, but the register access and hardware wake
sequence is protected by struct_mutex.

Signed-off-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-05-10 13:56:46 -07:00
Chris Wilson 93dfb40cd8 drm/i915: Rename agp_type to cache_level
... to clarify just how we use it inside the driver and remove the
confusion of the poorly matching agp_type names. We still need to
translate through agp_type for interface into the fake AGP driver.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:56:43 -07:00
Chris Wilson b259f6730c drm/i915: Move the irq wait queue initialisation into the ring init
Required so that we don't obliterate the queue if initialising the
rings after the global IRQ handler is installed.

[Jesse, you recently looked at refactoring the IRQ installation
routines, does moving the initialisation of ring buffer data structures away
from that routine make sense in your grand scheme?]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Jesse Barnes <jbarnes@virtuousgeek.org>
Reviewed-by: Ben Widawsky <ben@bwidawsk.net>
Signed-off-by: Keith Packard <keithp@keithp.com>
2011-05-10 13:19:12 -07:00
Chris Wilson 8692d00e99 drm/i915: Replace vblank PM QoS with "Interrupt-Based AGPBUSY#"
I stumbled over this magic bit in the gen3 INSTPM:

Bit11 Interrupt-Based AGPBUSY# Enable:

‘0’ = Pending GMCH interrupts will not cause AGPBUSY# assertion.
‘1’ = Pending GMCH interrupts will cause AGPBUSY# assertion and hence
      can cause the CPU to exit C3.  There is no suppression of cacheable
      writes.

Note that in either case in C3 the interrupts are not lost. They will be
forwarded to the ICH when the GMCH is out of C3.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Tested-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Cc: stable@kernel.org
2011-03-01 17:33:38 +00:00
Chris Wilson 60c8bdf64a Revert "drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU"
Using PM latency request turns out to be very fragile and only works for
some systems, depending upon the ACPI implementation. However, I've
stumbled across a promising bit in INSTPM: "Interrupt-Based AGPBUSY#".

This reverts commit b0b544cd37.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01 17:33:22 +00:00
Chris Wilson 5d9faa16a7 drm/i915: Silence an innocuous compiler warning for an unused variable
drivers/gpu/drm/i915/i915_irq.c: In function ‘ironlake_irq_postinstall’:
drivers/gpu/drm/i915/i915_irq.c:1618: warning: unused variable ‘pipe’

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-03-01 16:00:30 +00:00
Chris Wilson 9035a97a32 Merge branch 'drm-intel-fixes' into drm-intel-next
Grab the latest stabilisation bits from -fixes and some suspend and
resume fixes from linus.

Conflicts:
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/i915/i915_irq.c
2011-02-16 09:44:30 +00:00
Jesse Barnes e67189ab9a drm/i915: don't enable FDI & transcoder interrupts after all
We can enable some safely, but FDI and transcoder interrupts can occur
and block other interrupts from being detected (like port hotplug
events).  So keep them disabled by default (they can be re-enabled for
debugging display bringup, but should generally be off).

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-16 09:25:18 +00:00
Jesse Barnes 9db4a9c7b2 drm/i915: cleanup per-pipe reg usage
We had some conversions over to the _PIPE macros, but didn't get
everything.  So hide the per-pipe regs with an _ (still used in a few
places for legacy) and add a few _PIPE based macros, then make sure
everyone uses them.

[update: remove usage of non-existent no-op macro]
[update 2: keep modesetting suspend/resume code, update to new reg names]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[ickle: stylistic cleanups for checkpatch and taste]
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 21:17:15 +00:00
Chris Wilson db53a30261 drm/i915: Refine tracepoints
A lot of minor tweaks to fix the tracepoints, improve the outputting for
ftrace, and to generally make the tracepoints useful again. It is a start
and enough to begin identifying performance issues and gaps in our
coverage.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 14:59:18 +00:00
Chris Wilson b6f7833b97 drm/i915: Include 'i915_error_state' hint for when the GPU catches fire
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-02-07 12:04:51 +00:00
Chris Wilson 4a1dc3ff68 Merge branch 'drm-intel-fixes' into drm-intel-next
Merge resume fixes from -fixes and an important fix for SDVO GMBUS.
2011-02-01 08:49:14 +00:00
Chris Wilson 78c6e170ba drm/i915: Suppress spurious vblank interrupts
Hugh Dickins found that characters in xterm were going missing and oft
delayed. Being the curious type, he managed to associate this with the
new high-precision vblank patches; disabling these he found, restored
the orderliness of his characters.

The oddness begins when one realised that Hugh was not using vblanks at
all on his system (fvwm and some xterms). Instead, all he had to go on
were warning of a pipe underrun, curiously enough at around 60Hz. He
poked and found that in addition to the underrun warning, the hardware
was flagging the start of a new frame, a vblank, which in turn was
kicking off the pending vblank processing code.

There is little we can do for the underruns on Hugh's machine, a
Crestline [965GM], which must have its FIFO watermarks set to 8.
However, we do not need to process the vblank if we know that they are
disabled...

Reported-by: Hugh Dickins <hughd@google.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-31 12:38:47 +00:00
Chris Wilson e2f973d58e drm/i915: Record all error ringbuffers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-28 11:21:37 +00:00
Chris Wilson bdd92c9ad2 Merge branch 'drm-intel-fixes' into drm-intel-next
Merge important suspend and resume regression fixes and resolve the
small conflict.

Conflicts:
	drivers/gpu/drm/i915/i915_dma.c
2011-01-24 23:45:32 +00:00
Chris Wilson 8e934dbf26 drm/i915: Prevent uninitialised reads during error state capture
error_bo and pinned_bo could be used uninitialised if there were no
active buffers.

Caught by kmemcheck.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24 18:28:29 +00:00
Chris Wilson 5a9a8d1a99 drm/i915: Handle the no-interrupts case for UMS by polling
If the driver calls into the kernel to wait for a breadcrumb to pass,
but hasn't enabled interrupts, fallback to polling the breadcrumb value.

Reported-by: Chris Clayton <chris2553@googlemail.com>
Tested-by: Chris Clayton <chris2553@googlemail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24 18:26:31 +00:00
Chris Wilson 4041b85323 drm/i915: Increase the amount of defense before computing vblank timestamps
Reported-by: Chris Clayton <chris2553@googlemail.com>
Tested-by: Chris Clayton <chris2553@googlemail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-24 18:26:30 +00:00
Chris Wilson a37f2f87ed drm/i915: Remove unused code: i915_enable_interrupt()
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-23 12:22:37 +00:00
Chris Wilson 475553de2f drm/i915: Don't kick-off hangcheck after a DRI interrupt
Hangcheck and error recovery is only used by GEM.

Reported-by: Herbert Xu <herbert@gondor.apana.org.au>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-20 11:21:16 +00:00
Chris Wilson b0b544cd37 drm/i915: Use PM QoS to prevent C-State starvation of gen3 GPU
945 class hardware has an interesting quirk in which the vblank
interrupt is not raised if the CPU is in a low power state. (We also
suspect that the memory bus is clocked to the CPU/c-state and not the
GPU so there are secondary starvation issues.) In order to prevent the
most obvious issue of the low of the vblank interrupt (stuttering
compositing that only updates when the mouse is moving) is to install a
PM QoS request to prevent low c-states whilst the GPU is active.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-19 12:38:26 +00:00
Chris Wilson c37d9a5de9 drm/i915: Fix error handler to capture the first batch after the seqno
Whilst we had no older batches on the active list, everything was fine.
However, if the GPU is free running and the requests are only being
reaped by the periodic retirer, than the current seqno may not be at the
start of the list. In this case we need to select the first batch after
the last seqno written by the gpu and not inclusive of the seqno.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-13 16:06:05 +00:00
Chris Wilson a779e5abda drm/i915: Record AGP memory type upon error
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 22:16:56 +00:00
Chris Wilson bcfb2e2858 drm/i915: Record the error batchbuffer on each ring
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:44:55 +00:00
Jesse Barnes 776ad8062b drm/i915: detect & report PCH display error interrupts
FDI and the transcoders can fail for various reasons, so detect those
conditions and report on them.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:44:01 +00:00
Chris Wilson 9862e600ce drm/i915/debugfs: Show the per-ring IMR
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:56 +00:00
Chris Wilson 0f46832fab drm/i915: Mask USER interrupts on gen6 (until required)
Otherwise we may consume 20% of the CPU just handling IRQs whilst
rendering. Ouch.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2011-01-11 20:43:56 +00:00
Jesse Barnes 3b8d8d91d5 drm/i915: dynamic render p-state support for Sandy Bridge
Add an interrupt handler for switching graphics frequencies and handling
PM interrupts.  This should allow for increased performance when busy
and lower power consumption when idle.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-18 11:07:02 +00:00
Mario Kleiner 0af7e4dff5 drm/i915: Add support for precise vblank timestamping (v2)
v2: Change IS_IRONLAKE to IS_GEN5 to adapt to 2.6.37

This patch adds new functions for use by the drm core:

.get_vblank_timestamp() provides a precise timestamp
for the end of the most recent (or current) vblank
interval of a given crtc, as needed for the DRI2
implementation of the OML_sync_control extension.
It is a thin wrapper around the drm function
drm_calc_vbltimestamp_from_scanoutpos() which does
almost all the work.

.get_scanout_position() provides the current horizontal
and vertical video scanout position and "in vblank"
status of a given crtc, as needed by the drm for use by
drm_calc_vbltimestamp_from_scanoutpos().

The patch modifies the pageflip completion routine
to use these precise vblank timestamps as the timestamps
for pageflip completion events.

This code has been only tested on a HP-Mini Netbook with
Atom processor and Intel 945GME gpu. The codepath for
(IS_G4X(dev) || IS_GEN5(dev) || IS_GEN6(dev)) gpu's
has not been tested so far due to lack of hardware.

Signed-off-by: Mario Kleiner <mario.kleiner@tuebingen.mpg.de>
Acked-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-16 21:02:24 +00:00
Chris Wilson c6df541c00 Revert "drm/i915: Avoid using PIPE_CONTROL on Ironlake"
Restore PIPE_CONTROL once again just for Ironlake, as it appears that
MI_USER_INTERRUPT does not have the same coherency guarantees, that is
on Ironlake the interrupt following a GPU write is not guaranteed to
arrive after the write is coherent from the CPU, as it does on the
other generations.

Reported-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Reported-by: Shuang He <shuang.he@intel.com>
Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=32402
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-15 10:15:25 +00:00
Chris Wilson b13c2b96bf drm/i915/ringbuffer: Make IRQ refcnting atomic
In order to enforce the correct memory barriers for irq get/put, we need
to perform the actual counting using atomic operations.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-14 11:34:46 +00:00
Chris Wilson 88f23b8fa3 drm/i915: Avoid using PIPE_CONTROL on Ironlake
The workaround is hideous and we are using the STORE_DWORD on all other
generations on all other rings, so use for the gen5 render ring as
well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 23:18:14 +00:00
Chris Wilson 1ec14ad313 drm/i915: Implement GPU semaphores for inter-ring synchronisation on SNB
The bulk of the change is to convert the growing list of rings into an
array so that the relationship between the rings and the semaphore sync
registers can be easily computed.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-12-05 00:37:38 +00:00
Chris Wilson ab5793ad3a drm/i915: Tweak on-error bbaddr parsing for clarity
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-25 15:03:24 +00:00
Chris Wilson 748ebc6017 drm/i915: Record fence registers on error.
Having seen the effects of erroneous fencing on the batchbuffer, a
useful sanity check is to record the fence registers at the time of an
error.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:13 +00:00
Chris Wilson 05394f3975 drm/i915: Use drm_i915_gem_object as the preferred type
A glorified s/obj_priv/obj/ with a net reduction of over a 100 lines and
many characters!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 20:19:10 +00:00
Chris Wilson 3685092b71 drm/i915: Avoid oops when capturing NULL ring for inactive pinned buffers
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-23 08:49:38 +00:00
Chris Wilson c4a1d9e4dc drm/i915: Capture interesting display registers on error
When trying to diagnose mysterious errors on resume, capture the
display register contents as well.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:08:19 +00:00
Chris Wilson c724e8a940 drm/i915: Capture pinned buffers on error
The pinned buffers are useful for diagnosing errors in setting up state
for the chipset, which may not necessarily be 'active' at the time of
the error, e.g. the cursor buffer object.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-22 08:07:02 +00:00
Chris Wilson 3143a2bf18 drm/i915: Convert (void)I915_READ to POSTING_READ
... and so hide the flushes from tracing.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-16 15:55:10 +00:00
Chris Wilson 8168bd48bb drm/i915: Remove the definitions for Primary Ring Buffer
We only ever used the PRB0, neglecting the secondary ring buffers, and
now with the advent of multiple engines with separate ring buffers we
need to excise the anachronisms from our code (and be explicit about
which ring we mean where). This is doubly important in light of the
FORCEWAKE required to read ring buffer registers on SandyBridge.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-11 17:54:52 +00:00
Chris Wilson 527f9e907c drm/i915: Remove the global irq wait queue
... as it has been replaced by per-ring waiters.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-11 01:16:58 +00:00
Chris Wilson e5c6526036 drm/i915/debugfs: Report ring in error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-11-01 12:08:05 +00:00
Chris Wilson add354ddf6 drm/i915: Record BSD engine error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 22:19:21 +01:00
Chris Wilson 1d8f38f4e7 drm/i915: Record BLT engine error state
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-29 19:22:13 +01:00
Chris Wilson f406839f09 drm/i915: Capture ERROR register on Sandybridge hangs
This holds error state from the main graphics arbiter mainly involving
the DMA engine and address translation.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:31:09 +01:00
Chris Wilson b2223497b4 drm/i915: Remove the confusing global waiting/irq seqno
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:30:59 +01:00
Chris Wilson 893eead092 drm/i915: Fix hangcheck to handle multiple rings
Currently, we believe the GPU is idle if just the RENDER ring is idle.
This is obviously wrong if we only using either the BLT or the BSD
rings and so masking genuine hangs.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:29:36 +01:00
Chris Wilson e1f99ce6ca drm/i915: Propagate errors from writing to ringbuffer
Preparing the ringbuffer for adding new commands can fail (a timeout
whilst waiting for the GPU to catch up and free some space). So check
for any potential error before overwriting HEAD with new commands, and
propagate that error back to the user where possible.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 23:26:34 +01:00
Chris Wilson 78501eac34 drm/i915/ringbuffer: Drop the redundant dev from the vfunc interface
The ringbuffer keeps a pointer to the parent device, so we can use that
instead of passing around the pointer on the stack.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-27 12:18:21 +01:00
Linus Torvalds c48c43e422 Merge branch 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-core-next' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (476 commits)
  vmwgfx: Implement a proper GMR eviction mechanism
  drm/radeon/kms: fix r6xx/7xx 1D tiling CS checker v2
  drm/radeon/kms: properly compute group_size on 6xx/7xx
  drm/radeon/kms: fix 2D tile height alignment in the r600 CS checker
  drm/radeon/kms/evergreen: set the clear state to the blit state
  drm/radeon/kms: don't poll dac load detect.
  gpu: Add Intel GMA500(Poulsbo) Stub Driver
  drm/radeon/kms: MC vram map needs to be >= pci aperture size
  drm/radeon/kms: implement display watermark support for evergreen
  drm/radeon/kms/evergreen: add some additional safe regs v2
  drm/radeon/r600: fix tiling issues in CS checker.
  drm/i915: Move gpu_write_list to per-ring
  drm/i915: Invalidate the to-ring, flush the old-ring when updating domains
  drm/i915/ringbuffer: Write the value passed in to the tail register
  agp/intel: Restore valid PTE bit for Sandybridge after bdd3072
  drm/i915: Fix flushing regression from 9af90d19f
  drm/i915/sdvo: Remove unused encoding member
  i915: enable AVI infoframe for intel_hdmi.c [v4]
  drm/i915: Fix current fb blocking for page flip
  drm/i915: IS_IRONLAKE is synonymous with gen == 5
  ...

Fix up conflicts in
 - drivers/gpu/drm/i915/{i915_gem.c, i915/intel_overlay.c}: due to the
   new simplified stack-based kmap_atomic() interface
 - drivers/gpu/drm/vmwgfx/vmwgfx_drv.c: added .llseek entry due to BKL
   removal cleanups.
2010-10-26 18:57:59 -07:00
Peter Zijlstra 3e4d3af501 mm: stack based kmap_atomic()
Keep the current interface but ignore the KM_type and use a stack based
approach.

The advantage is that we get rid of crappy code like:

	#define __KM_PTE			\
		(in_nmi() ? KM_NMI_PTE : 	\
		 in_irq() ? KM_IRQ_PTE :	\
		 KM_PTE0)

and in general can stop worrying about what context we're in and what kmap
slots might be appropriate for that.

The downside is that FRV kmap_atomic() gets more expensive.

For now we use a CPP trick suggested by Andrew:

  #define kmap_atomic(page, args...) __kmap_atomic(page)

to avoid having to touch all kmap_atomic() users in a single patch.

[ not compiled on:
  - mn10300: the arch doesn't actually build with highmem to begin with ]

[akpm@linux-foundation.org: coding-style fixes]
[akpm@linux-foundation.org: fix up drivers/gpu/drm/i915/intel_overlay.c]
Acked-by: Rik van Riel <riel@redhat.com>
Signed-off-by: Peter Zijlstra <a.p.zijlstra@chello.nl>
Acked-by: Chris Metcalf <cmetcalf@tilera.com>
Cc: David Howells <dhowells@redhat.com>
Cc: Hugh Dickins <hughd@google.com>
Cc: Ingo Molnar <mingo@elte.hu>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: "H. Peter Anvin" <hpa@zytor.com>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Russell King <rmk@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: David Miller <davem@davemloft.net>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Dave Airlie <airlied@linux.ie>
Cc: Li Zefan <lizf@cn.fujitsu.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-10-26 16:52:08 -07:00
Chris Wilson 549f736582 drm/i915: Enable SandyBridge blitter ring
Based on an original patch by Zhenyu Wang, this initializes the BLT ring for
SandyBridge and enables support for user execbuffers.

Cc: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-21 19:08:39 +01:00
Chris Wilson 69dc4987cb drm/i915: Track objects in global active list (as well as per-ring)
To handle retirements, we need per-ring tracking of active objects.
To handle evictions, we need global tracking of active objects.

As we enable more rings, rebuilding the global list from the individual
per-ring lists quickly grows tiresome and overly complicated. Tracking the
active objects in two lists is the lesser of two evils.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-20 10:51:51 +01:00
Andrea Gelmini 139d363bcf drivers: gpu: drm: i915: Fix a typo.
"userpace" -> "userspace"

Signed-off-by: Andrea Gelmini <andrea.gelmini@gelma.net>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-19 09:20:12 +01:00
Yuanhan Liu 2d7b8366ae drm/i915: Update hotplug interrupts register definitions for Sandybridge
On Sandybridge, the bit definition for hotplug on SDE has changed, so
update the code to new definition.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30378
Cc: stable@kernel.org
Signed-off-by: Yuanhan Liu <yuanhan.liu@intel.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-08 10:28:30 +01:00
Chris Wilson 2fa772f340 drm/i915: Only print 'generating error event' if we actually are
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-10-01 14:48:20 +01:00
Chris Wilson 30dbf0c07f drm/i915: Adjust hangcheck EIO semantics
Owain Ainsworth reported an issue between the interaction of the
hangcheck and userspace immediately (and permanently) falling back to
s/w rasterisation. In order to break the mutex and begin resetting the
GPU, we must abort the current operation (usually within the wait) and
climb sufficiently far back up the call chain to drop the mutex. In his
implementation, Owain has a loop within the ioctl handler to detect the
hang and then sleep until the error handler has run. I've chosen to
return to userspace and report an EAGAIN which should trigger the
userspace ioctl handler to repeat the call (simply because it felt less
invasive...). Before hitting a wedged GPU, we then wait upon completion
of the error handler.

Reported-by: Owain G. Ainsworth <zerooa@googlemail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-25 12:23:12 +01:00
Chris Wilson f787a5f59e drm/i915: Only hold a process-local lock whilst throttling.
Avoid cause latencies in other clients by not taking the global struct
mutex and moving the per-client request manipulation a local per-client
mutex. For example, this allows a compositor to schedule a page-flip
(through X) whilst an OpenGL application is monopolising the GPU.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-24 21:03:00 +01:00
Xiang, Haihao 881f47b647 drm/i915: add a new BSD ring buffer for Sandybridge
This ring buffer is used for video decoding/encoding on Sandybridge.

Signed-off-by: Xiang, Haihao <haihao.xiang@intel.com>
Reviewed-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:57 +01:00
Chris Wilson f803aa5532 drm/i915: Clean up bo lists on all hung gpus
Previously we only tidied up the active bo lists for chipsets were we
would attempt to reset the GPU. However, this action is necessary for
the system to continue and reclaim the dead bo for all chipsets.

Pointed out, in passing, by Owain Ainsworth.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:54 +01:00
Kenneth Graunke 0573ed4a94 drm/i915: Add support for GPU soft reset on Ironlake.
Ironlake's graphics reset register has to be accessed via the MCHBAR,
rather than via PCI config space, which requires some refactoring.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:48 +01:00
Kenneth Graunke eeccdcac07 drm/i915: Rename graphics reset registers.
The graphics domains are listed as GRDOM in the documentation, and the
GDRST PCI config register (0xc0) is only valid on I965 and GM45.  Newer
chips (like Sandy Bridge) have a different GDRST.

Signed-off-by: Kenneth Graunke <kenneth@whitecape.org>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:47 +01:00
Chris Wilson a6c45cf013 drm/i915: INTEL_INFO->gen supercedes i8xx, i9xx, i965g
Avoid confusion between i965g meaning broadwater and the gen4+ chipset
families.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-21 11:19:45 +01:00
Chris Wilson b3b079dbef drm/i915: Reduce hangcheck frequency
By reducing the hangcheck frequency we check less often, conserving
resources, and still detect a lock up quickly. On a fast machine with a
slow GPU (like a Core2 paired with a 945G) it is easy for the hangcheck to
misfire as we check too fast.

Also once hung and if we fail to completely reset the chip, we have a
nasty habit of proclaming a hang many times a second and generating a
strobe-like display.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-14 10:30:10 +01:00
Chris Wilson 5eddb70ba2 drm/i915: Use macros to switch between equivalent pipe registers
The purpose is to make the code much easier to read and therefore reduce
the possibility for bugs.

A side effect is that it also makes it much easier for the compiler,
reducing the object size by 4k -- from just a few functions!

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-11 19:27:12 +01:00
Chris Wilson 8b3016c4f4 Merge branch 'drm-intel-fixes' into drm-intel-next 2010-09-11 09:49:58 +01:00
Chris Wilson 4ef69c7a64 drm/i915: Rename intel_encoder->enc to base for consistency
[Patch is slightly larger than is strictly necessary to fixup
surrounding checkpatch.pl errors.]

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Jesse Barnes <jbarnes@virtuousgeek.org>
2010-09-09 17:00:13 +01:00
Chris Wilson 7839d956fc drm/i915: Double check that the wait_request is not pending before warning
If we are busy, then we may have woken up the wait_request handler but
not yet serviced it before the hang check fires. So in hang check,
double check that the i915_gem_do_wait_request() is still pending the
wake-up before declaring all hope lost.

Fixes regression with e78d73b16b.

Bugzilla: https://bugs.freedesktop.org/show_bug.cgi?id=30073
Reported-and-tested-by: Sitsofe Wheeler <sitsofe@yahoo.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-09 09:18:00 +01:00
Chris Wilson 8c80b59b37 drm/i915: Add ringbuffer wait reset to hangcheck
The GPU records whether it is currently waiting for a completion of a
WAIT_FOR_EVENT in the RB_WAIT bit in the ringbuffer control registers.
On third generation chipsets and later, a write of 1 to this bit breaks
the hang and returns the GPU to arbitration, i.e. the GPU should
continue executing the reminder of the batchbuffer and return to normal
operations.

By adding this to hangcheck we can avoid a full GPU reset under these
conditions.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 11:29:59 +01:00
Chris Wilson 995b6762f0 drm/i915: Quieten sparse warnings for missing prototypes.
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:57 +01:00
Chris Wilson 3bd3c93299 drm/i915: Compile out error state without DEBUG_FS
Alexander reported that the compilation of intel_overlay.c was failing
due to an inclusion that was only valid with CONFIG_DEBUG_FS. As the
whole error reporting is only useful with debugfs enabled, remove all
the redundant error state collection code when compiling without
CONFIG_DEBUG_FS.

Reported-by: Alexander Lam <lambchop468@gmail.com>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:23:55 +01:00
Chris Wilson 2bbda38963 drm/i915: Ironlake page-flipping is per-plane not per-pipe
Fix a minor confusion between intel_page_flip_finish(pipe) and
intel_page_flip_finish_plane(plane) -- should have no effect as
currently we map pipe 0 to plane 0 (and pipe 1 to plane 1).

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:34 +01:00
Chris Wilson 3b61796785 drm/i915: Rename i915_opregion.c to intel_opregion.c
It's part of the generic Intel driver infrastructure so rename it in
prepreparation for using it for VBT.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-08 10:13:31 +01:00
Simon Farnsworth 4e5359cd05 drm/i915: Avoid pageflipping freeze when we miss the flip prepare interrupt
When we miss the flip prepare interrupt, we never get into the
software state needed to restart userspace, resulting in a freeze of a
full-screen OpenGL application (such as a compositor).

Work around this by checking DSPxSURF/DSPxBASE to see if the page flip
has actually happened. If it has, do the work we would have done when
the flip prepare interrupt comes in.

Also, add debugfs information to tell us what's going on (based on the
patch from Chris Wilson attached to bugs.fdo bug #29798).

Signed-off-by: Simon Farnsworth <simon.farnsworth@onelan.co.uk>
Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
2010-09-07 11:16:35 +01:00
Zhenyu Wang 3fdef0205e drm/i915: fix render pipe control notify on sandybridge
This one is missed in last pipe control fix for sandybridge,
that really unmask interrupt bit for notify in render engine IMR.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-21 23:28:54 -07:00
Chris Wilson e78d73b16b drm/i915: Wake-up wait_request() from elapsed hang-check (v2)
If our watchdog fires and we see that the GPU is idle, but that we
are still waiting on an interrupt, forcibly wake-up the waiter.

i915_do_wait_request() should not be racy, yet there are persistent
reports that 945GM hangs whilst the GPU is idle. This implies that the
hardware is not quite as coherent as the documentation claims - a write
followed by a flush is supposed to be coherent in main memory before the
flush is retired and the irq is emitted. This seems to be a sensible and
elegant guard to force the wait to timeout.

v2: Daniel Vetter pointed out that a warning would be useful to explain
why the machine appeared to stall.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:36 -07:00
Chris Wilson e56660ddfb drm/i915: Record error batch buffers using iomem
Directly read the GTT mapping for the contents of the batch buffers
rather than relying on possibly stale CPU caches. Also for completeness
scan the flushing/inactive lists for the current buffers - we are
collecting error state after all.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:33 -07:00
Chris Wilson 6ef3d42780 drm/i915: Capture the overlay status upon a GPU hang.
v2: Add the interrupt status and address.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Reviewed-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-09 11:24:31 -07:00
Chris Wilson cbb465e72a drm/i915: Include instdone[1] in hangcheck
References:

  Bug 26691 - Spurious hangcheck whilst executing a long shader over a
              large vertex buffer
  https://bugs.freedesktop.org/show_bug.cgi?id=26691

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:46 -07:00
Jesse Barnes d874bcff79 drm/i915: remove duplicate PIPE*STAT bit definitions
Having two sets has made me think I caught a bug more than once now.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:42 -07:00
Jesse Barnes e25e660109 drm/i915: remove unused vblank_enable var from i915_driver_irq_handler
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-08-01 19:03:42 -07:00
Jesse Barnes 70565d00db drm/i915: fix page flip finish vs. prepare on plane B
The refreshed patch had a copy & paste bug.

Reported-by: Simon Farnsworth <simon.farnsworth@onelan.com>
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-07-01 18:47:12 -07:00
Andy Lutomirski 2d1c9752ea drm/i915: Fix CRT hotplug regression in 2.6.35-rc1
Commit 7a772c492f has two bugs which
made the hotplug problems on my laptop worse instead of better.

First, it did not, in fact, disable the CRT plug interrupt -- it
disabled all the other hotplug interrupts.  It seems rather doubtful
that that bit of the patch fixed anything, so let's just remove it.
(If you want to add it back, you probably meant ~CRT_HOTPLUG_INT_EN.)

Second, on at least my GM45, setting CRT_HOTPLUG_ACTIVATION_PERIOD_64
and CRT_HOTPLUG_VOLTAGE_COMPARE_50 (when they were previously unset)
causes a hotplug interrupt about three seconds later.  The old code
never restored PORT_HOTPLUG_EN so this could only happen once, but
they new code restores those registers.  So just set those bits when
we set up the interrupt in the first place.

Signed-off-by: Andy Lutomirski <luto@mit.edu>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-07-01 15:35:57 -07:00
Jesse Barnes 1afe3e9d43 drm/i915: gen3 page flipping fixes
Gen3 chips have slightly different flip commands, and also contain a bit
that indicates whether a "flip pending" interrupt means the flip has
been queued or has been completed.

So implement support for the gen3 flip command, and make sure we use the
flip pending interrupt correctly depending on the value of ECOSKPD bit
0.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-18 17:59:53 -07:00
Adam Jackson c496fa1fff drm/i915/gen4: Fix interrupt setup ordering
Unmask, then enable interrupts, then enable interrupt sources; matches
PCH ordering.  The old way (sources, enable, unmask) gives a window
during which interrupt conditions would appear in ISR but would never
reach IIR and thus never raise an IRQ.  Since interrupts only trigger
on rising edges in ISR, this would lead to conditions where (for
example) output hotplugging would never fire an interrupt because it
was already stuck on in ISR.

Also, since we know IIR and PIPExSTAT have been cleared during
irq_preinstall, don't clear them again during irq_postinstall, nothing
good can come of that.

Signed-off-by: Adam Jackson <ajax@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-06-04 17:21:41 -07:00
Chris Wilson 35aed2e6be drm/i915: Only print an message if there was an error
Only report an error if the GPU has actually detected one, otherwise we
are just hung.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-28 10:39:25 -07:00
Jesse Barnes 7648fa99eb drm/i915: add power monitoring support
Add power monitoring support to the i915 driver for use by the IPS
driver.  Export the available power info to the IPS driver through a few
new inter-driver hooks.  When used together, the IPS driver and this
patch can significantly increase graphics performance on Ironlake class
chips.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: Fixed 32-bit compile.  stupid obfuscating div_u64()]
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 14:10:01 -07:00
Zou Nan hai d1b851fc0d drm/i915: implement BSD ring buffer V2
The BSD (bit stream decoder) ring is used for accessing the BSD engine
which decodes video bitstream for H.264 and VC1 on G45+.  It is
asynchronous with the render ring and has access to separate parts of
the GPU from it, though the render cache is coherent between the two.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 13:46:58 -07:00
Zou Nan hai 852835f343 drm/i915: convert some gem structures to per-ring V2
The active list and request list move into the ringbuffer structure,
so each can track its active objects in the order they are in that
ring.  The flushing list does not, as it doesn't matter which ring
caused data to end up in the render cache.  Objects gain a pointer to
the ring they are active on (if any).

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 13:42:11 -07:00
Zou Nan hai 8187a2b70e drm/i915: introduce intel_ring_buffer structure (V2)
Introduces a more complete intel_ring_buffer structure with callbacks
for setup and management of a particular ringbuffer, and converts the
render ring buffer consumers to use it.

Signed-off-by: Zou Nan hai <nanhai.zou@intel.com>
Signed-off-by: Xiang Hai hao <haihao.xiang@intel.com>
[anholt: Fixed up whitespace fail and rebased against prep patches]
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-05-26 13:24:49 -07:00
Eric Anholt d3301d86b4 drm/i915: Rename dev_priv->ring to dev_priv->render_ring.
With the advent of the BSD ring, be clear about which ring this is.
The docs are pretty consistent with calling this the Render engine at
this point.
2010-05-26 12:36:00 -07:00
Eric Anholt 62fdfeaf8b drm/i915: Move ringbuffer-related code to intel_ringbuffer.c.
This is preparation for supporting multiple ringbuffers on Ironlake.
The non-copy-and-paste changes are:
- de-staticing functions
- I915_GEM_GPU_DOMAINS moving to i915_drv.h to be used by both files.
- i915_gem_add_request had only half its implementation
  copy-and-pasted out of the middle of it.
2010-05-26 12:36:00 -07:00
Linus Torvalds 59534f7298 Merge branch 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6
* 'drm-for-2.6.35' of git://git.kernel.org/pub/scm/linux/kernel/git/airlied/drm-2.6: (207 commits)
  drm/radeon/kms/pm/r600: select the mid clock mode for single head low profile
  drm/radeon: fix power supply kconfig interaction.
  drm/radeon/kms: record object that have been list reserved
  drm/radeon: AGP memory is only I/O if the aperture can be mapped by the CPU.
  drm/radeon/kms: don't default display priority to high on rs4xx
  drm/edid: fix typo in 1600x1200@75 mode
  drm/nouveau: fix i2c-related init table handlers
  drm/nouveau: support init table i2c device identifier 0x81
  drm/nouveau: ensure we've parsed i2c table entry for INIT_*I2C* handlers
  drm/nouveau: display error message for any failed init table opcode
  drm/nouveau: fix init table handlers to return proper error codes
  drm/nv50: support fractional feedback divider on newer chips
  drm/nv50: fix monitor detection on certain chipsets
  drm/nv50: store full dcb i2c entry from vbios
  drm/nv50: fix suspend/resume with DP outputs
  drm/nv50: output calculated crtc pll when debugging on
  drm/nouveau: dump pll limits entries when debugging is on
  drm/nouveau: bios parser fixes for eDP boards
  drm/nouveau: fix a nouveau_bo dereference after it's been destroyed
  drm/nv40: remove some completed ctxprog TODOs
  ...
2010-05-21 11:14:52 -07:00
Dave Airlie 05ea893c46 Merge remote branch 'anholt/drm-intel-next' into drm-next
* anholt/drm-intel-next: (515 commits)
  drm/i915: Fix out of tree builds
  drm/i915: move fence lru to struct drm_i915_fence_reg
  drm/i915: don't allow tiling changes on pinned buffers v2
  drm/i915: Be extra careful about A/D matching for multifunction SDVO
  drm/i915: Fix DDC bus selection for multifunction SDVO
  drm/i915: cleanup mode setting before unmapping registers
  drm/i915: Make fbc control wrapper functions
  drm/i915: Wait for the GPU whilst shrinking, if truly desperate.
  drm/i915: Use spatio-temporal dithering on PCH
  [MTD] Remove zero-length files mtdbdi.c and internal.ho
  pata_pcmcia / ide-cs: Fix bad hashes for Transcend and kingston IDs
  libata: Fix several inaccuracies in developer's guide
  slub: Fix bad boundary check in init_kmem_cache_nodes()
  raid6: fix recovery performance regression
  KEYS: call_sbin_request_key() must write lock keyrings before modifying them
  KEYS: Use RCU dereference wrappers in keyring key type code
  KEYS: find_keyring_by_name() can gain access to a freed keyring
  ALSA: hda: Fix 0 dB for Packard Bell models using Conexant CX20549 (Venice)
  ALSA: hda - Add quirk for Dell Inspiron 19T using a Conexant CX20582
  ALSA: take tu->qlock with irqs disabled
  ...
2010-05-19 09:35:51 +10:00
Dave Airlie eb1f8e4f3b drm/fbdev: rework output polling to be back in the core. (v4)
After thinking it over a lot it made more sense for the core to deal with
the output polling especially so it can notify X.

v2: drop plans for fake connector - per Michel's comments - fix X patch sent to xorg-devel, add intel polled/hpd setting, add initial nouveau polled/hpd settings.

v3: add config lock take inside polling, add intel/nouveau poll init/fini calls

v4: config lock was a bit agressive, only needed around connector list reading.
otherwise it could re-enter.

glisse: discard drm_helper_hpd_irq_event

v3: Reviewed-by: Michel Dänzer <michel@daenzer.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-05-18 17:40:11 +10:00
Andrew Morton 788885ae7a drivers/gpu/drm/i915/i915_irq.c:i915_error_object_create(): use correct kmap-atomic slot
i915_error_object_create() is called from the timer interrupt and hence
can corrupt the KM_USER0 slot.  Use KM_IRQ0 instead.

Reported-by: Jaswinder Singh Rajput <jaswinderlinux@gmail.com>
Tested-by: Jaswinder Singh Rajput <jaswinderlinux@gmail.com>
Acked-by: Chris Wilson <chris@chris-wilson.co.uk>
Cc: Dave Airlie <airlied@linux.ie>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2010-05-11 17:33:42 -07:00
Eric Anholt 34dc4d4423 Merge remote branch 'origin/master' into drm-intel-next
Conflicts:
	drivers/gpu/drm/i915/i915_dma.c
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/radeon/r300.c

The BSD ringbuffer support that is landing in this branch
significantly conflicts with the Ironlake PIPE_CONTROL fix on master,
and requires it to be tested successfully anyway.
2010-05-10 13:36:52 -07:00
Jesse Barnes e552eb7038 drm/i915: use PIPE_CONTROL instruction on Ironlake and Sandy Bridge
Since 965, the hardware has supported the PIPE_CONTROL command, which
provides fine grained GPU cache flushing control.  On recent chipsets,
this instruction is required for reliable interrupt and sequence number
reporting in the driver.

So add support for this instruction, including workarounds, on Ironlake
and Sandy Bridge hardware.

https://bugs.freedesktop.org/show_bug.cgi?id=27108

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Tested-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-22 14:48:55 -07:00
Daniel Vetter a8089e849a drm/i915: drop pointer to drm_gem_object
Luckily the change is quite a little bit less invasive than I've
feared.

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-20 13:23:14 +10:00
Dave Airlie 7fff400be6 Merge branch 'drm-fbdev-cleanup' into drm-core-next
* drm-fbdev-cleanup:
  drm/fb: remove drm_fb_helper_setcolreg
  drm/kms/fb: use slow work mechanism for normal hotplug also.
  drm/kms/fb: add polling support for when nothing is connected.
  drm/kms/fb: provide a 1024x768 fbcon if no outputs found.
  drm/kms/fb: separate fbdev connector list from core drm connectors
  drm/kms/fb: move to using fb helper crtc grouping instead of core crtc list
  drm/fb: fix fbdev object model + cleanup properly.

Conflicts:
	drivers/gpu/drm/i915/i915_drv.h
	drivers/gpu/drm/nouveau/nouveau_drv.h
2010-04-20 13:16:04 +10:00
Dave Airlie 97921a5b03 Merge remote branch 'anholt/drm-intel-next' of /home/airlied/kernel/drm-next into drm-core-next
* 'anholt/drm-intel-next' of /home/airlied/kernel/drm-next: (48 commits)
  agp/intel-gtt: kill previous_size assignments
  agp/intel-gtt: kill intel_i830_tlbflush
  agp/intel: split out gmch/gtt probe, part 1
  agp/intel: kill mutli_gmch_chip
  agp/intel: uncoditionally reconfigure driver on resume
  agp/intel: split out the GTT support
  agp/intel: introduce intel-agp.h header file
  drm/i915: Don't touch PORT_HOTPLUG_EN in intel_dp_detect()
  drm/i915/pch: Use minimal number of FDI lanes (v2)
  drm/i915: Add the support of memory self-refresh on Ironlake
  drm/i915: Move Pineview CxSR and watermark code into update_wm hook.
  drm/i915: Only save/restore FBC on the platform that supports FBC
  drm/i915: Fix the incorrect argument for SDVO SET_TV_format command
  drm/i915: Add support of SDVO on Ibexpeak PCH
  drm/i915: Don't enable pipe/plane/VCO early (wait for DPMS on).
  drm/i915: do not read uninitialized ->dev_private
  Revert "drm/i915: Use a dmi quirk to skip a broken SDVO TV output."
  drm/i915: implement multifunction SDVO device support
  drm/i915: remove unused intel_pipe_get_connector()
  drm/i915: remove connector object in old output structure
  ...
2010-04-20 13:11:45 +10:00
Linus Torvalds 13bd8e4673 Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel
* 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/anholt/drm-intel:
  drm/i915: Ignore LVDS EDID when it is unavailabe or invalid
  drm/i915: Add no_lvds entry for the Clientron U800
  drm/i915: Rename many remaining uses of "output" to encoder or connector.
  drm/i915: Rename intel_output to intel_encoder.
  agp/intel: intel_845_driver is an agp driver!
  drm/i915: introduce to_intel_bo helper
  drm/i915: Disable FBC on 915GM and 945GM.
2010-04-17 14:28:50 -07:00
Zhao Yakui edcb49ca34 drm/i915: Fix legacy BLC event for pipe A
OpRegion event on 965G requires legacy BLC event enabled in pipe stat. As LVDS
could be on either pipe now, we should enable BLC event on both pipe. If fail to
do so, we couldn't handle the brightness request triggered from graphics
opregion.

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-12 09:23:37 -07:00
Zhenyu Wang 5bf4c9c469 drm/i915: use encoder_list for hotplug callback
Instead of walking through drm connector_list uses encoder_list
for calling hotplug functions which is consistent with intel display
hotplug reporting.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-04-09 14:16:35 -07:00
Dave Airlie 4abe35204a drm/kms/fb: use slow work mechanism for normal hotplug also.
a) slow work is always used now for any fbcon hotplug, as its not
   a fast task and is more suited to being ran under slow work.

b) attempt to not do any fbdev changes when X is running as we'll
   just mess it up. This hooks set_par to hopefully do the changes
   once X hands control to fbdev.

This also adds the nouveau/intel hotplug support.

Signed-off-by: Dave Airlie <airlied@redhat.com>
2010-04-07 10:30:38 +10:00
Tejun Heo 5a0e3ad6af include cleanup: Update gfp.h and slab.h includes to prepare for breaking implicit slab.h inclusion from percpu.h
percpu.h is included by sched.h and module.h and thus ends up being
included when building most .c files.  percpu.h includes slab.h which
in turn includes gfp.h making everything defined by the two files
universally available and complicating inclusion dependencies.

percpu.h -> slab.h dependency is about to be removed.  Prepare for
this change by updating users of gfp and slab facilities include those
headers directly instead of assuming availability.  As this conversion
needs to touch large number of source files, the following script is
used as the basis of conversion.

  http://userweb.kernel.org/~tj/misc/slabh-sweep.py

The script does the followings.

* Scan files for gfp and slab usages and update includes such that
  only the necessary includes are there.  ie. if only gfp is used,
  gfp.h, if slab is used, slab.h.

* When the script inserts a new include, it looks at the include
  blocks and try to put the new include such that its order conforms
  to its surrounding.  It's put in the include block which contains
  core kernel includes, in the same order that the rest are ordered -
  alphabetical, Christmas tree, rev-Xmas-tree or at the end if there
  doesn't seem to be any matching order.

* If the script can't find a place to put a new include (mostly
  because the file doesn't have fitting include block), it prints out
  an error message indicating which .h file needs to be added to the
  file.

The conversion was done in the following steps.

1. The initial automatic conversion of all .c files updated slightly
   over 4000 files, deleting around 700 includes and adding ~480 gfp.h
   and ~3000 slab.h inclusions.  The script emitted errors for ~400
   files.

2. Each error was manually checked.  Some didn't need the inclusion,
   some needed manual addition while adding it to implementation .h or
   embedding .c file was more appropriate for others.  This step added
   inclusions to around 150 files.

3. The script was run again and the output was compared to the edits
   from #2 to make sure no file was left behind.

4. Several build tests were done and a couple of problems were fixed.
   e.g. lib/decompress_*.c used malloc/free() wrappers around slab
   APIs requiring slab.h to be added manually.

5. The script was run on all .h files but without automatically
   editing them as sprinkling gfp.h and slab.h inclusions around .h
   files could easily lead to inclusion dependency hell.  Most gfp.h
   inclusion directives were ignored as stuff from gfp.h was usually
   wildly available and often used in preprocessor macros.  Each
   slab.h inclusion directive was examined and added manually as
   necessary.

6. percpu.h was updated not to include slab.h.

7. Build test were done on the following configurations and failures
   were fixed.  CONFIG_GCOV_KERNEL was turned off for all tests (as my
   distributed build env didn't work with gcov compiles) and a few
   more options had to be turned off depending on archs to make things
   build (like ipr on powerpc/64 which failed due to missing writeq).

   * x86 and x86_64 UP and SMP allmodconfig and a custom test config.
   * powerpc and powerpc64 SMP allmodconfig
   * sparc and sparc64 SMP allmodconfig
   * ia64 SMP allmodconfig
   * s390 SMP allmodconfig
   * alpha SMP allmodconfig
   * um on x86_64 SMP allmodconfig

8. percpu.h modifications were reverted so that it could be applied as
   a separate patch and serve as bisection point.

Given the fact that I had only a couple of failures from tests on step
6, I'm fairly confident about the coverage of this conversion patch.
If there is a breakage, it's likely to be something in one of the arch
headers which should be easily discoverable easily on most builds of
the specific arch.

Signed-off-by: Tejun Heo <tj@kernel.org>
Guess-its-ok-by: Christoph Lameter <cl@linux-foundation.org>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: Lee Schermerhorn <Lee.Schermerhorn@hp.com>
2010-03-30 22:02:32 +09:00
Eric Anholt 21d40d37ec drm/i915: Rename intel_output to intel_encoder.
The intel_output naming is inherited from the UMS code, which had a
structure of screen -> CRTC -> output.  The DRM code has an additional
notion of encoder/connector, so the structure is screen -> CRTC ->
encoder -> connector.  This is a useful structure for SDVO encoders
which can support multiple connectors (each of which requires
different programming in the one encoder and could be connected to
different CRTCs), or for DVI-I, where multiple encoders feed into the
connector for whether it's used for digital or analog.  Most of our
code is encoder-related, so transition it to talking about encoders
before we start trying to distinguish connectors.

This patch is produced by sed s/intel_output/intel_encoder/ over the
driver.

Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-25 12:27:32 -07:00
Daniel Vetter 23010e43b3 drm/i915: introduce to_intel_bo helper
This is a purely cosmetic change to make changes in this area easier.
And hey, it's not only clearer and typechecked, but actually shorter,
too!

[anholt: To clarify, this is a change to let us later make
drm_i915_gem_object subclass drm_gem_object, instead of having
drm_gem_object have a pointer to i915's private data]

Signed-off-by: Daniel Vetter <daniel.vetter@ffwll.ch>
Acked-by: Dave Airlie <airlied@gmail.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-03-25 11:06:17 -07:00
Eric Anholt c619eed4b2 drm/i915: More s/IS_IRONLAKE/HAS_PCH_SPLIT for Sandybridge.
I think this is pretty much correct.  Not really tested.

Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-26 13:23:20 -08:00
Eric Anholt b9201c14d9 drm/i915: Disable the hangcheck reset on Sandybridge until we add support.
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-26 13:23:20 -08:00
Eric Anholt bad720ff3e drm/i915: Add initial bits for VGA modesetting bringup on Sandybridge.
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-26 13:23:17 -08:00
Chris Wilson 9df30794f6 drm/i915: Record batch buffer following GPU error
In order to improve our diagnostic capabilities following a GPU hang
and subsequent reset, we need to record the batch buffer that triggered
the error. We assume that the current batch buffer, plus a few details
about what else is on the active list, will be sufficient -- at the very
least an improvement over nothing.

The extra information is stored in /debug/dri/.../i915_error_state
following an error, and may be decoded using
intel_gpu_tools/tools/intel_error_decode.

v2: Avoid excessive work under spinlocks.
v3: Include ringbuffer for later analysis.
v4: Use kunmap correctly and record more buffer state.
v5: Search ringbuffer for current batch buffer
v6: Use a work fn for the impossible IRQ error case.
v7: Avoid non-atomic paths whilst in IRQ context.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22 12:01:39 -05:00
Matthew Garrett b5b72e891a drm/i915: Deobfuscate the render p-state obfuscation
The ironlake render p-state support includes some rather odd variable
names. Clean them up in order to improve the readability of the code.

Signed-off-by: Matthew Garrett <mjg@redhat.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22 11:46:55 -05:00
Jesse Barnes f97108d1d0 drm/i915: add dynamic performance control support for Ironlake
Ironlake (and 965GM, which this patch doesn't support) supports a
hardware performance and power management feature that allows it to
adjust to changes in GPU load over time with software help.  The goal
if this is to maximize performance/power for a given workload.

This patch enables that feature, which is also a requirement for
supporting Intelligent Power Sharing, a feature which allows for
dynamic budgeting of power between the CPU and GPU in Arrandale
platforms.

Tested-by: ykzhao <yakui.zhao@intel.com>
[anholt: Resolved against the irq handler loop removal]
Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-22 11:46:54 -05:00
Zhenyu Wang f072d2e771 drm/i915: fix flip done interrupt on Ironlake
On Ironlake plane flip interrupt means flip done event already, the
behavior is not like old chips, and perform like other usual interrupt.
So only need to handle flip done event when receiving that interrupt.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-02-10 14:34:13 -08:00
Jesse Barnes 013d5aa2bb drm/i915: page flip support for Ironlake
This patch adds support for page flipping on Ironlake, which uses
different interrupt bits for triggering flip submit IRQs.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
[anholt: hand-resolved for rebasing off of render power saving patch]
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-29 15:29:47 -08:00
Li Peng 643ced9b0b drm/i915: don't trigger ironlake vblank interrupt at irq install
Zhenyu noticed that the ironlake vblank enabling patch has one
issue that it will trigger vblank starting from irq postinstall,
this isn't necessary. This patch addresses this issue by only
adding the vblank into DEIER but mask them in DEIMR, so that it
won't trigger vblank interrupt at irq install.

Signed-off-by: Li Peng <peng.li@intel.com>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-29 14:22:09 -08:00
Li Peng c062df6196 drm/i915: enable vblank interrupt on ironlake
so far vblank interrupt on ironlake is disabled, this would cause
bad gfx performance if userspace calls drm_wait_vblank. This patch
enables vblank interrupt on ironlake and follows vblank get/put
model.

Signed-off-by: Li Peng <peng.li@intel.com>
Acked-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-25 09:14:30 -08:00
Zou Nan hai c7c85101af drm/i915: remove loop in Ironlake interrupt handler
On Ironlake, there is an interrupt master control bit. With the bit
disabled before clearing IIR, we do not need to handle extra interrupt
in a loop. This patch removes the loop in Ironlake interrupt handler.
It fixed irq lost issue on some Ironlake platforms.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zou Nan hai <Nanhai.zou@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2010-01-15 11:23:49 -08:00
Zhenyu Wang c566ec4915 drm/i915: Reload hangcheck timer too for Ironlake
Make sure hangcheck timer won't beat us unexpectedly on Ironlake.

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-17 11:17:38 -08:00
Jesse Barnes b01f2c3a4a drm/i915: only enable hotplug for detected outputs
This patch changes around our hotplug enable code a bit to only enable
it for ports we actually detect and initialize.  This prevents problems
with stuck or spurious interrupts on outputs that aren't actually wired
up, and is generally more correct.

Fixes FDO bug #23183.

Signed-off-by: Jesse Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-16 14:00:05 -08:00
Dave Airlie 0b5e8db639 Merge remote branch 'anholt/drm-intel-next' into drm-linus
Pull more Intel changes in, especially one to init the GTT properly
2009-12-10 15:44:19 +10:00
Chris Wilson 4f8d619cc3 drm/i915: Remove a debugging printk from hangcheck
A residual bare printk survived the merger of the hang detector, remove
this debugging left-over.

Signed-off-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-08 23:40:47 -08:00
Dave Airlie 3ff99164f6 Merge remote branch 'anholt/drm-intel-next' into drm-linus
This merges the upstream Intel tree and fixes up numerous conflicts
due to patches merged into Linus tree later in -rc cycle.

Conflicts:
	drivers/char/agp/intel-agp.c
	drivers/gpu/drm/drm_dp_i2c_helper.c
	drivers/gpu/drm/i915/i915_irq.c
	drivers/gpu/drm/i915/i915_suspend.c
2009-12-08 14:03:47 +10:00
Adam Jackson f2b115e69d drm/i915: Fix product names and #defines
IGD* isn't a useful name.  Replace with the codenames, as sourced from
pci.ids.

Signed-off-by: Adam Jackson <ajax@redhat.com>
[anholt: Fixed up for merge with pineview/ironlake changes]
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-07 14:55:56 -08:00
Kristian Høgsberg 6b95a207c1 drm/i915: Add intel implementation of the pageflip ioctl
Acked-by: Jakob Bornecrantz <jakob@vmware.com>
Acked-by: Thomas Hellström <thomas@shipmail.org>
Review-by: Chris Wilson <chris@chris-wilson.co.uk>
Signed-off-by: Jesse "Orange Smoothie" Barnes <jbarnes@virtuousgeek.org>
Signed-off-by: Kristian Høgsberg <krh@bitplanet.net>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-12-01 09:10:35 -08:00
Shaohua Li 2644487781 drm/i915: remove Pineview EOS protection support
HW guys have an evaluation about the impact about EOS, and say the impact
is quite small, so they have removed EOS detection support. This patch
removes EOS feature.

revert commit 0430296558
directly reverting it gives a hunk error, so please use this one.

Signed-off-by: Shaohua Li <shaohua.li@intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
[anholt: fixed up commit message for update that the feature's really gone]
2009-11-30 09:42:12 -08:00
Zou, Nanhai 2d109a845d drm/i915: Fix IRQ stall issue on Ironlake
The master irq control in DE must be disabled before irq handling,
and enable after the process. This fixes the irq stall issue on
Ironlake.

Cc: Stable Team <stable@kernel.org>
Signed-off-by: Zou, Nanhai <nanhai.zou@intel.com>
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-12 11:16:33 -08:00
Zhenyu Wang c650156af3 drm/i915: Add display hotplug event on Ironlake
Enable display hotplug irqs from Ibex Peak (PCH).

Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:49:37 -08:00
Zhao Yakui 01c66889c1 drm/i915: Add ACPI OpRegion support for Ironlake
Add the support of ACPI opregion on Ironlake so that the backlight
brightness can be adjusted by using ACPI interface
   >/sys/class/backlight/acpi_video0/brightness

Signed-off-by: Zhao Yakui <yakui.zhao@intel.com>
Tested-by: Zhao Yakui <yakui.zhao@intel.com>
[zhenyuw: cleanups, fix typo for checking GSE irq and convert to
current irq handling logic.]
Signed-off-by: Zhenyu Wang <zhenyuw@linux.intel.com>
Signed-off-by: Eric Anholt <eric@anholt.net>
2009-11-05 14:49:13 -08:00