Commit Graph

441294 Commits

Author SHA1 Message Date
Chen-Yu Tsai b4575c6998 pinctrl: sunxi: fix pin numbers passed to register offset helpers
The pin numbers passed to sunxi_*_reg helpers to get the correct
registers should be the pin offset for the PIO block, not the
absolute number we use that is based on the alphanumeric labels
Allwinner uses.

This patch subtracts .pin_base from the pin number passed to these
functions, so the driver accesses the correct registers.

Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Reviewed-by: Boris Brezillon <boris.brezillon@free-electrons.com>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:26:01 +02:00
Anson Huang 2cc140fe36 pinctrl: add pinctrl driver for imx6sx
Add a pinctrl driver for i.MX6 SoloX based on pinctrl-imx core
driver.

Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@freescale.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:24:28 +02:00
Alexander Stein cccb0c3e6a pinctrl/at91: Fix lockup when IRQ on PIOC and PIOD occurs
With commit 80cc3732 (pinctrl/at91: convert driver to use gpiolib irqchip)
gpiochip_set_chained_irqchip is called for PIOC, PIOD and PIOE. The
associated GPIO chip for the IRQ chip is overwritten each time, because
they share the same hard IRQ line.
Thus if an IRQ occurs on PIOC or PIOD, gpio_irq_handler will only check on
PIOE (the assigned GPIO chip) where no event occured. Thus the IRQ will
not be cleared, retriggering the ISR.
Fix that (like done before) by only set the PIOC GPIO chip to the IRQ chip
and walk the list in the irq handler.

Signed-off-by: Alexander Stein <alexanders83@web.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-27 11:13:10 +02:00
Linus Walleij cdcb0ab630 pinctrl: msm: switch to using generic GPIO irqchip helpers
This switches the Qualcomm MSM pin control driver over to using
the generic GPIO irqchip helpers.

Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Josh Cartwright <joshc@codeaurora.org>
Acked-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:40:04 +02:00
Maxime Ripard ba6764d57d pinctrl: sunxi: Fix multiple registration issue
When the support for the PRCM muxer on the A31 has been added, the global
static pinctl_desc definition has been left as is. Unfortunately, this
structure is used to register the pinctrl device, and prior to this
registration, we set the name and pins field.

Since this structure is shared across instances, that means that the latest
registered pinctrl device wins in setting the name, pins and pins numbers,
which is not really a good thing.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:36:27 +02:00
Maxime Ripard 118c565a8f pinctrl: sunxi: Fix recursive dependency
Fix the following configuration error:
drivers/pinctrl/sunxi/Kconfig:3:error: recursive dependency detected!
drivers/pinctrl/sunxi/Kconfig:3:	symbol PINCTRL_SUNXI is selected by PINCTRL_SUN4I_A10
drivers/pinctrl/sunxi/Kconfig:9:	symbol PINCTRL_SUN4I_A10 default value contains PINCTRL_SUNXI

Add a new intermedia PINCTRL_SUNXI_COMMON, that superseeds the PINCTRL_SUNXI
one.

We still need to keep PINCTRL_SUNXI at the moment in order to preserve
bisectability. Indeed, during that merge window, we also introduced the
MACH_SUN* symbols. Since it's going through different trees, we can't rely on
the fact that the options will be there, while ARCH_SUNXI still select
PINCTRL_SUNXI.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:35:16 +02:00
Antoine Tenart 48b6bce352 pinctrl: berlin: add the BG2CD pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:06:38 +02:00
Antoine Tenart b016d1bd05 pinctrl: berlin: add the BG2 pinctrl driver
Add the pin-controller driver for the Berlin BG2 SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:06:04 +02:00
Antoine Tenart 626eea8706 pinctrl: berlin: add the BG2Q pinctrl driver
Add the pin-controller driver for the Berlin BG2Q SoC, with definition
of its groups and functions. Pin control registers are part of chip/
system control registers, which will be represented by a single node.
Until a proper driver for the chip/system control is available,
register the corresponding regmap in pinctrl driver probe.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:05:30 +02:00
Antoine Tenart 3de68d331c pinctrl: berlin: add the core pinctrl driver for Marvell Berlin SoCs
The Marvell Berlin boards have a group based pinmuxing mechanism. This
adds the core driver support. We actually do not need any information
about the pins here and only have the definition of the groups.

Let's take the example of the uart0 pinmuxing on the BG2Q. Balls BK4 and
BH6 are muxed to respectively UART0 RX and TX if the group GSM12 is set
to mode 0:

Group	Modes	Offset Base	Offset	LSB	Bit Width
GSM12	3	sm_base		0x40	0x10	0x2

Ball	Group	Mode 0		Mode 1		Mode 2
BK4	GSM12	UART0_RX	IrDA0_RX	GPIO9
BH6	GSM12	UART0_TX	IrDA0_TX	GPIO10

So in order to configure BK4 -> UART0_TX and BH6 -> UART0_RX, we need
to set (sm_base + 0x40 + 0x10) &= ff3fffff.

As pin control registers are part of either chip control or system
control registers, that deal with a bunch of other functions we rely
on a regmap instead of exclusively remapping any resources.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:05:00 +02:00
Mika Westerberg 3ff95885ed pinctrl: baytrail: Add pull type, strength and open drain to debugfs output
In case of resolving power management or similar issues it might be useful
to have these properties included in the debugfs output.

Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Acked-by: Mathias Nyman <mathias.nyman@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:54 +02:00
Jin Yao 605a7bca7c pinctrl: baytrail: Register GPIO chip after chip->to_irq is set
If chip->to_irq is NULL ACPI GPIO helpers don't register GPIO event
handlers thus preventing any ACPI GPIO triggered events. Solve this by
calling gpiochip_add() after we have set up drivers chip->to_irq hook.

Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:53 +02:00
Jin Yao 20482d3279 pinctrl: baytrail: Add back Baytrail-T ACPI ID
Now that the x86 dynamic IRQ allocation problem has been resolved with
commmit 62a08ae2a5 (genirq: x86: Ensure that dynamic irq allocation does
not conflict), we can add back Baytrail-T ACPI ID to the pinctrl driver.

This makes the driver to work on Asus T100 where it is needed for several
things like ACPI GPIO events and SD card detection.

References: https://bugzilla.kernel.org/show_bug.cgi?id=68291
Acked-by: Rafael J. Wysocki <rafael.j.wysocki@intel.com>
Signed-off-by: Jin Yao <yao.jin@intel.com>
Signed-off-by: Mika Westerberg <mika.westerberg@linux.intel.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:53 +02:00
Magnus Damm f39d8a72fe pinctrl: sh-pfc: r8a73a4: Allow Multiplatform Build
Add #ifdefs to allow r8a73a4 Multiplatform build. Needed
to enable r8a73a4 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:52 +02:00
Magnus Damm 672d323774 pinctrl: sh-pfc: sh73a0: Allow Multiplatform Build
Add #ifdefs to allow sh73a0 Multiplatform build. Needed
to enable sh73a0 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:52 +02:00
Magnus Damm b6c996a295 pinctrl: sh-pfc: r8a7740: Allow Multiplatform Build
Add #ifdefs to allow r8a7740 Multiplatform build. Needed
to enable r8a7740 Multiplatform support.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:51 +02:00
Laurent Pinchart 0e26e8dfb9 pinctrl: sh-pfc: Don't set the pinmux_irq irq field for multiplatform
In the multiplatform kernel case the IRQs associated with the PFC GPIOs
are specified through DT. The pinmux_irq irq field is thus ignored by
the code, and doesn't need to be set.

This will allow removing the mach/irq.h include from pfc-*.c files that
was required for the irq_pin() macro used to initialize the irq field.

Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:51 +02:00
Maxime Ripard b22116b33a pinctrl: sunxi: Enable the pinctrl Kconfig options by default
Enable the freshly introduced Kconfig options whenever their matching
architecture is enabled.

Since the Kconfig symbols for these machines are going through a different
tree, keep PINCTRL_SUNXI around for the moment to avoid breaking the defconfig.
It should be removed eventually.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-23 00:01:50 +02:00
Heiko Stübner c51426efd3 dt-bindings: adapt rockchip-pinctrl doc to changed bindings
Introduce the syscons for grf and pmu and deprecate the previous register
areas.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:16:41 +02:00
Heiko Stübner 1e747e59cc pinctrl: rockchip: base regmap supplied by a syscon
This allows the basic registers of the general register files to be supplied
by a syscon instead of being mapped locally.

The GRF registers contain a lot more than pinctrl functions like dma, usb-phy
and general soc control and status registers, intermixed with the iomux, pull
and drive-strength registers.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:16:13 +02:00
Heiko Stübner a658efaa85 pinctrl: rockchip: only map bank0-pull-region when pmu regmap missing
When the pmu registers are supplied through a syscon regmap we do not need
to map the registers ourself.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:15:46 +02:00
Heiko Stübner 14dee8677e pinctrl: rockchip: let pmu registers be supplied by a syscon
Currently the pmu registers containing pin pull settings on the rk3188 are mapped
locally when bank0 is instantiated. Add an alternative that can resolve the pmu
from a syscon phandle.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:15:17 +02:00
Heiko Stübner 622f32372b pinctrl: rockchip: rockchip_pinctrl in rockchip_get_bank_data
Convert rockchip_get_bank_data to use the struct rockchip_pinctrl because
later on we need to check a value from it when registering the gpio banks.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:14:46 +02:00
Heiko Stübner 751a99aba4 pinctrl: rockchip: use regmaps instead of raw mappings
This allows us to use syscons in the future.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:14:15 +02:00
Heiko Stübner bfc7a42a0e pinctrl: rockchip: do not require 2nd register area
Deprecate secondary register area for rk3188 pulls. Instead use big enough
initial mapping of grf registers to catch all.

The now deprecated register is still supported though.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Max Schwarz <max.schwarz@online.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-09 11:13:44 +02:00
Linus Walleij 9dffe1d4a7 Pinctrl cleanup and reworks for 3.16
This serie of patch:
   - Moves the Allwinner pinctrl driver to a folder of its own
   - removes the sunxi-pinctrl-pins header, and split the driver into a core
     one, with all the logic, and smaller drivers, one for each SoC, that
     declare the pins, and will provide to the core the set of pins.
   - And does a few cleanups here and there.
 -----BEGIN PGP SIGNATURE-----
 Version: GnuPG v1.4.14 (GNU/Linux)
 
 iQIcBAABAgAGBQJTZuWnAAoJEBx+YmzsjxAgRkwQAIhWvJQjbcge8vzPYBmX+KdD
 kv+P00u5U8H8EOsLVCphOWtok7uARKEOA+mrhSTucvQmyU2GeJg8xBK/NZVvANR+
 HAnORGIYzeYX6OUW/EXcQDcMcnEHZS5fOMYW8oqnQhRga5by/DZ40lxepgTWb5gb
 uhzwE4sKpxG0qLyQI+CMyLt5GOvObdRHe/7btZWKtOPScUDrgsAOAKRJ6QPJG6VV
 u0M0EUi+sU7u6dUVKooo8szqbKjZ1iq+1t/VDSQrHMTeoRoytkh1+y+czNNE1hDj
 8MA+OhJwxg6CAxKL4ylBGwL1sx8Bv9Yuwzv9OtJkBUJjY28j0jKdoKhlDh79ZJG7
 hclrPltvZjZZEm1UQ3Q4ItVpA9u8l9Wwx/+R58AQtUd3fkZdHeyi+HFcdtVG6kWU
 RgcnDPt9tzgPbocevIdqbGtoctZyC+4IK1ifOTBdBL4ccyWBmh9H9+rRZJ0eCENC
 dCC60mYW5ToYskbT/huI+8+uIFvvxrg5WS2GiCIoSNG4KEplnl7cypwncL6hvJyu
 cIYgseWo8C8qsPf2kQ82JaJAim70sE2w1F9Edr6pv4XLmCv5/2hU4i1xXEXdwp3P
 1RNP7EzmIAFJFnlWlMFh1euwaVXjdwZ2TXpMr6iZ18RVIoMWBMfvFwNLF083oXJe
 uHH8T/+UiDR17Fwm2Kqf
 =nUR7
 -----END PGP SIGNATURE-----

Merge tag 'sunxi-pinctrl-for-3.16' of https://github.com/mripard/linux into devel

Pinctrl cleanup and reworks for 3.16

This serie of patch:
  - Moves the Allwinner pinctrl driver to a folder of its own
  - removes the sunxi-pinctrl-pins header, and split the driver into a core
    one, with all the logic, and smaller drivers, one for each SoC, that
    declare the pins, and will provide to the core the set of pins.
  - And does a few cleanups here and there.
2014-05-09 08:47:16 +02:00
Maxime Ripard dc9691066f pinctrl: sunxi: Move the reset handling functions out of the core
The way that reset is handled right now is that it is made optional for every
pinctrl driver, while actually, it isn't used at all for the main pin
controllers so far, and while it's mandatory for the A31's secondary pin
controller.

Move the reset functions out of the core and in the driver, where they can be
made mandatory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 19:57:18 -05:00
Maxime Ripard 340ba6c497 pinctrl: sunxi: Introduce per-driver Kconfig options
Add one Kconfig option for each driver. This will allow to better control which
driver is enabled, instead of having either all or nothing.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 19:41:44 -05:00
Maxime Ripard 2519859418 pinctrl: sunxi: Move Allwinner A20 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be.

This is the final step toward retiring pinctrl-sunxi-pins.h that used to define
all the pins for all the Allwinner SoCs in a single header, that would have in
turn result in having these structures in the final binary as many times as the
header was included.

We can finally remove that header, and remove all the driver part of the
pinctrl-sunxi core.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:04:49 -07:00
Maxime Ripard 16c675f989 pinctrl: sunxi: Move Allwinner A31 special pins driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:31 -07:00
Maxime Ripard 1c996176e7 pinctrl: sunxi: Move Allwinner A31 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:30 -07:00
Maxime Ripard 342cefb212 pinctrl: sunxi: Move Allwinner A13 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard 0a127c1c39 pinctrl: sunxi: Move Allwinner A10s pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:29 -07:00
Maxime Ripard f2821b1ca3 pinctrl: sunxi: Move Allwinner A10 pinctrl driver to a driver of its own
Move the pin description to a driver specific to be. This is one more step
toward retiring pinctrl-sunxi-pins.h that used to define all the pins for all
the Allwinner SoCs in a single header, that would have in turn result in having
these structures in the final binary as many times as the header was included.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:28 -07:00
Maxime Ripard 2284ba6b7d pinctrl: sunxi: Libraryse the driver
This will allow to have multiple drivers using the same core code, and
eventually, retire pinctrl-sunxi-pins.h

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-04 00:03:24 -07:00
Maxime Ripard 4409cafc1a pinctrl: sunxi: Switch to devm_ioremap_resource
The previous code was calling of_iomap, which doesn't do any resource
management, and doesn't call request_mem_region either. Use
devm_ioremap_resource that do both.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard d10acc6353 pinctrl: sunxi: Replace hardcoded pin defines by a macro
We previously had an evergrowing (and exhaustive) list of the pins that could
be used on any Allwinner SoCs. These defines were then used by each pinctrl
driver to declare the list of functions for this pin. Since it's pretty much
all boilerplate, we can remove it just by a single macro.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:44 -07:00
Maxime Ripard 5f9107774f pinctrl: sunxi: Move the Allwinner pinctrl driver to its own directory
This will allow to create numerous files without crippling the main pinctrl
directory.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:43 -07:00
Maxime Ripard 0df6846d55 pinctrl: sunxi: Drop unused structure members
The ranges and nranges were never used. Remove them.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:42 -07:00
Maxime Ripard d39bd8457f pinctrl: sunxi: Add const qualifier to the pin descriptor
The pins description structure were declared as const, but the of_device_id
data magic was losing it silently.

Make sure we have it on both sides.

And now that we're using const, we can also remove the useless cast in probe.

Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2014-05-03 23:59:02 -07:00
Andy Gross 2aa02733fb pinctrl: qcom: Correct name for pin 0
Fix copy/paste error in pinctrl_pin_desc for pin 0.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-05-02 15:42:52 -07:00
Thomas Petazzoni fd67f88478 pinctrl: mvebu: new driver for Orion platforms
This commit extends the pinctrl mvebu logic with a new driver to cover
Orion5x SoC. It supports the definitions for the 5181l, 5182 and 5281
variants of Orion5x, which are the three ones supported by the old
style MPP code in arch/arm/mach-orion5x/.

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-24 15:09:35 +02:00
Heiko Stübner a076e2ed3f pinctrl: rockchip: implement PIN_CONFIG_OUTPUT handling
In some cases it is nice to be able to simply control a gpio output
via the PIN_CONFIG_OUTPUT option without having a driver control it.
Thus add support for it to the rockchip pinctrl driver.

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 23:19:40 +02:00
Heiko Stübner dab3eba7c1 pinctrl: rockchip: return a complete config in pinconf_get
Till now pinconf_get only set the argument value into the config parameter
effectively removing the actual config param value. As other pinctrl drivers
do, it might be nicer to keep the config param intact.
Therefore construct a real pinconfig value from param and arg in pinconf_get

Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 23:18:37 +02:00
Linus Walleij 7420d2d09b pinctrl: sirf: switch driver to use gpiolib irqchip helpers
This switches the SiRF pinctrl driver over to using the gpiolib
irqchip helpers simplifying some of the code.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:02:54 +02:00
Barry Song c5eb757ca8 pinctrl: sirf: wrap all gpio banks into one gpio_chip
all gpio banks are in one chip, that makes software clean in mapping
irq and gpio.

Signed-off-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:01:31 +02:00
Linus Walleij aef95b691f pinctrl: sirf: rename inlined accessor
The sirfsoc_irqchip_to_bank() is obviously misnamed, as it is
not converting an irqchip to a bank but converts a gpiochip
to a bank so rename it sirfsoc_gpiochip_to_bank().

Acked-by: Barry Song <Baohua.Song@csr.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 22:01:17 +02:00
Andy Gross 625cb407b8 dt: Document Qualcomm IPQ8064 pinctrl binding
Define a new binding for the Qualcomm TLMMv2 based pin controller inside the
IPQ8064.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 16:02:09 +02:00
Andy Gross b4da6573e7 pinctrl: qcom: Add definitions for IPQ8064
This adds pinctrl definitions for the GPIO pins of the TLMM v2 block in the
Qualcomm IPQ8064 platform.

Signed-off-by: Andy Gross <agross@codeaurora.org>
Reviewed-by: Bjorn Andersson <bjorn.andersson@sonymobile.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 15:59:58 +02:00
Boris BREZILLON 02b5269a24 pinctrl: sunxi: list all pinctrl compatible strings
List all sunxi pinctrl compatible strings in order to be able to grep for
those values.

Signed-off-by: Boris BREZILLON <boris.brezillon@free-electrons.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
2014-04-23 15:47:08 +02:00