Commit Graph

767803 Commits

Author SHA1 Message Date
Mikita Lipski fe61a2f1a5 drm/amd/display: adding ycbcr420 pixel encoding for hdmi
[why]
HDMI EDID's VSDB contains spectial timings for specifically
YCbCr 4:2:0 colour space. In those cases we need to verify
if the mode provided is one of the special ones has to use
YCbCr 4:2:0 pixel encoding for display info.
[how]
Verify if the mode is using specific ycbcr420 colour space with
the help of DRM helper function and assign the mode to use
ycbcr420 pixel encoding.

Signed-off-by: Mikita Lipski <mikita.lipski@amd.com>
Tested-by: Mike Lothian <mike@fireburn.co.uk>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:04 -05:00
Darren Powell 87e3f1366e drm/amd: Remove errors from sphinx documentation
Eliminating the warnings produced by sphinx when processing the sphinx comments in
 amdgpu_device.c & amdgpu_mn.c

Signed-off-by: Darren Powell <darren.powell@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:03 -05:00
Gustavo A. R. Silva 6f3472a993 drm/amd/display/dc/dce: Fix multiple potential integer overflows
Add suffix ULL to constant 5 and cast variables target_pix_clk_khz and
feedback_divider to uint64_t in order to avoid multiple potential integer
overflows and give the compiler complete information about the proper
arithmetic to use.

Notice that such constant and variables are used in contexts that
expect expressions of type uint64_t (64 bits, unsigned). The current
casts to uint64_t effectively apply to each expression as a whole,
but they do not prevent them from being evaluated using 32-bit
arithmetic instead of 64-bit arithmetic.

Also, once the expressions are properly evaluated using 64-bit
arithmentic, there is no need for the parentheses that enclose
them.

Addresses-Coverity-ID: 1460245 ("Unintentional integer overflow")
Addresses-Coverity-ID: 1460286 ("Unintentional integer overflow")
Addresses-Coverity-ID: 1460401 ("Unintentional integer overflow")
Fixes: 4562236b3b ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Gustavo A. R. Silva <gustavo@embeddedor.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:03 -05:00
Kees Cook 4c1ac53eb8 drm/amd/display: Use 2-factor allocator calls
As already done treewide, switch from open-coded multiplication to
2-factor allocation helper.

Signed-off-by: Kees Cook <keescook@chromium.org>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:03 -05:00
Harry Wentland 25177e7f94 Revert "drm/amd/display: Fix indentation in dcn10 resource constructor"
That change was a merge gone bad.

This reverts commit cb1d7eacb5.

Signed-off-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:02 -05:00
Dan Carpenter 5d908944c5 drm/amd/display: off by one in find_irq_source_info()
The ->info[] array has DAL_IRQ_SOURCES_NUMBER elements so this condition
should be >= instead of > or we could read one element beyond the end of
the array.

Fixes: 4562236b3b ("drm/amd/dc: Add dc display driver (v2)")
Signed-off-by: Dan Carpenter <dan.carpenter@oracle.com>
Reviewed-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:02 -05:00
Rex Zhu 20582319bc drm/amd/pp: Remove the same struct define in powerplay
delete the same struct define in powerplay, share the struct
with display.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:02 -05:00
Rex Zhu 70b63170c3 drm/amd/display: Fix copy error when set memory clocks
Set memory clocks same as soc clocks

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:01 -05:00
Rex Zhu b0a634ac68 drm/amd/display: Refine the implementation of dm_pp_get_funcs_rv
powerplay/dpm export all interfaces in struct amd_pm_funcs.
so call common exported interfaces instead of powerplay inner interfaces

Also not include header file hwmgr.h

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:01 -05:00
Rex Zhu ea870e4441 drm/amd/pp: Export notify_smu_enable_pwe to display
Display can notify smu to enable pwe after gpu suspend.
It is used in case when display resumes from S3 and wants to start
audio driver by enabling pwe

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:00 -05:00
Alex Deucher 289278cb7d drm: drop drm_pcie_get_speed_cap_mask and drm_pcie_get_max_link_width
These functions duplicated functionality which was ultimately added
to the pci core.

All users of these functions have been ported to using the newly
exposed pci functionality.  These functions are no longer used,
so drop them.

Acked-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Dave Airlie <airlied@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:00 -05:00
Alex Deucher 5f152a572c drm/radeon: use pcie functions for link width
This is the last user of drm_pcie_get_speed_cap_mask.  Use the pci
version so we can drop drm_pcie_get_speed_cap_mask.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:40:00 -05:00
Alex Deucher 5d9a633040 drm/amdgpu: use pcie functions for link width and speed
Use the newly exported pci functions to get the link width
and speed rather than using the drm duplicated versions.

Also query the GPU link caps directly rather than hardcoding
them.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:59 -05:00
Alex Deucher 4976f1c8cc drm/amdgpu: update amd_pcie.h to include gen4 speeds
Internal header used by the driver to specify pcie gen
speeds of the asic and chipset.

Acked-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:59 -05:00
Alex Deucher 576c7218a1 PCI: Export pcie_get_speed_cap and pcie_get_width_cap
So drivers can use them.  This can be used to replace
duplicate code in the drm subsystem.

Acked-by: Christian König <christian.koenig@amd.com>
Acked-by: Bjorn Helgaas <bhelgaas@google.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:59 -05:00
Alex Deucher 8eaf2b1faa drm/amdgpu: switch firmware path for SI parts
Use separate firmware path for amdgpu to avoid conflicts
with radeon on SI parts.

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:58 -05:00
Alex Deucher ce206464e3 drm/amdgpu: switch firmware path for CIK parts (v2)
Use separate firmware path for amdgpu to avoid conflicts
with radeon on CIK parts.

v2: squash in logic simplification (Alex)

Reviewed-by: Chunming Zhou <david1.zhou@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:58 -05:00
Nicolai Hähnle 9fc15f5fc8 drm/amdgpu: fix user fence write race condition
The buffer object backing the user fence is reserved using the non-user
fence, i.e., as soon as the non-user fence is signaled, the user fence
buffer object can be moved or even destroyed.

Therefore, emit the user fence first.

Both fences have the same cache invalidation behavior, so this should
have no user-visible effect.

Signed-off-by: Nicolai Hähnle <nicolai.haehnle@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:57 -05:00
Rex Zhu 860c15e903 drm/amd/pp: Remove duplicate code in vega12_hwmgr.c
use smu_helper function smu_set_watermarks_for_clocks_ranges
in vega12_set_watermarks_for_clocks_ranges.

Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:57 -05:00
Rex Zhu 99c5e27d33 drm/amd/pp: Refine the interface exported to display
use void * as function parameter type in order for extension.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:57 -05:00
rex zhu d4d5eace21 drm/amd/display: Notify powerplay the display controller id
powerplay can recalculate the number of active display

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:56 -05:00
rex zhu 3180fb676d drm/amd/display: Notify powerplay the min_dcef clock
powerplay can notify smu to recalculates the maximum deep-sleep
divider display allowed.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:56 -05:00
rex zhu 7d8d968dac drm/amd/pp: Switch the tolerable latency for display
Select the lowest MCLK frequency that is within
the tolerable latency defined in DISPALY

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:56 -05:00
Rex Zhu 6eb9d60304 drm/amd/pp: Memory Latency is always 25us on Vega10
For HBM, 25us latency is enough for memory clock switch.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:55 -05:00
Rex Zhu 23ec3d1479 drm/amd/pp: Convert clock unit to KHz as defined
Convert clock unit 10KHz to KHz as the data sturct defined.
e.g.
struct pp_clock_with_latency {
	uint32_t clocks_in_khz;
	uint32_t latency_in_us;
};
Meanwhile revert the same conversion in display side.

Acked-by: Alex Deucher <alexander.deucher@amd.com>
Acked-by: Harry Wentland <harry.wentland@amd.com>
Signed-off-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:55 -05:00
Alex Deucher afb1436c7b drm/amdgpu: update uvd_v6_0_ring_vm_funcs to use new nop packet
Was missed when updating the uvd 6 module.

Fixes: 1aac3c9180 (drm/amdgpu: fix insert nop for UVD6 ring)
Reviewed-by: Leo Liu <leo.liu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
Cc: stable@vger.kernel.org
2018-07-05 16:39:54 -05:00
Huang Rui f8ddb39a15 drm/amdgpu: fix the wrong type of gem object creation
We still use legacy type of gem_object_create, it should update to ttm_bo_type
now.

Signed-off-by: Huang Rui <ray.huang@amd.com>
Reviewed-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:54 -05:00
Dirk Hohndel (VMware) da5fd66c0e drm/radeon: add SPDX identifier and clarify license
This is dual licensed under GPL-2.0 or MIT.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:54 -05:00
Dirk Hohndel (VMware) 9f87830f61 drm/amd: add SPDX identifier and clarify license
This is dual licensed under GPL-2.0 or MIT.

Acked-by: Thomas Gleixner <tglx@linutronix.de>
Signed-off-by: Dirk Hohndel (VMware) <dirk@hohndel.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:53 -05:00
Thomas Zimmermann c3c18309c8 drm/amd: Replace drm_dev_unref with drm_dev_put
This patch unifies the naming of DRM functions for reference counting
of struct drm_device. The resulting code is more aligned with the rest
of the Linux kernel interfaces.

Signed-off-by: Thomas Zimmermann <contact@tzimmermann.org>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:53 -05:00
Alex Deucher 5d4af988f3 drm/amdgpu/vce: simplify vce instance setup
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer.

Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:53 -05:00
Alex Deucher 1cf0abb6c9 drm/amdgpu/sdma: simplify sdma instance setup
Set the me instance in early init and use that rather than
calculating the instance based on the ring pointer.

Reviewed-by: James Zhu <James.Zhu@amd.com>
Reviewed-by: Leo Liu <leo.liu@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:52 -05:00
Alex Deucher ed54d954e5 drm/amdgpu/pp: fix copy paste typo in smu7_get_pp_table_entry_callback_func_v1
Should be using PCIELaneLow for the low clock level.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:52 -05:00
Alex Deucher 9861023c29 drm/amdgpu/pp: fix copy paste typo in smu7_init_dpm_defaults
Should be mclk rather than sclk.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:52 -05:00
Alex Deucher 594c34cc6f drm/amdgpu/pp: fix endian swapping in atomctrl_get_voltage_range
Need to swap before doing arthimetic on the values.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:51 -05:00
Alex Deucher c9037d4439 drm/amdgpu/pp: add missing byte swapping in process_pptables_v1_0.c
Values need to be swapped on big endian.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:51 -05:00
Alex Deucher 70eb46db10 drm/amdgpu/pm: fix display count in non-DC path
new_active_crtcs is a bitmask, new_active_crtc_count is the
actual count.

Reviewed-by: Rex Zhu <Rex.Zhu@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:50 -05:00
Alex Deucher 3413accb3e drm/amdgpu: fix swapped emit_ib_size in vce3
The phys and vm versions had the values swapped.

Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:50 -05:00
Michel Dänzer 3f37e29626 drm/amdgpu: Remove amdgpu_gem_map_attach target_dev documentation
The parameter was removed.

Fixes: a19741e5e5 "dma_buf: remove device parameter from attach
                     callback v2"
Reviewed-by: Junwei Zhang <Jerry.Zhang@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:50 -05:00
Michel Dänzer 463d2fe85b drm/amdgpu: Add AMDGPU_GPU_PAGES_IN_CPU_PAGE define
To hopefully make the code dealing with GPU vs CPU pages a little
clearer.

Suggested-by: Christian König <christian.koenig@amd.com>
Reviewed-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:49 -05:00
Michel Dänzer 9735bf1930 drm/amdgpu: Use gmc_vram_full_visible in vram_mgr_bo_invisible_size
Signed-off-by: Michel Dänzer <michel.daenzer@amd.com>
Reviewed-by: Christian König <christian.koenig@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:39:49 -05:00
Lyude Paul 280cf1a94b drm/amdgpu: Dynamically probe for ATIF handle (v2)
The other day I was testing one of the HP laptops at my office with an
i915/amdgpu hybrid setup and noticed that hotplugging was non-functional
on almost all of the display outputs. I eventually discovered that all
of the external outputs were connected to the amdgpu device instead of
i915, and that the hotplugs weren't being detected so long as the GPU
was in runtime suspend. After some talking with folks at AMD, I learned
that amdgpu is actually supposed to support hotplug detection in runtime
suspend so long as the OEM has implemented it properly in the firmware.

On this HP ZBook 15 G4 (the machine in question), amdgpu wasn't managing
to find the ATIF handle at all despite the fact that I could see acpi
events being sent in response to any hotplugging. After going through
dumps of the firmware, I discovered that this machine did in fact
support ATIF, but that it's ATIF method lived in an entirely different
namespace than this device's handle (the device handle was
\_SB_.PCI0.PEG0.PEGP, but ATIF lives in ATPX's handle at
\_SB_.PCI0.GFX0).

So, fix this by probing ATPX's ACPI parent's namespace if we can't find
ATIF elsewhere, along with storing a pointer to the proper handle to use
for ATIF and using that instead of the device's handle.

This fixes HPD detection while in runtime suspend for this ZBook!

v2: Update the comment to reflect how the namespaces are arranged
based on the system configuration. (Alex)

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:58 -05:00
Lyude Paul 24aeefcdee drm/amdgpu: Add amdgpu_atpx_get_dhandle()
Since it seems that some vendors are storing the ATIF ACPI methods under
the same handle that ATPX lives under instead of the device's own
handle, we're going to need to be able to retrieve this handle later so
we can probe for ATIF there.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:58 -05:00
Lyude Paul aa03c075d0 drm/amdgpu: s/disp_detetion_ports/disp_detection_ports/
Fix typo.

Reviewed-by: Jim Qu <Jim.Qu@amd.com>
Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:57 -05:00
Lyude Paul 102c16a024 drm/amdgpu: Make struct amdgpu_atif private to amdgpu_acpi.c
Currently, there is nothing in amdgpu that actually uses these structs
other than amdgpu_acpi.c. Additionally, since we're about to start
saving the correct ACPI handle to use for calling ATIF in this struct
this saves us from having to handle making sure that the acpi_handle
(and by proxy, the type definition for acpi_handle and all of the other
acpi headers) doesn't need to be included within the amdgpu_drv struct
itself. This follows the example set by amdgpu_atpx_handler.c.

Signed-off-by: Lyude Paul <lyude@redhat.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:57 -05:00
Evan Quan 0c3d017445 drm/amd/powerplay: cosmetic fix
Fix coding style and drop unused variable.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan 6ad87101f3 drm/amd/powerplay: correct vega12 thermal support as true
Thermal support is enabled on vega12.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan 28a7b4f449 drm/amd/powerplay: set vega12 pre display configurations
Set num_displays to 0 and force uclk high as part of the mode
set sequence.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:56 -05:00
Evan Quan e17c7f92b2 drm/amd/powerplay: apply clocks adjust rules on power state change
This add the apply_clocks_adjust_rules callback which is used
to validate the clock settings on a power state change.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:55 -05:00
Evan Quan a0a59c8fc7 drm/amd/powerplay: correct vega12 max num of dpm level
Use MAX_NUM_CLOCKS instead of VG12_PSUEDO* macros for
the max number of dpm levels.

Signed-off-by: Evan Quan <evan.quan@amd.com>
Acked-by: Alex Deucher <alexander.deucher@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
2018-07-05 16:38:55 -05:00