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659 Commits

Author SHA1 Message Date
Aurelien Jarno dcc65026c4 target-arm: fix bugs introduced by 1b2b1e547b 
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-18 16:00:18 +02:00
Aurelien Jarno 98a463171b target-arm: fix bugs introduced by 3174f8e91f 
Use load_reg_var() instead of accessing cpu_R[rn] directly to generate
correct code when rn = 15.

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-18 15:53:28 +02:00
Aurelien Jarno b567b38c2c target-arm: remove T0 and T1 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:53:08 +02:00
Filip Navara 747a651e8e target-arm: remove cpu_T for ARM once and for all 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:18 +02:00
Filip Navara 312eea9f99 target-arm: convert VFP not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara da6b5335d5 target-arm: convert disas_iwmmxt_insn not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 3a554c0f20 target-arm: convert disas_dsp_insn not use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 1b2b1e547b target-arm: convert disas_neon_ls_insn not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara dd8fbd787e target-arm: convert disas_neon_data_insn and helpers not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 3174f8e91f target-arm: convert rest of disas_arm_insn / disas_thumb2_insn not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 396e467cb1 target-arm: replace thumb usage of cpu_T registers by proper register allocations 
The goal is eventually to get rid of all cpu_T register usage and to use
just short-lived tmp/tmp2 registers. This patch converts all the places where
cpu_T was used in the Thumb code and replaces it with explicit TCG register
allocation.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 15bb4eac12 target-arm: fix TANDC and TORC instructions 
Uninitialized register was used instead of proper TCG variable.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 194576157a target-arm: convert NEON VZIP/VUZP/VTRN helper functions to pure TCG 
The neon_trn_u8, neon_trn_u16, neon_unzip_u8, neon_zip_u8 and neon_zip_u16
helpers used fixed registers to return values. This patch replaces that with
TCG code, so T0/T1 is no longer directly used by the helper functions.

Bugs in the gen_neon_unzip register load code were also fixed.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara a6445c52aa target-arm: convert gen_lookup_tb not to use cpu_T 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:17 +02:00
Filip Navara 2fbac54be0 target-arm: get rid of gen_set_psr_T0 and replace it by gen_set_psr/gen_set_psr_im 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Filip Navara c67b6b719b target-arm: fix SRS/RFE instructions 
The encoding of 'IA' and 'DB' conditions was swapped.
SRS instruction must store banked SPSR instead of CPSR at the specific address.
Missing 'return' statement at the end of RFE handling.
Fixed write-back code to reference correct registers.

From: Hyeonsung Jang <hsjang@ok-labs.com>
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Filip Navara 217aff9c76 target-arm: remove unused gen_movl_T2_reg function 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Filip Navara 288eebe54f target-arm: remove useless line that sets register that is never used again 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Filip Navara 12edd4f269 target-arm: get rid of temporary variable cache 
The temporary variable cache in no longer need since tcg_temp_free was introduced.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Filip Navara 155c3eacd2 target-arm: use tcg_global_mem_new_i32 to allocate registers 
Currently each read/write of ARM register involves a LD/ST TCG operation. This
patch uses TCG memory-backed registers to represent the ARM register set. With
memory-backed registers the LD/ST operations are transparently generated by TCG
and host registers could be used to optimize the generated code.

Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
 2009-10-17 23:52:16 +02:00
Anthony Liguori c227f0995e Revert "Get rid of _t suffix" 
In the very least, a change like this requires discussion on the list.

The naming convention is goofy and it causes a massive merge problem.  Something
like this _must_ be presented on the list first so people can provide input
and cope with it.

This reverts commit 99a0949b72.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-10-01 16:12:16 -05:00
malc 99a0949b72 Get rid of _t suffix 
Some not so obvious bits, slirp and Xen were left alone for the time
being.

Signed-off-by: malc <av1474@comtv.ru>
 2009-10-01 22:45:02 +04:00
Blue Swirl 72cf2d4f0e Fix sys-queue.h conflict for good 
Problem: Our file sys-queue.h is a copy of the BSD file, but there are
some additions and it's not entirely compatible. Because of that, there have
been conflicts with system headers on BSD systems. Some hacks have been
introduced in the commits 15cc923584,
f40d753718,
96555a96d7 and
3990d09adf but the fixes were fragile.

Solution: Avoid the conflict entirely by renaming the functions and the
file. Revert the previous hacks.

Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-09-12 07:36:22 +00:00
Nathan Froyd 0b5c1ce846 cleanup cpu-exec.c, part 0/N: consolidate handle_cpu_signal 
handle_cpu_signal is very nearly copy-paste code for each target, with a
few minor variations.  This patch sets up appropriate defaults for a
generic handle_cpu_signal and provides overrides for particular targets
that did things differently.  Fixing things like the persistent (XXX:
use sigsetjmp) should now become somewhat easier.

Previous comments on this patch suggest that the "activate soft MMU for
this block" comments refer to defunct functionality.  I have removed
such blocks for the appropriate targets in this patch.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-08-24 08:21:42 -05:00
Paul Brook ffe47d331d Save/restore ARMv6 MMU state 
Correctly save/restore ARMV6 MMU state.

Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-07-31 13:19:39 +01:00
Juan Quintela e2542fe2bc rename WORDS_BIGENDIAN to HOST_WORDS_BIGENDIAN 
Signed-off-by: Juan Quintela <quintela@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-07-27 14:09:21 -05:00
Blue Swirl 8167ee8839 Update to a hopefully more future proof FSF address 
Signed-off-by: Blue Swirl <blauwirbel@gmail.com>
 2009-07-16 20:47:01 +00:00
Filip Navara 024589f182 Remove unused gen_bx_T0 function. 
Signed-off-by: Filip Navara <filip.navara@gmail.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-06-24 09:09:15 -05:00
Anthony Liguori f80f9ec9a6 Convert machine registration to use module init functions 
This cleans up quite a lot of #ifdefs, extern variables, and other ugliness.

Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>
 2009-05-21 08:47:55 -05:00
Juha Riihimäki 21aeb3430c fix ARMv7 data processing instructions 
ARMv7 defines a new behavior for ARM data processing instructions
compared to earlier architecture revisions; when the destination
register is R15, a Branch and Exchange operation is executed rather
than a simple Branch to the target address. This patch corrects the
behavior of the emulation for the aforementioned operations. To be
applied after applying the previous patch in this patch set.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-05-15 03:18:42 +01:00
Juha Riihimäki e9bb4aa977 fix ARMv7 data processing instructions 
Modernize parts of target-arm/translate.c in preparation for the
modifications in the subsequent patch in this patch set. This is done
in order to avoid writing new code to target-arm/translate.c that
would use deprecated methods and/or variables.

Signed-off-by: Juha Riihimäki <juha.riihimaki@nokia.com>
Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-05-15 02:48:18 +01:00
Paul Brook 4af396115a Syborg (Symbian Virtual Platform) board 
A virtual reference platform for SymbianOS development/debugging.

Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-05-14 23:11:09 +01:00
Paul Brook cb76e138d3 Fixe ARM NEON vrshl. 
Signed-off-by: Paul Brook <paul@codesourcery.com>
 2009-05-09 23:12:06 +01:00
aliguori 0bf46a40a1 qemu: introduce qemu_init_vcpu (Marcelo Tosatti) 
Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7242 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-24 18:03:41 +00:00
aliguori 6a4955a813 qemu: per-arch cpu_has_work (Marcelo Tosatti) 
Blue Swirl: fix Sparc32 breakage

Signed-off-by: Marcelo Tosatti <mtosatti@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7238 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-24 18:03:20 +00:00
aurel32 37f9ba4600 target-arm: don't use T[x] in helper 
(Torbjörn Andersson)

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7034 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-07 22:48:36 +00:00
aurel32 1b530a6dfc Add new command line option -singlestep for tcg single stepping. 
This replaces a compile time option for some targets and adds
this feature to targets which did not have a compile time option.

Add monitor command to enable or disable single step mode.

Modify monitor command "info status" to display single step mode.

Signed-off-by: Stefan Weil <weil@mail.berlios.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@7004 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-04-05 20:08:59 +00:00
pbrook cbbccffc7a Fix ARM quadword VDUP (core register). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6857 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-17 12:19:58 +00:00
aurel32 66896cb803 tcg: rename bswap_i32/i64 functions 
Rename bswap_i32 into bswap32_i32 and bswap_i64 into bswap64_i64

Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6829 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-13 09:34:48 +00:00
aurel32 533d177a98 Fix correct reset value for ARM CP15 c1 auxiliary control register 
According to ARM Cortex A8 Technical Reference Manual, the reset value for CP15 c1 auxiliary control
register is 2, not zero (page 3.12).

Signed-off-by: Riku Voipio <riku.voipio@iki.fi>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6771 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-07 22:10:28 +00:00
aurel32 2b3ea3154d clean build: Fix arm build warnings 
Fix remaining arm warnings - except for the mess in the NetWinder FP
emulator.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6766 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-07 21:48:00 +00:00
pbrook c276471991 The _exit syscall is used for both thread termination in NPTL applications, 
and process termination in legacy applications.  Try to guess which we want
based on the presence of multiple threads.

Also implement locking when modifying the CPU list.


Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6735 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-03-07 15:24:59 +00:00
aurel32 84a031c68f Fix cpu_arm_handle_mmu_fault warning 
This patch fixes:

/scratch/froydnj/qemu.git/target-arm/helper.c:451: warning: no previous prototype for 'cpu_arm_handle_mmu_fault'

by moving the declaration of the function to cpu.h from exec.h.  cpu.h
seems to be the place most other ports declare the corresponding
function.

Signed-off-by: Nathan Froyd <froydnj@codesourcery.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6550 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-07 15:19:20 +00:00
aliguori 0d0266a53b targets: remove error handling from qemu_malloc() callers (Avi Kivity) 
Signed-off-by: Avi Kivity <avi@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6530 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-02-05 22:06:11 +00:00
aliguori eca1bdf415 Log reset events (Jan Kiszka) 
Original idea&code by Kevin Wolf, split-up in two patches and added more
archs.

This patch introduces a flag to log CPU resets. Useful for tracing
unexpected resets (such as those triggered by x86 triple faults).

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6452 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-26 19:54:31 +00:00
aliguori 8fec2b8c45 global s/loglevel & X/qemu_loglevel_mask(X)/ (Eduardo Habkost) 
These are references to 'loglevel' that aren't on a simple 'if (loglevel &
X) qemu_log()' statement.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6340 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-15 22:36:53 +00:00
aliguori 93fcfe39a0 Convert references to logfile/loglevel to use qemu_log*() macros 
This is a large patch that changes all occurrences of logfile/loglevel
global variables to use the new qemu_log*() macros.

Signed-off-by: Eduardo Habkost <ehabkost@redhat.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6338 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-15 22:34:14 +00:00
aurel32 fad6cb1a56 Update FSF address in GPL/LGPL boilerplate 
The attached patch updates the FSF address in the GPL/LGPL boilerplate
in most GPL/LGPLed files, and also in COPYING.LIB.

Signed-off-by: Stuart Brady <stuart.brady@gmail.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6162 c046a42c-6fe2-441c-8c8c-71466251a162
 2009-01-04 22:05:52 +00:00
pbrook fe76d97653 Implement flush-to-zero mode (denormal results are replaced with zero). 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6107 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 14:33:59 +00:00
pbrook 5c7908ed23 Implement default-NaN mode. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6106 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 13:53:37 +00:00
pbrook a49ea279c4 Implement ARMv7 cp15 cache ID registers. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6105 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 13:37:53 +00:00
pbrook fe1479c3ad Implement (very) basic Thumb2-EE support. This doesn't actually implement 
EE state, just the associated system coprocessor registers.  It is sufficient
to keep OS setup and context switching code happy.

Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6104 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 13:18:36 +00:00
pbrook 644ad8066d Fix VFP fixed point conversion routines. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6103 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 13:02:08 +00:00
pbrook d4934d18f3 Implement ARMv7 MMU access permissions. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6099 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-19 12:39:00 +00:00
balrog 997641a84f ARM: basic SX1-cellphone sysemu support (Jean-Christophe PLAGNIOL-VILLARD). 
The TSC2102 chip is not included in documentation because a patch is
pending.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6038 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-15 02:05:00 +00:00
blueswir1 1d6198c3b0 Remove unnecessary trailing newlines 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@6000 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-13 09:32:43 +00:00
aurel32 db8d990204 Remove FORCE_RET() and RETURN() 
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5923 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 18:15:54 +00:00
balrog 955a7dd5e8 ARM: fix smmul and smmla/smmls usage of registers (Mans Rullgard). 
This fixes the destination and accumulator registers for the smmul
and smmla instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Acked-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5913 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 14:18:02 +00:00
balrog ded9d29547 ARM: fix usad8 and usada8 usage of registers (Mans Rullgard). 
This fixes the destination and accumulator registers for the usad8
and usada8 instructions.

Signed-off-by: Mans Rullgard <mans@mansr.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5912 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 14:03:27 +00:00
balrog 4cc633c38b Patch holes in ARM translation (Laurent Desnogues). 
- gen_set_CF_bit31:  use the right value to set carry flag
 - shifter_out_im:  remove a spurious semi-colon
 - add a break for VSHRN, VRSHRN, VQSHRN, VQRSHRN
   size 2 case
 - sbfx, ubfx are v6t2 instructions

The correct cps user mode behaviour is unclear so it's left out from the
commit until ARM decides it.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5908 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 13:32:09 +00:00
balrog aaf2d97dcb ARM: cosmetics (Laurent Desnogues). 
- remove macros that are not used
  - remove disass structure is_mem field which value is never used
  - correct a typo in a comment.

Signed-off-by: Laurent Desnogues <laurent.desnogues@gmail.com>
Signed-off-by: Andrzej Zaborowski <andrew.zaborowski@intel.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5907 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-12-07 13:20:16 +00:00
aurel32 2cbd949d7a Common cpu_loop_exit prototype 
All archs use the same cpu_loop_exit, so move the prototype in a common
header. i386 was carrying a __hidden attribute, but that was empty for
this arch anyway.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>

git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5820 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-30 16:23:09 +00:00
aliguori c0ce998e94 Use sys-queue.h for break/watchpoint managment (Jan Kiszka) 
This switches cpu_break/watchpoint_* to TAILQ wrappers, simplifying the
code and also fixing a use after release issue in
cpu_break/watchpoint_remove_all.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-25 22:13:57 +00:00
aliguori bfa50bc263 Remove premature memop TB terminations (Jan Kiszka) 
Now that we can properly restore the pc on watchpoint hits, there is no
more need for prematurely terminating TBs if watchpoints are present.
Remove all related bits.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5742 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 20:26:41 +00:00
aliguori a1d1bb3101 Refactor and enhance break/watchpoint API (Jan Kiszka) 
This patch prepares the QEMU cpu_watchpoint/breakpoint API to allow the
succeeding enhancements this series comes with.

First of all, it overcomes MAX_BREAKPOINTS/MAX_WATCHPOINTS by switching
to dynamically allocated data structures that are kept in linked lists.
This also allows to return a stable reference to the related objects,
required for later introduced x86 debug register support.

Breakpoints and watchpoints are stored with their full information set
and an additional flag field that makes them easily extensible for use
beyond pure guest debugging.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5738 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 20:07:32 +00:00
aliguori 6b9175478e Refactor translation block CPU state handling (Jan Kiszka) 
This patch refactors the way the CPU state is handled that is associated
with a TB. The basic motivation is to move more arch specific code out
of generic files. Specifically the long #ifdef clutter in tb_find_fast()
has to be overcome in order to avoid duplicating it for the gdb
watchpoint fixes (patch "Restore pc on watchpoint hits").

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5736 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 19:46:41 +00:00
aliguori 622ed3605b Convert CPU_PC_FROM_TB to static inline (Jan Kiszka) 
as macros should be avoided when possible.

Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
Signed-off-by: Anthony Liguori <aliguori@us.ibm.com>



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5735 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-18 19:36:03 +00:00
pbrook a7812ae412 TCG variable type checking. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5729 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-17 14:43:54 +00:00
pbrook c9fb531ab2 VFP fnmsc negative zero fix. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5610 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-11-03 19:09:29 +00:00
blueswir1 b1d8e52e63 Fix undeclared symbol warnings from sparse 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5539 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-26 13:43:07 +00:00
pbrook a47f43d272 Additional exclusive load/store instruction are v6K, not v6T2. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5518 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-22 21:42:54 +00:00
pbrook 86753403b2 Fix ARMv6t2 strex instructions. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5517 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-22 20:35:54 +00:00
pbrook b2fa17977f Fix ARMv6 translation table base address calculation. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5514 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-22 19:22:30 +00:00
pbrook 4be27dbbde Optimize redundant cp15 coprocessor access control register writes. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5512 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-22 16:14:08 +00:00
pbrook 56aebc8916 Add GDB XML register description support. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5459 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-10-11 17:55:29 +00:00
pbrook 3018f2598c Fix ARM NEON vdup and vtbl bugs. 
Signed-off-by: Paul Brook <paul@codesourcery.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5286 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-22 00:52:42 +00:00
pbrook e4b3861d15 Fix neon encoding comment. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5285 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-21 23:15:38 +00:00
pbrook 36aa55dcd9 Add concat_i32_i64 op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5280 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-21 13:48:32 +00:00
balrog b40d0353b0 Fix QADD / QSUB decoding on ARM (Torbjörn Andersson). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5273 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-09-20 03:18:07 +00:00
blueswir1 79383c9c08 Fix some warnings that would be generated by gcc -Wredundant-decls 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@5115 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-08-30 09:51:20 +00:00
balrog a87aa10b85 ARMv6: fix SIMD add/sub carry flags (Vincent Palatin). 
After a quick code review, it seems to be a bad cut-n-paste between
16-bit and 8-bit UADD/USUB, indeed UADD8/USUB8 tries to set GE bits by
pair instead of one at a time.
Besides, the addition operations (UADD8/UADD16) set GE bits to "NOT
carry" instead of "carry" (probably once again due to a copy of the
substraction code which sets flags to "NOT borrow")


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4900 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 10:46:13 +00:00
balrog 7997d92f2c ARM: fix CPS masks (Vincent Palatin). 
According to ARM Reference Manual (DDI0100 A4.1.16),
bit 5 is fixed to 0 (bit 4 is the MSB of the mode), so the instruction mask
should be  0x0ff10020 not 0x0ff10010.
Besides, mmod flag is bit 17 (b14 is SBZ)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4899 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 10:34:35 +00:00
balrog 22478e79f2 Fix smlald, smlsld, pkhtp, pkhbt, ssat, usat, umul, smul... (Laurent Desnogues). 
helper.c
 - copy reference c0_c2 to runtime c0_c2 and not c0_c1

op_helper.c
 - remove old code (PARAM1, probably some left over from old dyngen)
   that broke do_[us]sat

translate.c
 - gen_smul_dual should sign-extend from 16 bit to 32 bit and not from
   8 to 32
 - disas_arm_insn:
   * smlalxy:  that was completely wrong;  now the addition is
     performed as for smlald
   * pkhtb:  optional ASR not taken into account (similar
   * to [us]sat)
   * pkhtb/pkhbt: tmp2 is dead
   * smlald, smlsld, smuad, smusd, smlad, smlsd: rd
   * and rn swapped


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4898 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-19 10:12:22 +00:00
ths 2cfc5f17d3 Small cleanup of gen_intermediate_code(_internal), by Laurent Desnogues. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4891 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-18 18:01:29 +00:00
pbrook d60bb01cbb Terminate TB immediately after v7-M exception return. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4868 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-11 00:27:19 +00:00
ths 551bd27f22 Convert remaining __builtin_expect to likely/unlikely, by Jan Kiszka. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4840 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 17:57:36 +00:00
ths 06e80fc927 Silence compiler warning. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4839 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-03 16:40:06 +00:00
pbrook ab19b0ecfd ARMv7-M interrupt stack alignment fix. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4823 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-02 16:44:09 +00:00
pbrook 9656f324d2 Move interrupt_request and user_mode_only to common cpu state. 
Save and restore env->interrupt_request and env->halted.



git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4817 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-07-01 20:01:19 +00:00
ths bf20dc076b Spelling fixes, spotted by Stuart Brady. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4809 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-30 17:22:19 +00:00
pbrook b3c7724cbc Move CPU save/load registration to common code. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4808 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-30 16:31:04 +00:00
pbrook a50f5b9186 Suppress bogus compiler warnings. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4803 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 15:25:29 +00:00
pbrook 2e70f6efa8 Add instruction counter. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4799 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-29 01:03:05 +00:00
balrog a60de94777 Mark a dead_tmp as such in ARM msr. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4648 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-02 02:29:26 +00:00
balrog 89cdb6af04 Provide basic emulation for Sharp SL-6000 PDA (Tosa), Dmitry Baryshkov. 
This adds basic support for emulating Sharp Zaurus SL-6000 PDA (tosa).
Currently it provides only basic support: no kbd/lcd, sound, ts, etc.
But it's able at least to boot Linux from CF.

Signed-off-by: Dmitry Baryshkov <dbaryshkov@gmail.com>


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4643 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-06-02 01:33:11 +00:00
pbrook f8ed7070ea Fix typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4624 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 17:54:15 +00:00
pbrook 6e68e076e7 Move clone() register setup to target specific code. Handle fork-like clone. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4623 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-30 17:22:15 +00:00
bellard 9133e39b84 Push common interrupt variables to cpu-defs.h (Glauber Costa) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4612 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-29 10:08:06 +00:00
pbrook fbb4a2e371 Implement ARM magic kernel page and TLS register. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4610 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-29 00:20:44 +00:00
bellard ce5232c5c2 moved halted field to CPU_COMMON 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4609 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-28 17:14:10 +00:00
pbrook 9b7b85d260 Fix off-by-one unwinding error. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4570 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-25 00:36:06 +00:00
pbrook cb63669a54 Fix ARM conditional branch bug. 
Add tcg_gen_brcondi.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4552 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-24 02:22:00 +00:00
balrog c30bb26499 Add N810 to allowed -M values, add documentation part for N8x0. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4490 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-18 13:01:40 +00:00
balrog 4aa9aca4c2 Remove arm's local not_i32 tcg op now that there's one in tcg. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4475 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-17 18:15:04 +00:00
pbrook 390efc54fb Add TCG native negation op. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4426 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 14:35:37 +00:00
pbrook 868314358e Add zero extension (pseudo-)ops. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4424 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-11 12:22:01 +00:00
aurel32 8dd3dca351 remove target ifdefs from vl.c 
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4327 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-04 13:11:44 +00:00
pbrook 460a09c1fb Fix incorrect argument types. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4291 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-05-01 12:04:35 +00:00
aurel32 d2856f1ad4 Factorize code in translate.c 
(Glauber Costa)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4274 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-28 00:32:32 +00:00
balrog 601d70b9e5 Remove an unused field and fix some non-code typos. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4222 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-20 01:03:45 +00:00
balrog 66230e0dee Correct more ARM VFP 32/64 and signed/unsigned typos. 
Fixes unreadable fonts in Maemo guest.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4221 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-20 00:58:01 +00:00
balrog 422ebf6979 Save the exact SWI return address in Thumb mode. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4217 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-16 23:17:02 +00:00
balrog 827df9f3c5 Add basic OMAP2 chip support. 
Add the OMAP242x (arm1136 core) initialisation with basic on-chip
peripherals and update OMAP1 peripherals which are re-used in OMAP2.
Make palmte.c and sd.c errors go to stderr.
Allow disabling SD chipselect.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4213 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-14 21:05:22 +00:00
balrog f93eb9ff66 Move the excess of arm_load_kernel() parameters into a struct. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4212 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-14 20:27:51 +00:00
balrog e22f8f39f3 Correctly restore pc after an exception occured in Thumb mode. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4211 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-14 19:14:06 +00:00
balrog 5b340b51fd Fix ARM VFP related segfaults. 
The fconst change is partly a guess.
VFP_OP1 is still unused.
An ARMv6 target still won't boot.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4210 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-14 02:19:57 +00:00
balrog 6a0d8a1d23 Fix the offset in Thumb bl instruction. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4204 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-13 13:25:31 +00:00
balrog 2637a3beb9 Set an unset label in ARM strex. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4203 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-13 03:15:14 +00:00
balrog 72f1c62f7d Fix ARM and Thumb ldlex/stlex. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4202 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-13 01:53:27 +00:00
balrog 6c95676b16 Store the right TCG temp (typo). 
Stops ARMv6 target from segfaulting early.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4201 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-13 00:57:49 +00:00
aurel32 ca10f86763 Remove osdep.c/qemu-img code duplication 
(Kevin Wolf)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4191 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 21:35:42 +00:00
aurel32 1654b2d6bf Fix few spelling issues in comments 
(Stefan Weil)


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4187 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-11 04:55:07 +00:00
aurel32 3ebdd11939 Move target-arm/nwfpe into linux-user/arm/nwfpe 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4185 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-09 06:53:01 +00:00
aurel32 6d9a42be17 Implement ARM floating point exception emulation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4166 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-07 20:30:53 +00:00
pbrook 6fbe23d50e ARM N=Z=1 flag fix. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4156 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-04-01 17:19:11 +00:00
pbrook 663715fbe2 ARM TCG conversion 16/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4153 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:49:36 +00:00
pbrook e677137d99 ARM TCG conversion 15/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4152 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:49:05 +00:00
pbrook ad69471ce5 ARM TCG conversion 14/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4151 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:48:30 +00:00
pbrook 8f8e3aa451 ARM TCG conversion 13/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4150 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:48:01 +00:00
pbrook 8984bd2e83 ARM TCG conversion 12/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4149 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:48 +00:00
pbrook 5e3f878ad6 ARM TCG conversion 11/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4148 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:34 +00:00
pbrook 4373f3ceeb ARM TCG conversion 10/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4147 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:19 +00:00
pbrook b010980544 ARM TCG conversion 9/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4146 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:47:03 +00:00
pbrook d9ba48308d ARM TCG conversion 8/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4145 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:50 +00:00
pbrook 6ddbc6e4cf ARM TCG conversion 7/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4144 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:33 +00:00
pbrook 3670669ce2 ARM TCG conversion 6/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4143 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:19 +00:00
pbrook 8f01245ee7 ARM TCG conversion 5/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4142 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:46:03 +00:00
pbrook 1497c961af ARM TCG conversion 4/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4141 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:45:50 +00:00
pbrook 9a119ff6c1 ARM TCG conversion 3/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4140 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:45:35 +00:00
pbrook f51bbbfefe ARM TCG conversion 2/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4139 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:45:13 +00:00
pbrook b26eefb68e ARM TCG conversion 1/16. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@4138 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-03-31 03:44:26 +00:00
bellard 57fec1fee9 use the TCG code generator 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3944 c046a42c-6fe2-441c-8c8c-71466251a162
 2008-02-01 10:50:11 +00:00
ths 01ba98161f Handle cpu_model in copy_cpu(), by Kirill A. Shutemov. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3778 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-12-09 02:22:57 +00:00
pbrook 2ad207d4a0 Thumb semihosting fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3729 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-24 23:22:11 +00:00
pbrook f090c9d4ad Add strict checking mode for softfp code. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3688 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-18 14:33:24 +00:00
bellard 2f6196984b suppressed tgetx and tputx (initial patch by Thayne Harbaugh) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3653 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-16 10:46:05 +00:00
balrog 2f4a40e569 Prevent cpsr_write/_read be put out of line in op.o (fixes a segfault on some platforms). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3633 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-13 01:50:15 +00:00
pbrook e160c51ccd Fix msr_mask. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3584 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 14:36:36 +00:00
bellard 44f8625d23 fixed invalid type 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3582 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 12:35:55 +00:00
pbrook 9ee6e8bb85 ARMv7 support. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3572 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-11 00:04:49 +00:00
bellard aaed909a49 added cpu_model parameter to cpu_init() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3562 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-11-10 15:15:54 +00:00
balrog 405ee3ad57 Invalidate TLBs when domains are changed (Matthew Warton). 
Legalise cp15 pid register writes (Matthew Warton).


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3494 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-31 00:47:13 +00:00
ths 273af66025 Adjust s390 addresses (the MSB is defined as "to be ignored"). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3486 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-29 14:39:49 +00:00
j_mayer 6ebbf39000 Replace is_user variable with mmu_idx in softmmu core, 
allowing support of more than 2 mmu access modes.
Add backward compatibility is_user variable in targets code when needed.
Implement per target cpu_mmu_index function, avoiding duplicated code
  and #ifdef TARGET_xxx in softmmu core functions.
Implement per target mmu modes definitions. As an example, add PowerPC
  hypervisor mode definition and Alpha executive and kernel modes definitions.
Optimize PowerPC case, precomputing mmu_idx when MSR register changes
  and using the same definition in code translation code.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3384 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-14 07:07:08 +00:00
j_mayer c732abe222 Unify '-cpu ?' option. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3380 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-10-12 06:47:46 +00:00
ths 198a74de4c Move get_sp_from_cpustate from cpu.h to target_signal.h. 
Enable sigaltstack processing for more architectures.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3253 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-27 16:44:32 +00:00
ths a04e134ad1 linux-user sigaltstack() syscall, by Thayne Harbaugh. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3252 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-27 13:57:58 +00:00
ths 3b46e62427 find -type f | xargs sed -i 's/[\t ]*$//g' # Yes, again. Note the star in the regex. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3177 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-17 08:09:54 +00:00
ths 5fafdf24ef find -type f | xargs sed -i 's/[\t ]$//g' # on most files 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3173 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-16 21:08:06 +00:00
ths ce62e5ba09 Fix tb->size mishandling, by Daniel Jacobowitz. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3160 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-09-11 10:04:58 +00:00
balrog 2e23213f26 Special-case iWMMXt register transfer insns, which are in ARM LDC2/STC2 class. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3107 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-08-01 02:31:54 +00:00
balrog 330c4d61a6 Fix XScale MMU's extended small pages. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3093 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-07-29 22:21:45 +00:00
balrog c3d2689d88 Basic OMAP310 support. Basic Palm Tungsten|E machine emulation. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3091 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-07-29 17:57:26 +00:00
balrog 82d179781b Various reg offset shift typos. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3085 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-07-24 01:07:44 +00:00
pbrook aa268ea622 Thumb shifter carry flag fixes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3083 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-07-22 18:16:42 +00:00
balrog 610c3c8afd Reset ARM cp15.c1_sys to default values. Fix XScale cp15 accesses. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@3013 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-24 12:09:48 +00:00
pbrook 39524770b2 Fix "blx lr" (Lauro Venancio). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2979 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-11 18:59:35 +00:00
balrog 7a774c875b Use the same offset for all STR and STM instructions that store r15, as specified in ARM ARM (patch from Chris McNett). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2970 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-10 13:53:18 +00:00
ths 9467d44c4d Move target-specific defines to the target directories. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2940 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-03 21:02:38 +00:00
ths bfed01fc79 Clean up of some target specifics in exec.c/cpu-exec.c. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2936 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-06-03 17:44:37 +00:00
balrog 1b1afeb95b Don't touch carry flag in ASR <reg> with zero <reg>, submitted by Aurelien Jarno. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2843 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-21 17:48:01 +00:00
pbrook ce8198612e ARM946 CPU support. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2783 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-08 02:30:40 +00:00
balrog a90b7318ba Implement power state changes (IDLE and SLEEP) for PXA. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2762 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-05-01 01:28:01 +00:00
balrog 9d55199763 Account for machine with RAM which is not mapped at 0x0 in arm_boot.c. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2757 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-30 02:24:42 +00:00
balrog 18c9b56060 Implement iwMMXt instruction set for the PXA270 cpu. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2752 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-30 02:02:17 +00:00
balrog c1713132e0 Core features of ARM XScale processors. Main PXA270 and PXA255 peripherals. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2749 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-30 01:26:42 +00:00
pbrook c73c3aa081 Fix ARM fine pagetables. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2742 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-29 19:06:34 +00:00
j_mayer 9b3c35e0e6 cpu_get_phys_page_debug should return target_phys_addr_t 
instead of target_ulong to be consistent.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2633 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-07 11:21:28 +00:00
ths 687fa640d4 Random bug fixes from code inspection, by Wang Cheng Yeh. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2580 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-04-02 08:18:36 +00:00
ths 8294eba187 SPARC host fixes, by Ben Taylor. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2503 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-19 14:47:40 +00:00
pbrook 5fd46862e5 ARM register index+writeback fix (Lauro Ramos Venancio). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2481 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-17 01:43:01 +00:00
pbrook 6658ffb81e Watchpoint support (previous commit got eaten by Savannah server crash). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2479 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-16 23:58:11 +00:00
pbrook f3d6b95e83 ARM reabbot support (orginal patch by Aurelien Jarno). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2476 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-11 13:03:18 +00:00
pbrook 5adb4839e3 Fix typo in help output. 
List ARM cpus.


git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2475 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-08 03:15:18 +00:00
pbrook 3371d27293 Implement --cpu for ARM. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2474 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-03-08 03:04:12 +00:00
pbrook 18acad9250 ARM doubleword post-modify fix (Daniel Jacobowitz). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2424 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-02-14 20:17:03 +00:00
ths 01d6a890b4 Sparc arm/mips/sparc register patch, by Martin Bochnig. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2377 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-02-02 01:03:34 +00:00
ths 5a7b542bbd siginfo fix for Darwin/Mac OS X, by Pierre d'Herbemont. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2369 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-01-31 12:16:51 +00:00
pbrook 8e71621f78 Add ARM Angel semihosting to system emulation. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2340 c046a42c-6fe2-441c-8c8c-71466251a162
 2007-01-20 17:12:09 +00:00
ths 9042c0e20d Check ELF binaries for machine type and endianness. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2274 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-12-23 14:18:40 +00:00
bellard 569f5d668c compilation fix 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2205 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-10-29 15:10:09 +00:00
pbrook a94a6abff4 Fix ARM VFP debugging dumps. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2201 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-10-25 17:43:33 +00:00
pbrook d37aca6625 Fix comment typo. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2197 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-10-22 11:54:30 +00:00
pbrook 78600320a8 Arm MMU fix (Justin Fletcher). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2154 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-09-09 14:36:26 +00:00
pbrook d07edbfa00 Fix Arm cp15 c13 (Process ID) register writes. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2067 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-07-21 22:39:57 +00:00
bellard 567d4107a6 qsub fix (Wolfgang Schildbach) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2024 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-06-26 19:55:19 +00:00
bellard 26a76461f2 C99 64 bit printf 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@2018 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-06-25 18:15:32 +00:00
pbrook 191f9a93f4 ARM postincrememnt addressing fix. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1970 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-06-14 14:36:07 +00:00
bellard 159f366388 ARM undefined instruction execution (Jason Wessel) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1938 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-05-22 23:06:04 +00:00
pbrook 358bf29e80 Thumb prefetch abort fix. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1805 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-04-09 14:38:57 +00:00
pbrook 53a5960aad Avoid accessing guest memory directly in usermode emulation. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1790 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-03-25 19:31:22 +00:00
pbrook 8637c67fc5 Fix FIQ bank switching. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1786 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-03-14 14:20:32 +00:00
pbrook 19b045dec9 Fix FPA condition codes (Ulrich Hecht). 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1784 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-03-11 21:03:16 +00:00
pbrook 40f137e1ea Add Arm926 core support. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1765 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-20 00:33:36 +00:00
pbrook 2ae23e7504 Fix Arm msr spsr bug. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1761 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-11 16:20:39 +00:00
pbrook ce4defa062 Arm Linux EABI syscall support. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1756 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-09 16:49:55 +00:00
pbrook 3aa22b4b53 Fix Thumb variable shift condition code bug. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1748 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-07 03:34:35 +00:00
pbrook 191abaa2f0 Fix Arm interrupted ldm bug. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1743 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-04 21:50:36 +00:00
pbrook 06c949e62a Implement Arm BKPT instruction. 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1740 c046a42c-6fe2-441c-8c8c-71466251a162
 2006-02-04 19:35:26 +00:00
bellard 68998c5de3 cpu_reset() fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1712 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-12-18 16:55:25 +00:00
bellard 6d7e63262c switching to Arm mode in do_interrupt() (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1711 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-12-18 16:54:08 +00:00
bellard ee0971849e Arm mulxy insn fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1683 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-12-04 18:56:28 +00:00
bellard 9332f9dafa ARM CPU suspend/halt (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1663 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-26 10:46:39 +00:00
bellard b5ff1b3127 ARM system emulation (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1661 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-26 10:38:39 +00:00
bellard 173d6cfe51 cpu_exec_init() change 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1643 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-21 23:32:20 +00:00
bellard a316d3353c added CPU_COMMON and CPUState.tb_jmp_cache[] 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1630 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-20 10:32:34 +00:00
bellard 6e256c935c use direct jump only for jumps in the same page 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1629 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-20 10:32:05 +00:00
bellard 2531fc7bc0 thumb BLX insn fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1607 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-11-06 19:36:29 +00:00
bellard c53be33474 suppressed JUMP_TB (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1594 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-10-30 21:39:19 +00:00
bellard a9049a07bb moved common softmmu code to common header (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1580 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-10-30 18:16:26 +00:00
bellard 1e8a7cfd11 Show thumb state in cpu dump (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1555 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-08-21 10:14:28 +00:00
bellard bc380d1719 ARM VFP dump fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1432 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-05-13 22:50:47 +00:00
bellard ff8263a951 ARM saturating arithmetic fixes (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1431 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-05-13 22:45:23 +00:00
bellard 5899f386ba ARM thumb fixes 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1418 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-27 20:25:20 +00:00
bellard e50e6a2019 better arm conditionnal execution implementation (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1399 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-26 20:36:11 +00:00
bellard 74c161bd17 Fix dumping of arm registers (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1387 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-23 18:46:03 +00:00
bellard 8aaca4c0b4 ARM singlestep support (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1384 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-23 18:27:52 +00:00
bellard 89344d5ad7 arm vfp fcmp and fcmpe instructions fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1382 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-23 18:21:13 +00:00
bellard 1fddef4b1b gdb support for user mode (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1367 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-17 19:16:13 +00:00
bellard 8e96005d86 VFP register ordering (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1355 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-04-07 19:42:46 +00:00
bellard b7a100da9c removed extern inline (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1340 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-03-20 10:34:22 +00:00
bellard 53cd663792 soft float support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1337 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-03-13 18:50:23 +00:00
bellard 2049521883 use the generic soft float code 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1333 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-03-13 16:55:58 +00:00
bellard b7bcbe9524 ARM VFP support (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1309 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-02-22 19:27:29 +00:00
bellard b8a9e8f133 initial user mmu support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1270 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-02-07 23:10:07 +00:00
bellard a8d3431ae9 endianness fixes 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1268 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-02-07 12:43:57 +00:00
bellard 7ff4d2180b CF generator for constant operands 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1267 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-02-07 12:42:35 +00:00
bellard 78573df6b2 SBCS fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1264 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-02-02 20:43:01 +00:00
bellard 99c475abf1 armv5te support (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1258 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-01-31 20:45:13 +00:00
bellard 0fa85d43d4 64 bit target support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1195 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-01-03 23:43:32 +00:00
bellard 526ff7de82 removed warnings 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1193 c046a42c-6fe2-441c-8c8c-71466251a162
 2005-01-03 23:41:14 +00:00
bellard 1e8d4eec48 more complete ARM shift fix 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1168 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-12-08 23:40:14 +00:00
bellard 88920f344d ARM shift fix (Paul Brook) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1167 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-12-08 22:28:39 +00:00
bellard 0d1a29f9fc correct handling of saved host registers 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1122 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-10-12 22:01:28 +00:00
bellard 7fe48483cd monitor fixes 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@1110 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-10-09 18:08:01 +00:00
bellard 7496f5266c cpu_single_env init 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@967 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-06-22 10:56:50 +00:00
bellard beddab753d arm load/store half word fix (Ulrich Hecht) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@785 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-05-05 18:36:10 +00:00
bellard d720b93d0b precise self modifying code support 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@745 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-04-25 17:57:43 +00:00
bellard e19e89a5d4 more log items 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@676 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-03-21 17:08:23 +00:00
bellard 537730b956 zero offset optimisation 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@635 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-02-22 13:40:57 +00:00
bellard 3d57da2a70 suppressed dummy FPU ops 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@610 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-02-16 21:47:14 +00:00
bellard 00406dff19 added arm nwfpe support (initial patch by Ulrich Hecht) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@609 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-02-16 21:43:58 +00:00
bellard 3cf1e035ba added TARGET_LONG_BITS 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@580 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-01-24 15:19:09 +00:00
bellard a6b025d37d added cpu_get_phys_page_debug() 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@579 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-01-24 15:18:16 +00:00
bellard bd49793889 use generic GenOpFunc 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@543 c046a42c-6fe2-441c-8c8c-71466251a162
 2004-01-05 00:06:41 +00:00
bellard 163a7cb620 imull fix (suggested by Robert J. Harley) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@478 c046a42c-6fe2-441c-8c8c-71466251a162
 2003-11-30 19:40:08 +00:00
bellard 2e134c9c55 64-bit multiplication fix (Ulrich Hecht) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@446 c046a42c-6fe2-441c-8c8c-71466251a162
 2003-11-11 13:55:33 +00:00
bellard e748ba4f53 ARM half word load/store fix (Ulrich Hecht) 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@438 c046a42c-6fe2-441c-8c8c-71466251a162
 2003-11-03 22:25:25 +00:00
bellard 2c0262afa7 new directory structure 
git-svn-id: svn://svn.savannah.nongnu.org/qemu/trunk@385 c046a42c-6fe2-441c-8c8c-71466251a162
 2003-09-30 20:34:21 +00:00