calling the platform registration of HDMI driver from core
during initialization.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding kconfig and makefile changes to add support for HDMI in OMAP4.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The panel driver(hdmi_omap4_panel.c) in omap2/dss acts as a controller
to manage the enable and disable requests and synchronize audio and video.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding the hdmi interface driver(hdmi.c) to the dss driver. It configures
the audio and video portion of HDMI based on functionality called by the
panel driver.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Yong Zhi <y-zhi@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding the hdmi interface driver header file (hdmi.h) to the dss driver.
Register and structure declaration done here.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding function to reset/set gamma table bit for TV interface, currently
only support for disabled is added.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding function to select between HDMI or VENC clock source.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Adding display type HDMI in dss_features, overlay and the manager so that
HDMI type of display will be recognized.
Signed-off-by: Mythri P K <mythripk@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
print_irq_status functions can be called with empty irq status when full
irq debugging is enabled. This patch makes print_irq_status functions
return immediately when given an empty irq status to lessen the debug
spam slightly.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
dsi_vc_send_bta_sync() waits for BTA interrupt with a 500ms timeout. If
a DSI error happens, no BTA is received and the timeout triggers. This
could be handled much faster by listening to DSI errors also.
This patch uses the ISR support to notice DSI errors while waiting for
the BTA, thus speeding up the fail-path considerably.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add generic ISR support for DSI interrupts. ISRs can be used instead of
custom hooks in the interrupt handler.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Clean up the IRQ handler a bit by separating collection of IRQ stats and
handling of IRQ errors to separate functions.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The DSI PLL parameters (regm, regn, regm_dispc, regm_dsi, fint) have different
fields and also different Max values on OMAP3 and OMAP4. Use dss features to
calculate the register fields and min/max values based on current OMAP revision.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Create 2 functions dss_feat_get_param_min() and dss_feat_get_param_max() which
return the minimum and maximum value of a parameter. Introduce a enum in
dss_features called dss_range_param which contains parameters whose ranges we
are interested in.
Replace this with dss_feat_get_max_dss_fck() which is specific to the parameter
DSS_FCK.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The structures dss_reg_field and dss_clk_source_name have enum members which
specify the register field and the clock source respectively. These members are
not used to choose the correct result in the corresponding feature functions.
Remove these members and change the features array declaration to incorporate
these enums.
The structure dss_clk_source_name without the enum member is just a pointer to
an string. Remove the structure and use a character pointer directly.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Something seems to be wrong with OMAP4 & VENC, and register access fails
in omap_venchw_probe().
This patch skips venc driver registration on OMAP4, thus circumventing
the problem for now.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch adds support for the standard push buttons available on
Overo expansion boards.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch adds support for the standard LEDs on the Overo COM and expansion boards
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The ads7846 driver now requires a regulator. This patch adds the
necessary regulator to the overo board file. Without it, the
following error occurs (and the touchscreen will not function):
ads7846 spi1.0: unable to get regulator: -19
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
On OMAP3, the pixel clock for the LCD manager was derived through DISPC_FCLK as:
Lcd Pixel clock = DISPC_FCLK / lcd / pcd
Where lcd and pcd are divisors in the DISPC_DIVISOR register.
On OMAP4, the pixel clocks for LCD1 and LCD2 managers are derived from 2 new
clocks named LCD1_CLK and LCD2_CLK. The pixel clocks are calculated as:
Lcd_o Pixel clock = LCDo_CLK / lcdo /pcdo, o = 1, 2
Where lcdo and pcdo registers are divisors in DISPC_DIVISORo registers.
LCD1_CLK and LCD2_CLK can have DSS_FCLK, and the M4 divider clocks of DSI1 PLL
and DSI2 PLL as clock sources respectively. Introduce functions to select and
get the clock source for these new clocks. Modify DISPC functions get the
correct lck and pck rates based on the clock source of these clocks. Since
OMAP2/3 don't have these clocks, force OMAP2/3 to always have the LCD_CLK source
as DSS_CLK_SRC_FCK by introducing a dss feature.
Introduce clock source names for OMAP4 and some register field changes in
DSS_CTRL on OMAP4.
Currently, LCD2_CLK can only have DSS_FCLK as its clock source as DSI2 PLL
functionality hasn't been introduced yet. BUG for now if DSI2 PLL is selected as
clock.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Clean up some of the DSS functions which select/get clock sources, use switch
to select the clock source members since more clock sources will be introduced
later on.
Remove the use of macro CONFIG_OMAP2_DSS_DSI in dispc_fclk_rate, use a dummy
inline for function for dsi_get_pll_hsdiv_dispc_rate() instead for code clarity.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch adds DSS2 support for DVI, S-video, the 480x272 Samsung
LTE430WQ-F0C panel, and the 320x240 LG.Philips LB035Q02 panel.
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
This patch adds support for the Gumstix Palo35 expansion board
which utilizes the 320 x 240 pixel LG.Philips LB035Q02 LCD Panel
Signed-off-by: Steve Sakoman <steve@sakoman.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Fix handling of error in omap_dispc_register_isr() in case there are no
free isr slots available.
Reported-by: Ben Tucker <btucker@mpcdata.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Using dss_features to select independent core clock divider and setting
it. Added the register used, to DISPC context save and restore group
-----------------------------------------------------------------------
In OMAP4, the minimum DISPC_CORE_CLK required can be expressed as:
DISPC_CORE_CLK >= max(PCLK1*HSCALE1, PCLK2*HSCALE2, ...)
Where PCLKi is the pixel clock generated by MANAGERi and HSCALEi is the
maximum horizontal downscaling done through MANAGERi
Based on the usecase, core clk can be increased or decreased at runtime
to save power. Such mechanism are not yet implemented. Hence, we set the
core clock divisor to 1, to support maximum range of resolutions
------------------------------------------------------------------------
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The OMAP4 DISPC_DIVISOR1 is backward compatible to OMAP3xxx DISPC_DIVISOR.
However DISPC_DIVISOR is also provided in OMAP4, to control DISPC_CORE_CLK
independent of Primary and Secondary display clocks.
Renamed DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch), to facilitate introduction
of DISPC_DIVISOR register, which is specific for OMAP4. OMAP4 has 3 registers
DISPC_DIVISOR, DISPC_DIVISOR1 and DISPC_DIVISOR2.
Also updated, all the usages of DISPC_DIVISOR(ch) to DISPC_DIVISORo(ch).
Use DISPC_DIVISORo(ch) when DISPC_DIVISOR1 or DISPC_DIVISOR2 has to be
configured
OMAP4 TRM uses DISPC_DIVISORo generically to refer to DISPC_DIVISOR1 and
DISPC_DIVISOR2
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
In OMAP3xxx DISPC_DIVISOR register has a logical clock divisor (lcd_div)
field. The lcd_div is common, for deciding the DISPC core functional clock
frequency, and the final pixel clock frequency for LCD display.
In OMAP4, there are 2 LCD channels, hence two divisor registers, DISPC_DIVISOR1
and DISPC_DIVISOR2. Also, there is a third register DISPC_DIVISOR.
The DISPC_DIVISOR in OMAP4 is used to configure lcd_div exclusively for core
functional clock configuration. For pixel clock configuration of primary and
secondary LCDs, lcd_div of DISPC_DIVISOR1 and DISPC_DIVISOR2 are used
respectively
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Raghuveer Murthy <raghuveer.murthy@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
On omap4 the registers may not be accessible right after enabling the
clocks. At some point this will be handled by pm_runtime, but, for the
time begin, adding a small delay after clk_enable() should make things
work.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
When using OMAP2_DSS_USE_DSI_PLL, which selects DSI PLL as source clock
for DISPC, the DSI needs the vdds_dsi regulator. Latest regulator
changes broke this, causing the the code to not acquire the regulator
when using OMAP2_DSS_USE_DSI_PLL.
This patch acquires the vdds_dsi regulator in dsi_pll_init(), fixing the
issue. This is is just a quick hack to get the OMAP2_DSS_USE_DSI_PLL
option working. There shouldn't be any other downside in this solution
than some extra lines of code.
OMAP2_DSS_USE_DSI_PLL is itself a big hack, and should be removed, and
the feature itself should be implemented in a more sane way. However,
the solution is not trivial, and people are using DSI PLL to get more
exact pixel clocks, so this hack is an acceptable temporary solution for
the time being.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Taal driver used to take a hard coded Macro for Virtual Channel and the VC_ID.
The Taal panel driver now requests for a Virtual channel through the
omap_dsi_request_vc() call in taal_probe().
The channel number returned by the request_vc() call is used for sending command
and data to the Panel. The DSI driver automatically configures the Virtual
Channel's source to either Video Port or L4 Slave port based on what the panel
driver is using it for.
The driver uses omap_dsi_release_vc() to free the VC specified by the panel.
taal_remove() or when a request_vc() call fails.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Introduce functions which request and release VC's. This will be used in panel
drivers in their probes.
omap_dsi_request_vc() takes in the pointer to the omap_dss_device, the VC_ID
parameter which goes into the header of the DSI packets, and returns a Virtual
channel number (or virtual channel register set) which it can use.
omap_dsi_set_vc_id() takes the omap_dss_device pointer, the Virtual Channel
number and the VC_ID that needs to be set for the specifed Virtual Channel.
omap_dsi_release_vc() takes the omap_dss_device pointer and the Virtual Channel
number that needs to be made free.
Initialisation of VC parameters is done in dsi_init().
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
cpu_is_omapxxx() was used previously to select the supported interfaces.
Now that the interfaces are platform devices, we no longer need to do
the check when registering the driver. Thus we can just remove the
checks.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
DPI and SDI are different from the other interfaces as they are not
hwmods and there is not platform driver for them. They could be said to
be a part of DSS or DISPC modules, although it's not a clear definition.
This patch moves DPI and SDI initialization into DSS platform driver,
making the code more consistent: omap_dss_probe() only initializes
platform drivers now.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
FB_OMAP_BOOTLOADER_INIT does not work, and it was only partially
implemented for SDI.
This patch removes support for FB_OMAP_BOOTLOADER_INIT to clean up the
code and to remove any assumptions that FB_OMAP_BOOTLOADER_INIT would
work.
Proper implementation is much more complex, requiring early boot time
register and clock handling to keep the DSS running.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
DSI PLL output clock names have been made more generic. The clock name
describes what the source of the clock and what clock is used for. Some of
DSI PLL parameters like dividers and DSI PLL source have also been made more
generic.
dsi1_pll_fclk and dsi2_pll_fclk have been changed as dsi_pll_hsdiv_dispc_clk
and dsi_pll_hsdiv_dsi_clk respectively. Also, the hsdividers are now named
regm_dispc and regm_dsi instead of regm3 and regm4.
Functions and macros named on the basis of these clock names have also been
made generic.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Clock source names vary across OMAP2/3 and OMAP4, the clock source enum
names have been made generic in the driver, but for purposes of debugging
and dumping clock sources, it is better to preserve the actual TRM name of
the clock.
Introduce a dss feature function 'dss_feat_get_clk_source_name()' which
returns a string with the TRM clock name for the current OMAP in use. The OMAP
specific name is printed along the generic name within brackets.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The enum members of 'dss_clk_source' have clock source names specific to
OMAP2/3. Change the names to more generic terms such that they now describe
where the clocks come from and what they are used for.
Also, change the enum member names to have "DSS_CLK_SRC" instead of "DSS_SRC"
for more clarity.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
The maximum supported frequency for DSS has increased from 173 to 186 Mhz on
OMAP4.
Introduce a dss feature function to get the max_fck to replace DISPC_MAX_FCK
macro.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Add dss_features and register fields to incorporate changes in DISPC pipelines
between OMAP3 and OMAP4.
Register fields added: FEAT_REG_HORIZONTALACCU, FEAT_REG_VERTICALACCU
DSS Features added: FEAT_LINEBUFFERSPLIT, FEAT_ROWREPEATENABLE, FEAT_RESIZECONF
_dispc_set_scaling() and _dispc_set_rotation_attrs() have been cleaned up.
Signed-off-by: Archit Taneja <archit@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
There is a linker error from lcd_2430sdp.c if CONFIG_TWL4030_CORE is not
set. This can be triggered on OMAP2 builds when OMAP3 or OMAP4 are not set.
drivers/built-in.o: In function `sdp2430_panel_disable':
drivers/video/omap/lcd_2430sdp.c:123: undefined reference to `twl_i2c_write_u8'
drivers/video/omap/lcd_2430sdp.c:124: undefined reference to `twl_i2c_write_u8'
drivers/built-in.o: In function `sdp2430_panel_enable':
drivers/video/omap/lcd_2430sdp.c:110: undefined reference to `twl_i2c_write_u8'
drivers/video/omap/lcd_2430sdp.c:112: undefined reference to `twl_i2c_write_u8'
Fix this by selecting the TWL4030_CORE for MACH_OMAP_2430SDP when building
with CONFIG_FB_OMAP as there is no own Kconfig entry for lcd_2430 and it is
compiled always when both MACH_OMAP_2430SDP and FB_OMAP are set.
Signed-off-by: Jarkko Nikula <jhnikula@gmail.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
hwmod databases provide information about which optional clocks are available
for a given platform. This is available via a function pointer opt_clock_enable
in pdata.
Use this information during get/enable/disable/put of clocks.
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Provide a function in pdata to allow dss submodules to check if a given
clock is available on a platform as an optional clock.
Signed-off-by: Senthilvadivu Guruswamy <svadivu@ti.com>
(based on implementation from Senthil)
Signed-off-by: Sumit Semwal <sumit.semwal@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
dsi_reset_tx_fifo() was not used. Furthermore, OMAP errata states that
TX FIFO flush is not functional, so the function wouldn't even have
worked.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
CONFIG_FB_OMAP_LCD_VGA option is present in drivers/video/omap
There is no explaination about what this flag does.
Lets add information about it.
FB_OMAP_LCD_VGA flag sets resolution of display to VGA (640 X 480).
The default resolution of 3430 LDP is 320 X 240.
Signed-off-by: Mayuresh Janorkar <mayur@ti.com>
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Only OMAP 3430 hardware has SDI support. The availability of SDI HW can
be found out by checking if the LCD channel supports SDI displays.
This patch checks for SDI HW support before accessing SDI registers,
which fixes a crash on OMAP4 when SDI SW support is compiled in.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Mythri P K