Commit Graph

3299 Commits

Author SHA1 Message Date
Suzuki K Poulose 0dbd3b18c6 arm64: Introduce pmd_thp_or_huge
Add a helper to determine if a given pmd represents a huge page
either by hugetlb or thp, as we have for arm. This will be used
by KVM MMU code.

Suggested-by: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Steve Capper <steve.capper@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
2016-04-21 14:56:52 +02:00
Suzuki K Poulose 120f0779c3 kvm arm: Move fake PGD handling to arch specific files
Rearrange the code for fake pgd handling, which is applicable
only for arm64. This will later be removed once we introduce
the stage2 page table walker macros.

Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
2016-04-21 14:56:44 +02:00
Suzuki K Poulose acd0501040 arm64: Cleanup VTCR_EL2 and VTTBR field values
We share most of the bits for VTCR_EL2 for different page sizes,
except for the TG0 value and the entry level value. This patch
makes the definitions a bit more cleaner to reflect this fact.

Also cleans up the VTTBR_X calculation. No functional changes.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
2016-04-21 14:56:41 +02:00
Suzuki K Poulose a563f75981 arm64: Reuse TCR field definitions for EL1 and EL2
TCR_EL1, TCR_EL2 and VTCR_EL2, all share some field positions
(TG0, ORGN0, IRGN0 and SH0) and their corresponding value definitions.

This patch makes the TCR_EL1 definitions reusable and uses them for TCR_EL2
and VTCR_EL2 fields.

This also fixes a bug where we assume TG0 in {V}TCR_EL2 is 1bit field.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
2016-04-21 14:56:28 +02:00
Sascha Hauer 748c7d4de4 ARM64: dts: mt8173: Add thermal/auxadc device nodes
This adds the thermal controller and auxadc nodes to the Mediatek MT8173
dtsi file.

Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-04-20 13:30:13 +02:00
Suzuki K Poulose 643d703d2d arm64: compat: Check for AArch32 state
Make sure we have AArch32 state available for running COMPAT
binaries and also for switching the personality to PER_LINUX32.

Signed-off-by: Yury Norov <ynorov@caviumnetworks.com>
[ Added cap bit, checks for HWCAP, personality ]
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:42 +01:00
Suzuki K Poulose 042446a31e arm64: cpufeature: Track 32bit EL0 support
Add cpu_hwcap bit for keeping track of the support for 32bit EL0.

Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:42 +01:00
Suzuki K Poulose a6dc3cd718 arm64: cpufeature: Check availability of AArch32
On ARMv8 support for AArch32 state is optional. Hence it is
not safe to check the AArch32 ID registers for sanity, which
could lead to false warnings. This patch makes sure that the
AArch32 state is implemented before we keep track of the 32bit
ID registers.

As per ARM ARM (D.1.21.2 - Support for Exception Levels and
Execution States, DDI0487A.h), checking the support for AArch32
at EL0 is good enough to check the support for AArch32 (i.e,
AArch32 at EL1 => AArch32 at EL0, but not vice versa).

Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:42 +01:00
Suzuki K Poulose c80aba803a arm64: Add helpers for detecting AArch32 support at EL0
Adds a helper to extract the support for AArch32 at EL0

Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:42 +01:00
Suzuki K Poulose 752835019c arm64: HWCAP: Split COMPAT HWCAP table entries
In order to handle systems which do not support 32bit at EL0,
split the COMPAT HWCAP entries into a separate table which can
be processed, only if the support is available.

Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:42 +01:00
Suzuki K Poulose f3efb67590 arm64: hwcaps: Cleanup naming
We use hwcaps for referring to ELF hwcaps capability information.
However this can be confusing with 'cpu_hwcaps' which stands for the
CPU capability bit field. This patch cleans up the names to make it
a bit more readable.

Tested-by: Yury Norov <ynorov@caviumnetworks.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:22:41 +01:00
Mark Rutland 2ff4936c1d arm64: asm: remove unused push/pop macros
We haven't used the push/pop macros for a while now, as it's typically
better to use immediate offsets for batches of accesses to the stack, as
we now do in the entry assembly for the kernel and hyp code.

Remove the unused macros.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:19:01 +01:00
Yang Shi 8ee708792e arm64: Kconfig: remove redundant HAVE_ARCH_TRANSPARENT_HUGEPAGE definition
HAVE_ARCH_TRANSPARENT_HUGEPAGE has been defined in arch/Kconfig already,
the ARM64 version is identical with it and the default value is Y. So remove
the redundant definition and just select it under CONFIG_ARM64.

Signed-off-by: Yang Shi <yang.shi@linaro.org>
[will: sort into alphabetical order whilst I'm resolving conflicts]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-20 12:16:50 +01:00
Masahiro Yamada 2fee7d5b08 arm64: spin-table: add missing of_node_put()
Since of_get_cpu_node() increments refcount, the node should be put.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-04-20 10:35:15 +01:00
Kefeng Wang 9974723e31 arm64: mm: Show bss segment in kernel memory layout
Show the bss segment information as with text and data in Virtual
memory kernel layout.

Acked-by: James Morse <james.morse@arm.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-19 17:03:31 +01:00
Kefeng Wang d32351c824 arm64: mm: make pr_cont() per line in Virtual kernel memory layout
Each line with single pr_cont() in Virtual kernel memory layout,
or the dump of the kernel memory layout in dmesg is not aligned
when PRINTK_TIME enabled, due to the missing time stamps.

Tested-by: James Morse <james.morse@arm.com>
Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-19 17:01:34 +01:00
Jan Glauber 82611c14c4 arm64: Reduce verbosity on SMP CPU stop
When CPUs are stopped during an abnormal operation like panic
for each CPU a line is printed and the stack trace is dumped.

This information is only interesting for the aborting CPU
and on systems with many CPUs it only makes it harder to
debug if after the aborting CPU the log is flooded with data
about all other CPUs too.

Therefore remove the stack dump and printk of other CPUs
and only print a single line that the other CPUs are going to be
stopped and, in case any CPUs remain online list them.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-19 09:53:04 +01:00
Huang Shijie 3a72db703c arm64: mm: remove the redundant code
We already re-enable interrupts where necessary in the entry code, so
there is no need to do it again in do_page fault. This patch removes
the redundant code.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Huang Shijie <shijie.huang@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-19 09:52:51 +01:00
Ard Biesheuvel adb4907007 arm64: fix invalidation of wrong __early_cpu_boot_status cacheline
In head.S, the str_l macro, which takes a source register, a symbol name
and a temp register, is used to store a status value to the variable
__early_cpu_boot_status. Subsequently, the value of the temp register is
reused to invalidate any cachelines covering this variable.

However, since str_l resolves to

      adrp    \tmp, \sym
      str     \src, [\tmp, :lo12:\sym]

the temp register never actually holds the address of the variable but
only of the 4 KB window that covers it, and reusing it leads to the
wrong cacheline being invalidated. So instead, take the address
explicitly before doing the store, and reuse that value to perform
the cache invalidation.

Fixes: bb9052744f ("arm64: Handle early CPU boot failures")
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Suzuki K Poulose <Suzuki.Poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-04-18 16:23:24 +01:00
Yuan Yao e26e054ba8 arm64: dts: ls1043a: add the DTS node for QSPI support
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-18 10:15:50 +08:00
Catalin Marinas 66dbd6e61a arm64: Implement ptep_set_access_flags() for hardware AF/DBM
When hardware updates of the access and dirty states are enabled, the
default ptep_set_access_flags() implementation based on calling
set_pte_at() directly is potentially racy. This triggers the "racy dirty
state clearing" warning in set_pte_at() because an existing writable PTE
is overridden with a clean entry.

There are two main scenarios for this situation:

1. The CPU getting an access fault does not support hardware updates of
   the access/dirty flags. However, a different agent in the system
   (e.g. SMMU) can do this, therefore overriding a writable entry with a
   clean one could potentially lose the automatically updated dirty
   status

2. A more complex situation is possible when all CPUs support hardware
   AF/DBM:

   a) Initial state: shareable + writable vma and pte_none(pte)
   b) Read fault taken by two threads of the same process on different
      CPUs
   c) CPU0 takes the mmap_sem and proceeds to handling the fault. It
      eventually reaches do_set_pte() which sets a writable + clean pte.
      CPU0 releases the mmap_sem
   d) CPU1 acquires the mmap_sem and proceeds to handle_pte_fault(). The
      pte entry it reads is present, writable and clean and it continues
      to pte_mkyoung()
   e) CPU1 calls ptep_set_access_flags()

   If between (d) and (e) the hardware (another CPU) updates the dirty
   state (clears PTE_RDONLY), CPU1 will override the PTR_RDONLY bit
   marking the entry clean again.

This patch implements an arm64-specific ptep_set_access_flags() function
to perform an atomic update of the PTE flags.

Fixes: 2f4b829c62 ("arm64: Add support for hardware updates of the access and dirty pte bits")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Ming Lei <tom.leiming@gmail.com>
Tested-by: Julien Grall <julien.grall@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: <stable@vger.kernel.org> # 4.3+
[will: reworded comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:09 +01:00
Ganapatrao Kulkarni 561662301e arm64, mm, numa: Add NUMA balancing support for arm64.
Enable NUMA balancing for arm64 platforms.
Add pte, pmd protnone helpers for use by automatic NUMA balancing.

Reviewed-by: Steve Capper <steve.capper@arm.com>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:09 +01:00
Ganapatrao Kulkarni 1a2db30034 arm64, numa: Add NUMA support for arm64 platforms.
Attempt to get the memory and CPU NUMA node via of_numa.  If that
fails, default the dummy NUMA node and map all memory and CPUs to node
0.

Tested-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Robert Richter <rrichter@cavium.com>
Signed-off-by: Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:09 +01:00
David Daney 3194ac6e66 arm64: Move unflatten_device_tree() call earlier.
In order to extract NUMA information from the device tree, we need to
have the tree in its unflattened form.

Move the call to bootmem_init() in the tail of paging_init() into
setup_arch, and adjust header files so that its declaration is
visible.

Move the unflatten_device_tree() call between the calls to
paging_init() and bootmem_init().  Follow on patches add NUMA handling
to bootmem_init().

Signed-off-by: David Daney <david.daney@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:08 +01:00
Suzuki K Poulose ac1ad20f9e arm64: vhe: Verify CPU Exception Levels
With a VHE capable CPU, kernel can run at EL2 and is a decided at early
boot. If some of the CPUs didn't start it EL2 or doesn't have VHE, we
could have CPUs running at different exception levels, all in the same
kernel! This patch adds an early check for the secondary CPUs to detect
such situations.

For each non-boot CPU add a sanity check to make sure we don't have
different run levels w.r.t the boot CPU. We save the information on
whether the boot CPU is running in hyp mode or not and ensure the
remaining CPUs match it.

Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[will: made boot_cpu_hyp_mode static]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:07 +01:00
Suzuki K Poulose 17eebd1a43 arm64: Add cpu_panic_kernel helper
During the activation of a secondary CPU, we could report serious
configuration issues and hence request to crash the kernel. We do
this for CPU ASID bit check now. We will need it also for handling
mismatched exception levels for the CPUs with VHE. Hence, add a
helper to do the same for reusability.

Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-15 18:06:06 +01:00
Leo Yan 6485160396 arm64: dts: Add L2 cache topology to Hi6220
This patch adds the L2 cache topology on Hi6220. Hi6220 has two
clusters, every cluster has 512KiB L2 cache (32KiB x 16 ways).

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 17:04:15 +01:00
Leo Yan cd0b69ec0e arm64: dts: register Hi6220's thermal zone for power allocator
With profiling Hi6220's power modeling so get dynamic coefficient and
sustainable power. So pass these parameters from DT.

Now enable power allocator with only one actor for CPU part, so directly
use cluster0's thermal sensor for monitoring temperature.

Reviewed-by: Javi Merino <javi.merino@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 17:02:18 +01:00
Leo Yan 2158ab084b arm64: dts: register Hi6220's thermal sensor
Bind thermal sensor driver for Hi6220.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:58:55 +01:00
Guodong Xu 841478d4ae arm64: dts: add wifi nodes support for hi6220-hikey
Add wifi nodes support for hi6220-hikey

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:10 +01:00
Xinwei Kong d6b259d4fa arm64: dts: add dwmmc nodes for hi6220
Add all three dwmmc nodes description for hi6220

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:07 +01:00
Chen Feng a817137a6c arm64: dts: hikey: Add hi655x pmic dts node
Add the mfd hi655x dts node and regulator support on hi6220 platform.

Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Fei Wang <w.f@huawei.com>
Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Reviewed-by: Rob Herring <robh@kernel.org>
Acked-by: Lee Jones <lee.jones@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:43:04 +01:00
Guodong Xu ad05f38ba9 arm64: dts: add LED nodes for hi6220-hikey
Add LED nodes for hi6220-hikey. There are total 6 LEDs on HiKey.
Four general purposed, one for WiFi activity, and one for Bluetooth
activity.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:10 +01:00
Guodong Xu c2aad93200 arm64: dts: hi6220: add pinctrl for uarts and enable them
Add pinctrl for uart2 uart3 and uart4. Enable uart1 uart2 and uart3.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:09 +01:00
Leo Yan 9986054072 arm64: dts: add Hi6220's stub clock node
Enable SRAM node and stub clock node for Hi6220, which uses mailbox
channel 1 for CPU's frequency change.

Furthermore, add the CPU clock phandle in CPU's node and using
operating-points-v2 to register operating points. So can be used by
cpufreq-dt driver.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:22:03 +01:00
Leo Yan 8607357016 arm64: dts: add mailbox node for Hi6220
This patch add device mailbox node for Hi6220 in DT.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Acked-by: Jassi Brar <jassisinghbrar@gmail.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:58 +01:00
Zhangfei Gao b4b31a7cd7 arm64: dts: Add hi6220 usb node
Add USB nodes for Hi6220

Signed-off-by: Zhangfei Gao <zhangfei.gao@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:53 +01:00
Guodong Xu 0c2317512d arm64: dts: hikey: enable i2c0 and i2c1 for working with mezzanine boards
In HiKey board dts file, enable i2c0 and i2c1 for working with 96boards' LS
mezzanine.

Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:52 +01:00
Xinwei Kong 5ff3a4ddd1 arm64: dts: add all hi6220 i2c nodes
This patch adds all I2C nodes for the Hi6220 SoC. This hi6220 Soc
use this I2C IP of Synopsys Designware for HiKey board.

Signed-off-by: Xinwei Kong <kong.kongxinwei@hisilicon.com>
Signed-off-by: Chen Feng <puck.chen@hisilicon.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:52 +01:00
Zhong Kaihua 60dac1b19b arm64: dts: add Hi6220 spi configuration nodes
Add Hi6220 spi configuration nodes. Disable by default in hi6220.dtsi
and enable it in board dts for usage of 96boards LS mezzanine board.

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.com>
Reviewed-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:45 +01:00
Zhong Kaihua 379e9bf52d arm64: dts: add Hi6220 pinctrl configuration nodes
Add Hi6220 pinctrl configuration nodes

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Acked-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:45 +01:00
Zhong Kaihua f2bfacf9dd arm64: dts: Add Hi6220 gpio configuration nodes
Add Hi6220 gpio configuration nodes

Signed-off-by: Zhong Kaihua <zhongkaihua@huawei.com>
Signed-off-by: Kong Xinwei <kong.kongxinwei@hisilicon.com>
Signed-off-by: Guodong Xu <guodong.xu@linaro.org>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:21:24 +01:00
Leo Yan 58fa29bfbe arm64: dts: enable idle states for Hi6220
Add cpu and cluster level's low power state for Hi6220.

Acked-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Leo Yan 9e92703165 arm64: dts: add sp804 timer node for Hi6220
Add sp804 timer for hi6220, so it can be used as broadcast timer.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Leo Yan 6da3aba6f0 arm64: dts: Reserve memory regions for hi6220
On Hi6220, below memory regions in DDR have specific purpose:

  0x05e0,0000 - 0x05ef,ffff: For MCU firmware using at runtime;
  0x06df,f000 - 0x06df,ffff: For mailbox message data;
  0x0740,f000 - 0x0740,ffff: For MCU firmware's section;
  0x3e00,0000 - 0x3fff,ffff: For OP-TEE.

This patch reserves these memory regions in DT.

Signed-off-by: Leo Yan <leo.yan@linaro.org>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-04-15 16:11:32 +01:00
Rhyland Klein 8d53957c66 arm64: tegra: Enable cros-ec and charger on Smaug
Add nodes for the ChromeOS Embedded Controller and for the gas gauge
connected to the I2C bus that it controls.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-15 15:36:38 +02:00
Brian Starkey f5f7e45537 arm64: dts: juno: Add external expansion bus to DT
The Juno development platform has an external expansion bus which can
be used for additional hardware (e.g. LogicTile Express daughterboards).

Add this bus to the Juno base device-tree.

Acked-by: Liviu Dudau <Liviu.Dudau@arm.com>
Signed-off-by: Brian Starkey <brian.starkey@arm.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-04-15 09:50:06 +01:00
Rameshwar Prasad Sahu 01d1b6e543 arm64: dts: apm: Fix compatible string for X-Gene 2 SATA controller DTS node
Fix X-Gene SATA controller compatible string for Merlin board.

Signed-off-by: Rameshwar Prasad Sahu <rsahu@apm.com>
Acked-by: Suman Tripathi <stripathi@apm.com>
2016-04-14 17:34:22 -07:00
James Morse 6afedcd23c arm64: mm: Add trace_irqflags annotations to do_debug_exception()
With CONFIG_PROVE_LOCKING, CONFIG_DEBUG_LOCKDEP and CONFIG_TRACE_IRQFLAGS
enabled, lockdep will compare current->hardirqs_enabled with the flags from
local_irq_save().

When a debug exception occurs, interrupts are disabled in entry.S, but
lockdep isn't told, resulting in:
DEBUG_LOCKS_WARN_ON(current->hardirqs_enabled)
------------[ cut here ]------------
WARNING: at ../kernel/locking/lockdep.c:3523
Modules linked in:
CPU: 3 PID: 1752 Comm: perf Not tainted 4.5.0-rc4+ #2204
Hardware name: ARM Juno development board (r1) (DT)
task: ffffffc974868000 ti: ffffffc975f40000 task.ti: ffffffc975f40000
PC is at check_flags.part.35+0x17c/0x184
LR is at check_flags.part.35+0x17c/0x184
pc : [<ffffff80080fc93c>] lr : [<ffffff80080fc93c>] pstate: 600003c5
[...]
---[ end trace 74631f9305ef5020 ]---
Call trace:
[<ffffff80080fc93c>] check_flags.part.35+0x17c/0x184
[<ffffff80080ffe30>] lock_acquire+0xa8/0xc4
[<ffffff8008093038>] breakpoint_handler+0x118/0x288
[<ffffff8008082434>] do_debug_exception+0x3c/0xa8
[<ffffff80080854b4>] el1_dbg+0x18/0x6c
[<ffffff80081e82f4>] do_filp_open+0x64/0xdc
[<ffffff80081d6e60>] do_sys_open+0x140/0x204
[<ffffff80081d6f58>] SyS_openat+0x10/0x18
[<ffffff8008085d30>] el0_svc_naked+0x24/0x28
possible reason: unannotated irqs-off.
irq event stamp: 65857
hardirqs last  enabled at (65857): [<ffffff80081fb1c0>] lookup_mnt+0xf4/0x1b4
hardirqs last disabled at (65856): [<ffffff80081fb188>] lookup_mnt+0xbc/0x1b4
softirqs last  enabled at (65790): [<ffffff80080bdca4>] __do_softirq+0x1f8/0x290
softirqs last disabled at (65757): [<ffffff80080be038>] irq_exit+0x9c/0xd0

This patch adds the annotations to do_debug_exception(), while trying not
to call trace_hardirqs_off() if el1_dbg() interrupted a task that already
had irqs disabled.

Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:40:33 +01:00
Anna-Maria Gleixner 4bc4927440 arm64: hw-breakpoint: Remove superfluous SMP function call
Since commit 1cf4f629d9 ("cpu/hotplug: Move online calls to
hotplugged cpu") it is ensured that callbacks of CPU_ONLINE and
CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this SMP
function calls are no longer required.

Replace smp_call_function_single() with a direct call of
hw_breakpoint_reset(). To keep the calling convention, interrupts are
explicitly disabled around the call.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:13:03 +01:00
Anna-Maria Gleixner 499c81507f arm64/debug: Remove superfluous SMP function call
Since commit 1cf4f629d9 ("cpu/hotplug: Move online calls to
hotplugged cpu") it is ensured that callbacks of CPU_ONLINE and
CPU_DOWN_PREPARE are processed on the hotplugged CPU. Due to this SMP
function calls are no longer required.

Replace smp_call_function_single() with a direct call to
clear_os_lock(). The function writes the OSLAR register to clear OS
locking. This does not require to be called with interrupts disabled,
therefore the smp_call_function_single() calling convention is not
preserved.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Anna-Maria Gleixner <anna-maria@linutronix.de>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:13:03 +01:00
Ard Biesheuvel 97740051dd arm64: simplify kernel segment mapping granularity
The mapping of the kernel consist of four segments, each of which is mapped
with different permission attributes and/or lifetimes. To optimize the TLB
and translation table footprint, we define various opaque constants in the
linker script that resolve to different aligment values depending on the
page size and whether CONFIG_DEBUG_ALIGN_RODATA is set.

Considering that
- a 4 KB granule kernel benefits from a 64 KB segment alignment (due to
  the fact that it allows the use of the contiguous bit),
- the minimum alignment of the .data segment is THREAD_SIZE already, not
  PAGE_SIZE (i.e., we already have padding between _data and the start of
  the .data payload in many cases),
- 2 MB is a suitable alignment value on all granule sizes, either for
  mapping directly (level 2 on 4 KB), or via the contiguous bit (level 3 on
  16 KB and 64 KB),
- anything beyond 2 MB exceeds the minimum alignment mandated by the boot
  protocol, and can only be mapped efficiently if the physical alignment
  happens to be the same,

we can simplify this by standardizing on 64 KB (or 2 MB) explicitly, i.e.,
regardless of granule size, all segments are aligned either to 64 KB, or to
2 MB if CONFIG_DEBUG_ALIGN_RODATA=y. This also means we can drop the Kconfig
dependency of CONFIG_DEBUG_ALIGN_RODATA on CONFIG_ARM64_4K_PAGES.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:11:44 +01:00
Ard Biesheuvel 7eb90f2ff7 arm64: cover the .head.text section in the .text segment mapping
Keeping .head.text out of the .text mapping buys us very little: its actual
payload is only 4 KB, most of which is padding, but the page alignment may
add up to 2 MB (in case of CONFIG_DEBUG_ALIGN_RODATA=y) of additional
padding to the uncompressed kernel Image.

Also, on 4 KB granule kernels, the 4 KB misalignment of .text forces us to
map the adjacent 56 KB of code without the PTE_CONT attribute, and since
this region contains things like the vector table and the GIC interrupt
handling entry point, this region is likely to benefit from the reduced TLB
pressure that results from PTE_CONT mappings.

So remove the alignment between the .head.text and .text sections, and use
the [_text, _etext) rather than the [_stext, _etext) interval for mapping
the .text segment.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:11:43 +01:00
Ard Biesheuvel 546c8c44f0 arm64: move early boot code to the .init segment
Apart from the arm64/linux and EFI header data structures, there is nothing
in the .head.text section that must reside at the beginning of the Image.
So let's move it to the .init section where it belongs.

Note that this involves some minor tweaking of the EFI header, primarily
because the address of 'stext' no longer coincides with the start of the
.text section. It also requires a couple of relocated symbol references
to be slightly rewritten or their definition moved to the linker script.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:11:30 +01:00
Ard Biesheuvel 2c09ec06bc arm64: use 'segment' rather than 'chunk' to describe mapped kernel regions
Replace the poorly defined term chunk with segment, which is a term that is
already used by the ELF spec to describe contiguous mappings with the same
permission attributes of statically allocated ranges of an executable.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 18:11:11 +01:00
Ard Biesheuvel 9f2875912d arm64: mm: restrict virt_to_page() to the linear mapping
Now that the vmemmap region has been redefined to cover the linear region
rather than the entire physical address space, we no longer need to
perform a virtual-to-physical translation in the implementaion of
virt_to_page(). This restricts virt_to_page() translations to the linear
region, so redefine virt_addr_valid() as well.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel 3e1907d5bf arm64: mm: move vmemmap region right below the linear region
This moves the vmemmap region right below PAGE_OFFSET, aka the start
of the linear region, and redefines its size to be a power of two.
Due to the placement of PAGE_OFFSET in the middle of the address space,
whose size is a power of two as well, this guarantees that virt to
page conversions and vice versa can be implemented efficiently, by
masking and shifting rather than ordinary arithmetic.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel e44308e62e arm64: insn: avoid virt_to_page() translations on core kernel symbols
Before restricting virt_to_page() to the linear mapping, ensure that
the text patching code does not use it to resolve references into the
core kernel text, which is mapped in the vmalloc area.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel 22b6f3b054 arm64: mm: avoid virt_to_page() translation for the zero page
The zero page is statically allocated, so grab its struct page pointer
without using virt_to_page(), which will be restricted to the linear
mapping later.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel d386825c95 arm64: mm: free __init memory via the linear mapping
The implementation of free_initmem_default() expects __init_begin
and __init_end to be covered by the linear mapping, which is no
longer the case. So open code it instead, using addresses that are
explicitly translated from kernel virtual to linear virtual.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel 97bbb54e4f arm64: vdso: avoid virt_to_page() translations on kernel symbols
The translation performed by virt_to_page() is only valid for linear
addresses, and kernel symbols are no longer in the linear mapping.
So perform the __pa() translation explicitly, which does the right
thing in either case, and only then translate to a struct page offset.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:31:49 +01:00
Ard Biesheuvel 8923a16686 arm64: remove the now unneeded relocate_initrd()
This removes the relocate_initrd() implementation and invocation, which are
no longer needed now that the placement of the initrd is guaranteed to be
covered by the linear mapping.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:20:45 +01:00
Ard Biesheuvel 177e15f0c1 arm64: add the initrd region to the linear mapping explicitly
Instead of going out of our way to relocate the initrd if it turns out
to occupy memory that is not covered by the linear mapping, just add the
initrd to the linear mapping. This puts the burden on the bootloader to
pass initrd= and mem= options that are mutually consistent.

Note that, since the placement of the linear region in the PA space is
also dependent on the placement of the kernel Image, which may reside
anywhere in memory, we may still end up with a situation where the initrd
and the kernel Image are simply too far apart to be covered by the linear
region.

Since we now leave it up to the bootloader to pass the initrd in memory
that is guaranteed to be accessible by the kernel, add a mention of this to
the arm64 boot protocol specification as well.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:20:45 +01:00
Ard Biesheuvel 3bab79edc6 Revert "arm64: account for sparsemem section alignment when choosing vmemmap offset"
This reverts commit 36e5cd6b89, since the
section alignment is now guaranteed by construction when choosing the
value of memstart_addr.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:15:08 +01:00
Ard Biesheuvel 06e9bf2fd9 arm64: choose memstart_addr based on minimum sparsemem section alignment
This redefines ARM64_MEMSTART_ALIGN in terms of the minimal alignment
required by sparsemem vmemmap. This comes down to using 1 GB for all
translation granules if CONFIG_SPARSEMEM_VMEMMAP is enabled.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:15:08 +01:00
Ard Biesheuvel 2958987f5d arm64/mm: ensure memstart_addr remains sufficiently aligned
After choosing memstart_addr to be the highest multiple of
ARM64_MEMSTART_ALIGN less than or equal to the first usable physical memory
address, we clip the memblocks to the maximum size of the linear region.
Since the kernel may be high up in memory, we take care not to clip the
kernel itself, which means we have to clip some memory from the bottom if
this occurs, to ensure that the distance between the first and the last
usable physical memory address can be covered by the linear region.

However, we fail to update memstart_addr if this clipping from the bottom
occurs, which means that we may still end up with virtual addresses that
wrap into the userland range. So increment memstart_addr as appropriate to
prevent this from happening.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-14 16:15:08 +01:00
Olof Johansson e24f89e37b This contains the rk3368-geekbox as new board, mailbox device
nodes for the core rk3368 and some cleanups for gpio-keys,
 mmc and tsadc.
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Merge tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

This contains the rk3368-geekbox as new board, mailbox device
nodes for the core rk3368 and some cleanups for gpio-keys,
mmc and tsadc.

* tag 'v4.7-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  Documentation: devicetree: rockchip: Document rk3368-GeekBox
  arm64: dts: rockchip: Add rk3368 GeekBox dts
  arm64: dts: rockchip: Clean up gpio-keys nodes
  dt-bindings: Add vendor prefix for GeekBuying.com
  arm64: dts: rockchip: Add rk3368 mailbox device nodes
  arm64: dts: rockchip: remove broken-cd from emmc and sdio
  arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 15:30:20 -07:00
Chanho Min 56a0eccdc0 arm64: dts: Add dts files for LG Electronics's lg1312 SoC
Add initial dtsi file to support lg1312 SoC which based on
Cortex-A53. Also add dts file to support lg1312 reference board
which based on lg1312 SoC.

Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 15:16:08 -07:00
Chanho Min b824a95481 arm64: defconfig: enable ARCH_LG1K
Enable building LG1K support in the defconfig.

Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 15:14:55 -07:00
Chanho Min 198ed9625a arm64: add Kconfig entry for LG1K SoC family
This patch introduces ARCH_LG1K to enable LG Electronics's LG1K SoC
family in Kconfig.

Signed-off-by: Chanho Min <chanho.min@lge.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 15:14:51 -07:00
Olof Johansson e43b7befc9 Renesas ARM64 Based SoC DT Updates for v4.7
* Use USB3.0 fallback compatibility string in DT for r8a7795 SoC
 * Add CAN support to DT for r8a7795 SoC
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Merge tag 'renesas-arm64-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt

Renesas ARM64 Based SoC DT Updates for v4.7

* Use USB3.0 fallback compatibility string in DT for r8a7795 SoC
* Add CAN support to DT for r8a7795 SoC

* tag 'renesas-arm64-dt-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: r8a7795: Use USB3.0 fallback compatibility string
  arm64: dts: r8a7795: Add CAN support
  arm64: dts: r8a7795: Add CAN external clock support

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 12:13:43 -07:00
Olof Johansson 49695dfac7 Renesas ARM64 Based SoC Cleanup for v4.7
* Use generic pinctrl properties in DT for salvator-x board
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Merge tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Renesas ARM64 Based SoC Cleanup for v4.7

* Use generic pinctrl properties in DT for salvator-x board

* tag 'renesas-arm64-cleanup-for-v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: salvator-x: use generic pinctrl properties

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 12:00:41 -07:00
Anup Patel d69dbd9f41 arm64: dts: Add ARM PL022 SPI DT nodes for NS2
We have two ARM PL022 SPI instances in NS2 SoC. On NS2 SVK,
one of the ARM PL022 SPI host has Silabs si3226x slic connected
to chip-select #0 whereas second ARM PL022 SPI host has Atmel
AT25 EEPROM connected to chip-select #0.

This patch adds ARM PL022, Silabs si3226x, and Atmel AT25
DT nodes in NS2 DT and NS2 SVK DT respectively.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13 10:34:29 -07:00
Anup Patel 59a5bedead arm64: dts: Move NS2 clock DT nodes to separate DT file
For more readabilty and consistency with other Broadcom SoCs, we move
all NS2 clock DT nodes from main SoC DT file to a separate DT file.

We also update the license header in ns2.dtsi as-per new Broadcom
convention.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13 10:34:29 -07:00
Anup Patel b2f9cd4845 arm64: dts: Add maintenance interrupt for GIC in NS2 DT
The KVM ARM64 requires GIC maintenance interrupt for VGIC emulation
so this patch adds the missing "interrupts" attribute to GIC node in
NS2 DT.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13 10:34:28 -07:00
Anup Patel 538fb37c13 arm64: dts: Add ARM PL330 DMA DT node for NS2
We have one ARM PL330 DMA instance with 8 channels in
NS2 SoC. Let's enable it for NS2 in NS2 DT.

Signed-off-by: Anup Patel <anup.patel@broadcom.com>
Reviewed-by: Ray Jui <rjui@broadcom.com>
Reviewed-by: Pramod KUMAR <pramodku@broadcom.com>
Reviewed-by: Scott Branden <sbranden@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-04-13 10:34:28 -07:00
Olof Johansson be0b0700ba Add support for a few more Amlogic S905/GXBB based boards: Hardkernel ODROID-C2
and Amlogic P200/P201 boards.
 We also fix the memory nodes on the Vega S95 DTS.
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Merge tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson into next/dt64

Add support for a few more Amlogic S905/GXBB based boards: Hardkernel ODROID-C2
and Amlogic P200/P201 boards.
We also fix the memory nodes on the Vega S95 DTS.

* tag 'gxbb-dt64' of https://github.com/carlocaione/linux-meson:
  ARM64: dts: amlogic: Add P200/P201 boards
  ARM64: dts: amlogic: add Hardkernel ODROID-C2
  Documentation: devicetree: amlogic: Document P20x and ODROID-C2 boards
  ARM64: dts: amlogic: update serial aliases
  ARM64: dts: amlogic: Clean up Vega S95 /memory nodes

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 10:19:35 -07:00
Olof Johansson a2c8eecb36 Update defconfig to have basic boot for the Amlogic meson boards.
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Merge tag 'gxbb-arm64' of https://github.com/carlocaione/linux-meson into next/arm64

Update defconfig to have basic boot for the Amlogic meson boards.

* tag 'gxbb-arm64' of https://github.com/carlocaione/linux-meson:
  arm64: defconfig: enable basic boot for Amlogic meson

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-04-13 10:16:36 -07:00
Linus Torvalds e012766258 ARM: SoC fixes
A batch of fixes for -rc4, for various platforms. Nothing really
 substantial and worth pointing out in particular; small fixes for various
 bugs, see shortlog for details.
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Merge tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC fixes from Olof Johansson:
 "A batch of fixes for -rc4, for various platforms.

  Nothing really substantial and worth pointing out in particular; small
  fixes for various bugs, see shortlog for details"

* tag 'armsoc-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  ARM: sa1100: remove references to the defunct handhelds.org
  bus: uniphier-system-bus: fix condition of overlap check
  ARM: uniphier: drop weird sizeof()
  ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type
  ARM: OMAP: Correct interrupt type for ARM TWD
  ARM: DRA722: Add ID detect for Silicon Rev 2.0
  ARM: dts: am43xx: fix edma memcpy channel allocation
  ARM: dts: AM43x-epos: Fix clk parent for synctimer
  ARM: OMAP2: Fix up interconnect barrier initialization for DRA7
  documentation: Fix pinctrl documentation for Meson8 / Meson8b
  ARM: dts: amlogic: Split pinctrl device for Meson8 / Meson8b
  ARM: mvebu: Correct unit address for linksys
  bus: mvebu-mbus: use %pa to print phys_addr_t
  arm64: dts: vulcan: Update PCI ranges
  ARM: u8500_defconfig: turn on the Synaptics RMI4 driver
  ARM: pxa: fix the number of DMA requestor lines
  ARM: OMAP2+: hwmod: Fix updating of sysconfig register
  ARM: OMAP2+: Use srst_udelay for USB on dm814x
2016-04-13 08:57:18 -07:00
Jisheng Zhang b5fda7ed5c arm64: cpuidle: make arm_cpuidle_suspend() a bit more efficient
Currently, we check two pointers: cpu_ops and cpu_suspend on every idle
state entry. These pointers check can be avoided:

If cpu_ops has not been registered, arm_cpuidle_init() will return
-EOPNOTSUPP, so arm_cpuidle_suspend() will never have chance to
run. In other word, the cpu_ops check can be avoid.

Similarly, the cpu_suspend check could be avoided in this hot path by
moving it into arm_cpuidle_init().

I measured the 4096 * time from arm_cpuidle_suspend entry point to the
cpu_psci_cpu_suspend entry point. HW platform is Marvell BG4CT STB
board.

1. only one shell, no other process, hot-unplug secondary cpus, execute
the following cmd

while true
do
	sleep 0.2
done

before the patch: 1581220ns

after the patch: 1579630ns

reduced by 0.1%

2. only one shell, no other process, hot-unplug secondary cpus, execute
the following cmd

while true
do
	md5sum /tmp/testfile
	sleep 0.2
done

NOTE: the testfile size should be larger than L1+L2 cache size

before the patch: 1961960ns
after the patch: 1912500ns

reduced by 2.5%

So the more complex the system load, the bigger the improvement.

Signed-off-by: Jisheng Zhang <jszhang@marvell.com>
Acked-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-13 14:49:23 +01:00
Kefeng Wang 7d7b4ae418 arm64: cpufeature: append additional id_aa64mmfr2 fields to cpufeature
There are some new cpu features which can be identified by id_aa64mmfr2,
this patch appends all fields of it.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-04-13 14:49:23 +01:00
Alim Akhtar afa05e55a0 arm64: dts: Add nodes for pdma0 and pdma1 for exynos7
This patch adds device tree nodes for pdma0 and pdma1 controllers
found on exynos7 SoCs.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-04-13 11:31:44 +02:00
Alim Akhtar 371feaff99 arm64: defconfig: Enable PL330 DMA controller
This patch enables PL330 DMA controller found on exynos7 SoCs.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-04-13 10:31:53 +02:00
Ingo Molnar 889fac6d67 Linux 4.6-rc3
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Merge tag 'v4.6-rc3' into perf/core, to refresh the tree

Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-04-13 08:57:03 +02:00
Liu Gang 22088b6ac3 arm64: dts: ls2080a: Add compatible "fsl,ls2080a-gpio" for ls2080a gpio nodes
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.

The chip-specific compatible "fsl,ls2080a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13 12:59:09 +08:00
Liu Gang c21de87db0 arm64: dts: ls1043a: Add compatible "fsl,qoriq-gpio" for ls1043a gpio nodes
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.

The chip-specific compatible "fsl,ls1043a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.

Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13 12:50:32 +08:00
Yuan Yao b3f85aba7b arm64: dts: ls2080a: update the DTS for QSPI and DSPI support
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Acked-by: Han xu <han.xu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13 10:27:26 +08:00
Yunhui Cui 730628f00c arm64: dts: ls1043a-rdb: add the DTS for DSPI support
This patch adds dts nodes for DSPI on LS1043A-RDB.

Signed-off-by: Yunhui Cui <B56489@freescale.com>
Signed-off-by: Yuan Yao <yao.yuan@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-04-13 09:48:59 +08:00
Rhyland Klein c1fd85b445 arm64: tegra: Add pinmux for Smaug board
Add pinmux node for Tegra210 Smaug board.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-12 17:17:01 +02:00
Jon Hunter 69e29bd1a5 arm64: tegra: Add stdout-path for various boards
For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.

For tegra132-norrin the alias serial0 is not defined and so add this.

This has been tested on tegra132-norrin and tegra210-p2371-0000.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:26 +02:00
Jon Hunter 2c9b050b6c arm64: tegra: Remove unused #power-domain-cells property
Remove the "#power-domain-cells" property which was incorrectly
included by commit e53095857166 ("arm64: tegra: Add Tegra210
support").

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:26 +02:00
Rhyland Klein a26f3963d9 arm64: tegra: Add gpio-keys nodes for Smaug
Add gpio-keys nodes for the volumn controls, lid switch, tablet mode and
power button.

Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
[treding@nvidia.com: use symbolic names for input types and codes]
[treding@nvidia.com: use wakeup-source instead of gpio-key,wakeup]
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:25 +02:00
Laxman Dewangan 0e91ba42be arm64: tegra: Enable power and volume keys on Jetson TX1
Add a gpio-keys device tree node to represent the Power, Volume Up and
Volume Down keys found on Jetson TX1.

Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:24 +02:00
Jon Hunter 5d17ba6e63 arm64: tegra: Add support for Google Pixel C
Add initial device-tree support for Google Pixel C (a.k.a. Smaug) based
upon Tegra210 SoC with 3 GiB of LPDDR4 RAM.

Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Alexandre Courbot <acourbot@nvidia.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Tested-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:39:19 +02:00
Sudeep Holla 81d22e89b4 arm64: tegra: Replace legacy *,wakeup property with wakeup-source
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.

This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.

Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:15 +02:00
Thierry Reding 68cd8b2e27 arm64: tegra: Fix copy/paste typo in several DTS includes
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.

Suggested-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:14 +02:00
Thierry Reding be70771d4c arm64: tegra: Remove 0, prefix from unit-addresses
When Tegra124 support was first merged the unit-addresses of all devices
were listed with a "0," prefix to encode the reg property's second cell.
It turns out that this notation is not correct, and the "," separator is
only used to separate fields in the unit address (such as the device and
function number in PCI devices), not individual cells for addresses with
more than one cell.

Signed-off-by: Thierry Reding <treding@nvidia.com>
2016-04-11 15:38:10 +02:00
Radim Krčmář 4a6cd3ba6f KVM/ARM Fixes for v4.6-rc4
Addresses:
  - Wrong indentation in the PMU code from the merge window
  - A long-time bug occuring with running ntpd on the host, candidate for stable
  - Properly handle (and warn about) the unsupported configuration of running on
    systems with less than 40 bits of PA space
  - More fixes to the PM and hotplug notifier stuff from the merge window
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Merge tag 'kvm-arm-for-4.6-rc4' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm

KVM/ARM Fixes for v4.6-rc4

Addresses:
 - Wrong indentation in the PMU code from the merge window
 - A long-time bug occuring with running ntpd on the host, candidate for stable
 - Properly handle (and warn about) the unsupported configuration of running on
   systems with less than 40 bits of PA space
 - More fixes to the PM and hotplug notifier stuff from the merge window
2016-04-08 14:17:27 +02:00
Marc Zyngier 6141570c36 arm64: KVM: Warn when PARange is less than 40 bits
We always thought that 40bits of PA range would be the minimum people
would actually build. Anything less is terrifyingly small.

Turns out that we were both right and wrong. Nobody has ever built
such a system, but the ARM Foundation Model has a PARange set to 36bits.
Just because we can. Oh well. Now, the KVM API explicitely says that
we offer a 40bit PA space to the VM, so we shouldn't run KVM on
the Foundation Model at all.

That being said, this patch offers a less agressive alternative, and
loudly warns about the configuration being unsupported. You'll still
be able to run VMs (at your own risks, though).

This is just a workaround until we have a proper userspace API where
we report the PARange to userspace.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2016-04-06 13:33:14 +02:00
Linus Torvalds 541d8f4d59 Miscellaneous bugfixes. ARM and s390 are new from the merge window,
others are usual stable material.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
 "Miscellaneous bugfixes.

  The ARM and s390 fixes are for new regressions from the merge window,
  others are usual stable material"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  compiler-gcc: disable -ftracer for __noclone functions
  kvm: x86: make lapic hrtimer pinned
  s390/mm/kvm: fix mis-merge in gmap handling
  kvm: set page dirty only if page has been writable
  KVM: x86: reduce default value of halt_poll_ns parameter
  KVM: Hyper-V: do not do hypercall userspace exits if SynIC is disabled
  KVM: x86: Inject pending interrupt even if pending nmi exist
  arm64: KVM: Register CPU notifiers when the kernel runs at HYP
  arm64: kvm: 4.6-rc1: Fix VTCR_EL2 VS setting
2016-04-05 16:16:00 -07:00
Andreas Färber fd7b980c9e arm64: dts: rockchip: Add rk3368 GeekBox dts
The GeekBox contains an MXM3 module with a Rockchip RK3368 SoC.
Some connectors are available directly on the module.

This adds initial support, namely serial, USB, GMAC, eMMC, IR and TSADC.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-31 18:59:53 +02:00
Wang Nan 1879445dfa perf/core: Set event's default ::overflow_handler()
Set a default event->overflow_handler in perf_event_alloc() so don't
need to check event->overflow_handler in __perf_event_overflow().
Following commits can give a different default overflow_handler.

Initial idea comes from Peter:

  http://lkml.kernel.org/r/20130708121557.GA17211@twins.programming.kicks-ass.net

Since the default value of event->overflow_handler is not NULL, existing
'if (!overflow_handler)' checks need to be changed.

is_default_overflow_handler() is introduced for this.

No extra performance overhead is introduced into the hot path because in the
original code we still need to read this handler from memory. A conditional
branch is avoided so actually we remove some instructions.

Signed-off-by: Wang Nan <wangnan0@huawei.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Cc: <pi3orama@163.com>
Cc: Alexander Shishkin <alexander.shishkin@linux.intel.com>
Cc: Alexei Starovoitov <ast@kernel.org>
Cc: Arnaldo Carvalho de Melo <acme@redhat.com>
Cc: Brendan Gregg <brendan.d.gregg@gmail.com>
Cc: He Kuang <hekuang@huawei.com>
Cc: Jiri Olsa <jolsa@kernel.org>
Cc: Jiri Olsa <jolsa@redhat.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Masami Hiramatsu <masami.hiramatsu.pt@hitachi.com>
Cc: Namhyung Kim <namhyung@kernel.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Stephane Eranian <eranian@google.com>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Vince Weaver <vincent.weaver@maine.edu>
Cc: Zefan Li <lizefan@huawei.com>
Link: http://lkml.kernel.org/r/1459147292-239310-3-git-send-email-wangnan0@huawei.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-03-31 10:30:47 +02:00
Suzuki K Poulose cb678d6016 arm64: kvm: 4.6-rc1: Fix VTCR_EL2 VS setting
When we detect support for 16bit VMID in ID_AA64MMFR1, we set the
VTCR_EL2_VS field to 1 to make use of 16bit vmids. But, with
commit 3a3604bc5e ("arm64: KVM: Switch to C-based stage2 init")
this is broken and we corrupt VTCR_EL2:T0SZ instead of updating the VS
field. VTCR_EL2_VS was actually defined to the field shift (19) and
not the real value for VS. This patch fixes the issue.

Fixes: commit 3a3604bc5e ("arm64: KVM: Switch to C-based stage2 init")
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2016-03-30 22:09:15 +02:00
Kevin Hilman ac40004db3 ARM64: dts: amlogic: Add P200/P201 boards
Add minimal DT files for the Amlogic P20x development boards, based on
the Amlogic S905/GXBB SoC.

Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2016-03-30 19:52:34 +02:00
Kevin Hilman 855960342d ARM64: dts: amlogic: add Hardkernel ODROID-C2
Add minimal DT files for the Hardkernel ODROID-C2 board based on the
Amlogic S905/GXBB SoC.

Used the other gxbb boards from Andreas Färber as a starting point.

Cc: Andreas Färber <afaerber@suse.de>
Cc: Carlo Caione <carlo@endlessm.com>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2016-03-30 19:52:33 +02:00
Kevin Hilman 962f271ec9 ARM64: dts: amlogic: update serial aliases
Apparently, it's not valid to have an alias point to a disabled device.
Fix this by moving the aliases that are used (serial0) into the files
that use them, and remove aliases to disabled devices (serial1).

Suggested-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
Acked-by: Arnd Bergmann <arnd@arndb.de>
2016-03-30 19:52:33 +02:00
Andreas Färber 65eb22ea1d ARM64: dts: amlogic: Clean up Vega S95 /memory nodes
Resolve the following warnings from new dtc by adding the unit address:

    DTC     arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-pro.dtb
  Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
    DTC     arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-meta.dtb
  Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name
    DTC     arch/arm64/boot/dts/amlogic/meson-gxbb-vega-s95-telos.dtb
  Warning (unit_address_vs_reg): Node /memory has a reg or ranges property, but no unit name

Fixes: cc733bc906 ("ARM64: dts: amlogic: Add Tronsmart Vega S95 configs")
Signed-off-by: Andreas Färber <afaerber@suse.de>
2016-03-30 19:52:33 +02:00
Kevin Hilman 97d8eb16aa arm64: defconfig: enable basic boot for Amlogic meson
Enables basic arch and serial console support for Amlogic meson family
SoCs.

Tested with Amlogic P200 and Hardkernel ODROID-C2 boards.

Signed-off-by: Kevin Hilman <khilman@baylibre.com>
Reviewed-by: Andreas Färber <afaerber@suse.de>
2016-03-30 19:50:47 +02:00
Shaohui Xie ec05e9cc6a arm64: dts: add LS1043a-QDS board support
The LS1043a-QDS board is a high-performance computing, evaluation,
development, and test platform supporting the LS1043a SoC.

shawn.guo: sort the entries in Makefile alphabetcially

Signed-off-by: Shaohui Xie <Shaohui.Xie@freescale.com>
Signed-off-by: Mingkai Hu <Mingkai.Hu@freescale.com>
Signed-off-by: Hou Zhiqiang <Zhiqiang.Hou@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
2016-03-30 21:57:46 +08:00
Jayachandran C e6cc3be552 arm64: dts: vulcan: Update PCI ranges
The PCI memory windows available in vulcan.dtsi are limited to 128MB
for 32-bit BARs, and 4GB for 64-bit BARs. Given the memory mapped IO
space available in arm64, these windows can be increased substantially
to support more use cases.

The change increases the 32-bit window to 256MB and the 64-bit window
to 128 GB. The firmware on vulcan boards will use these ranges as well.

PCI IO windows are not supported on Vulcan, so remove them instead of
keeping an unused value.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-30 00:26:16 +02:00
Andreas Färber 479d75b760 arm64: dts: rockchip: Clean up gpio-keys nodes
Drop superfluous #address-cells and #size-cells.
Use KEY_POWER define for 116.
Rename sub-nodes to avoid new dtc warnings.

Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Andreas Färber <afaerber@suse.de>
Reviewed-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-29 21:37:12 +02:00
Caesar Wang 6e7f9f5ad5 arm64: dts: rockchip: Add rk3368 mailbox device nodes
This adds mailbox device nodes in dts.

Mailbox is used by the Rockchip CPU cores to communicate
requests to MCU processor.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-29 21:36:57 +02:00
Will Deacon 431597bb95 arm64: defconfig: updates for 4.6
A few defconfig updates got dropped on the floor during the merge window,
so I've rounded up the remainder here:

  * Fix duplicate definition of MMC_BLOCK_MINORS and bump to 32 for
    msm8916

  * CPUFreq support for the Juno platform, using the MHU/SCPI interface

  * Removal of the default command line, which assumed a console called
    ttyAMA0

  * Bits and pieces for the Hi6220 (96Boards HiKey)

Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-03-29 16:56:00 +01:00
Shannon Zhao b8cfadfcef arm64: perf: Move PMU register related defines to asm/perf_event.h
To use the ARMv8 PMU related register defines from the KVM code, we move
the relevant definitions to asm/perf_event.h header file and rename them
with prefix ARMV8_PMU_. This allows us to get rid of kvm_perf_event.h.

Signed-off-by: Anup Patel <anup.patel@linaro.org>
Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-03-29 16:04:57 +01:00
James Morse a6002ec5a8 arm64: opcodes.h: Add arm big-endian config options before including arm header
arm and arm64 use different config options to specify big endian. This
needs taking into account when including code/headers between the two
architectures.

A case in point is PAN, which uses the __instr_arm() macro to output
instructions. The macro comes from opcodes.h, which lives under arch/arm.
On a big-endian build the mismatched config options mean the instruction
isn't byte swapped correctly, resulting in undefined instruction exceptions
during boot:

| alternatives: patching kernel code
| kdevtmpfs[87]: undefined instruction: pc=ffffffc0004505b4
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| kdevtmpfs[87]: undefined instruction: pc=ffffffc00076231c
| Internal error: Oops - undefined instruction: 0 [#1] SMP
| Modules linked in:
| CPU: 0 PID: 87 Comm: kdevtmpfs Not tainted 4.1.16+ #5
| Hardware name: Hisilicon PhosphorHi1382 EVB (DT)
| task: ffffffc336591700 ti: ffffffc3365a4000 task.ti: ffffffc3365a4000
| PC is at dump_instr+0x68/0x100
| LR is at do_undefinstr+0x1d4/0x2a4
| pc : [<ffffffc00076231c>] lr : [<ffffffc0000811d4>] pstate: 604001c5
| sp : ffffffc3365a6450

Cc: <stable@vger.kernel.org> #4.3.x-
Reported-by: Hanjun Guo <guohanjun@huawei.com>
Tested-by: Xuefeng Wang <wxf.wang@hisilicon.com>
Signed-off-by: James Morse <james.morse@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-03-29 16:04:57 +01:00
Alim Akhtar fbfcf4bf1c arm64: dts: exynos: Add TMU node for exynos7
This patch adds TMU node, related temprature sensor and triping
point data for Atlas cpu core found on exynos7 SoC.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-03-29 10:41:24 +09:00
Simon Horman 81ae0ac31b arm64: dts: r8a7795: Use USB3.0 fallback compatibility string
Use recently added fallback compatibility string in r8a7795 device tree.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-28 08:52:47 +09:00
Ramesh Shanmugasundaram 308b7e4ba6 arm64: dts: r8a7795: Add CAN support
Adds CAN controller nodes for r8a7795.

Note: CAN channel register base address mentioned in R-Car Gen3 Hardware
User Manual v0.5E is incorrect. The corrected base addresses are:

CAN Channel 0 - 0xe6c30000
CAN Channel 1 - 0xe6c38000

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-03-28 08:52:47 +09:00
Ramesh Shanmugasundaram 7811482f0e arm64: dts: r8a7795: Add CAN external clock support
Adds external CAN clock node for r8a7795. This clock can be used as
fCAN clock of CAN and CAN FD controller.

Signed-off-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-03-28 08:52:47 +09:00
Simon Horman fa3d2aede8 arm64: dts: salvator-x: use generic pinctrl properties
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.

This patch updates the kzm9g device tree to use the generic properties.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-03-28 08:50:52 +09:00
Shawn Lin 1ade61c141 arm64: dts: rockchip: remove broken-cd from emmc and sdio
Only one of "broken-cd" and "non-removable" should be supplied
according to Documentation/devicetree/bindings/mmc/mmc.txt.
Obviously emmc and sdio-wifi are non-removable devices, while
broken-cd is for removable device whose card detect pin is broken.

Signed-off-by: Shawn Lin <shawn.lin@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 00:54:39 +01:00
Caesar Wang 04317584ff arm64: dts: rockchip: fix the incorrect otp-out pin on rk3368
This patch fixes the incorrect Over-temperature protection pin.
since the rk3368 io list said the otp pin is gpio0a3.

Anyway, that should be fixed in here.

Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
2016-03-27 00:54:39 +01:00
Alexander Potapenko be7635e728 arch, ftrace: for KASAN put hard/soft IRQ entries into separate sections
KASAN needs to know whether the allocation happens in an IRQ handler.
This lets us strip everything below the IRQ entry point to reduce the
number of unique stack traces needed to be stored.

Move the definition of __irq_entry to <linux/interrupt.h> so that the
users don't need to pull in <linux/ftrace.h>.  Also introduce the
__softirq_entry macro which is similar to __irq_entry, but puts the
corresponding functions to the .softirqentry.text section.

Signed-off-by: Alexander Potapenko <glider@google.com>
Acked-by: Steven Rostedt <rostedt@goodmis.org>
Cc: Christoph Lameter <cl@linux.com>
Cc: Pekka Enberg <penberg@kernel.org>
Cc: David Rientjes <rientjes@google.com>
Cc: Joonsoo Kim <iamjoonsoo.kim@lge.com>
Cc: Andrey Konovalov <adech.fo@gmail.com>
Cc: Dmitry Vyukov <dvyukov@google.com>
Cc: Andrey Ryabinin <ryabinin.a.a@gmail.com>
Cc: Konstantin Serebryany <kcc@google.com>
Cc: Dmitry Chernenkov <dmitryc@google.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-03-25 16:37:42 -07:00
Linus Torvalds 9d854607f9 2nd set of arm64 updates for 4.6:
- KASLR bug fixes: use callee-saved register, boot-time I-cache
   maintenance
 - inv_entry asm macro fix (EL0 check typo)
 - pr_notice("Virtual kernel memory layout...") splitting
 - Clean-ups: use p?d_set_huge consistently, allow preemption around
   copy_to_user_page, remove unused __local_flush_icache_all()
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull second set of arm64 updates from Catalin Marinas:

 - KASLR bug fixes: use callee-saved register, boot-time I-cache
   maintenance

 - inv_entry asm macro fix (EL0 check typo)

 - pr_notice("Virtual kernel memory layout...") splitting

 - Clean-ups: use p?d_set_huge consistently, allow preemption around
   copy_to_user_page, remove unused __local_flush_icache_all()

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: mm: allow preemption in copy_to_user_page
  arm64: consistently use p?d_set_huge
  arm64: kaslr: use callee saved register to preserve SCTLR across C call
  arm64: Split pr_notice("Virtual kernel memory layout...") into multiple pr_cont()
  arm64: drop unused __local_flush_icache_all()
  arm64: fix KASLR boot-time I-cache maintenance
  arm64/kernel: fix incorrect EL0 check in inv_entry macro
2016-03-24 19:13:59 -07:00
Linus Torvalds 8a20a04bda ARM: DT changes, part 2
Here are some final updates for ARM SoC specific dts files:
 
 * The i.MX changes were sent relatively late, and had a dependency
   on the clk tree, so I delayed that a bit. Support for the new
   i.MX6qp SoC and a couple of new boards is added in this branch.
 
 * Uniphier renames a few files to match the final product names
   that were decided by the company, kudos to the kernel developer(s)
   for getting support upstream before the product release.
   Also two boards are added. The patches were posted early enough
   and nice overall, but we forgot to apply them and decided to
   give it some more time in linux-next
 
 * at91 has two small bug fixes.
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Merge tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull more ARM DT changes from Arnd Bergmann:
 "Here are some final updates for ARM SoC specific dts files:

   - The i.MX changes were sent relatively late, and had a dependency on
     the clk tree, so I delayed that a bit.  Support for the new i.MX6qp
     SoC and a couple of new boards is added in this branch.

   - Uniphier renames a few files to match the final product names that
     were decided by the company, kudos to the kernel developer(s) for
     getting support upstream before the product release.  Also two
     boards are added.  The patches were posted early enough and nice
     overall, but we forgot to apply them and decided to give it some
     more time in linux-next

   - at91 has two small bug fixes"

* tag 'armsoc-dt2' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (83 commits)
  ARM: dts: at91: sama5d4 Xplained: don't disable hsmci regulator
  ARM: dts: at91: sama5d3 Xplained: don't disable hsmci regulator
  ARM: dts: uniphier: add pinmux node for I2C ch4
  ARM: dts: uniphier: add @{address} to EEPROM node
  ARM: dts: uniphier: add PH1-Pro4 Sanji board support
  ARM: dts: uniphier: add PH1-Pro4 Ace board support
  ARM: dts: uniphier: enable I2C channel 2 of ProXstream2 Gentil board
  ARM: dts: uniphier: add EEPROM node for ProXstream2 Gentil board
  ARM: dts: uniphier: add reference clock nodes
  ARM: dts: uniphier: rework UniPhier System Bus nodes
  ARM: dts: uniphier: factor out ranges property of support card
  arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20
  ARM: dts: imx53-qsb: Fix gpio button polarity
  ARM: dts: vfxxx: Add DAC node for Vybrid SoC
  ARM: dts: imx6q: add missing links between ipu2 and mipi dsi
  ARM: dts: imx: Add support for Advantech/GE B850v3
  ARM: dts: imx: Add support for Advantech/GE B650v3
  ARM: dts: imx: Add support for Advantech/GE B450v3
  ARM: dts: imx: Add support for Advantech/GE Bx50v3
  ARM: dts: imx: Add Advantech BA-16 Qseven module
  ...
2016-03-24 19:01:38 -07:00
Linus Torvalds 0f0fbec9c3 Merge branch 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull irq fixes from Thomas Gleixner:
 "A small set of fixes for the usual ARM/SOC irqchip drivers

   - A set of fixes for mbigen to handle multiple devices in a hardware
     module proper

   - A cleanup for the mbigen config option which was pointlessly user
     configurable.

   - A cleanup for tegra replacing open coded functionality by the
     proper core function

  The config cleanup touches arch/arm64/Kconfig.platforms to select the
  irq chip for the related platform"

* 'irq-urgent-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  irqchip/mbigen: Make CONFIG_HISILICON_IRQ_MBIGEN a hidden option
  ARM64: Kconfig: Select mbigen interrupt controller on Hisilicon platform
  irqchip/mbigen: Handle multiple device nodes in a mbigen module
  irqchip/mbigen: Adjust DT bindings to handle multiple devices in a module
  irqchip/tegra: Switch to use irq_domain_free_irqs_common
2016-03-24 10:29:44 -07:00
Mark Rutland 691b1e2ebf arm64: mm: allow preemption in copy_to_user_page
Currently we disable preemption in copy_to_user_page; a behaviour that
we inherited from the 32-bit arm code. This was necessary for older
cores without broadcast data cache maintenance, and ensured that cache
lines were dirtied and cleaned by the same CPU. On these systems dirty
cache line migration was not possible, so this was sufficient to
guarantee coherency.

On contemporary systems, cache coherence protocols permit (dirty) cache
lines to migrate between CPUs as a result of speculation, prefetching,
and other behaviours. To account for this, in ARMv8 data cache
maintenance operations are broadcast and affect all data caches in the
domain associated with the VA (i.e. ISH for kernel and user mappings).

In __switch_to we ensure that tasks can be safely migrated in the middle
of a maintenance sequence, using a dsb(ish) to ensure prior explicit
memory accesses are observed and cache maintenance operations are
completed before a task can be run on another CPU.

Given the above, it is not necessary to disable preemption in
copy_to_user_page. This patch removes the preempt_{disable,enable}
calls, permitting preemption.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-24 16:32:54 +00:00
Mark Rutland c661cb1c53 arm64: consistently use p?d_set_huge
Commit 324420bf91 ("arm64: add support for ioremap() block
mappings") added new p?d_set_huge functions which do the hard work to
generate and set a correct block entry.

These differ from open-coded huge page creation in the early page table
code by explicitly setting the P?D_TYPE_SECT bits (which are implicitly
retained by mk_sect_prot() for any valid prot), but are otherwise
identical (and cannot fail on arm64).

For simplicity and consistency, make use of these in the initial page
table creation code.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-24 16:32:29 +00:00
Ard Biesheuvel d5e5743797 arm64: kaslr: use callee saved register to preserve SCTLR across C call
The KASLR code incorrectly expects the contents of x18 to be preserved
across a call into C code, and uses it to stash the contents of SCTLR_EL1
before enabling the MMU. If the MMU needs to be disabled again to create
the randomized kernel mapping, x18 is written back to SCTLR_EL1, which is
likely to crash the system if x18 has been clobbered by kasan_early_init()
or kaslr_early_init(). So use x22 instead, which is not in use so far in
head.S

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-24 16:19:24 +00:00
MaJun dd17a3c40d ARM64: Kconfig: Select mbigen interrupt controller on Hisilicon platform
As a interrupt controller used on some of hisilicon SOCs(660,1610 etc.),
mbigen driver should be enabled when CONFIG_ARCH_HISI is enabled.

Signed-off-by: Ma Jun <majun258@huawei.com>
Cc: mark.rutland@arm.com
Cc: jason@lakedaemon.net
Cc: marc.zyngier@arm.com
Cc: Catalin.Marinas@arm.com
Cc: guohanjun@huawei.com
Cc: Will.Deacon@arm.com
Cc: huxinwei@huawei.com
Cc: lizefan@huawei.com
Cc: dingtianhong@huawei.com
Cc: zhaojunhua@hisilicon.com
Cc: liguozhu@hisilicon.com
Cc: linux-arm-kernel@lists.infradead.org
Link: http://lkml.kernel.org/r/1458723993-21044-2-git-send-email-majun258@huawei.com
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-03-23 12:02:29 +01:00
Linus Torvalds b91d9c6716 * Build fixes for PPC KVM
* Miscellaneous bugfixes for ARM KVM
 * Cleanup of memory barrier and removal of redundant barriers
 * x86 fixes: page tracking oops, support for old buggy KVM nested on 4.5
 * Support for protection keys in guests
 * Lockdep fix
 * Another conversion to simple wait queues and raw spinlocks,
   backported from PREEMPT_RT
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull more KVM updates from Paolo Bonzini:
 "Second round of KVM changes for 4.6:

   - build fixes for PPC KVM
   - miscellaneous bugfixes for ARM KVM
   - cleanup of memory barrier and removal of redundant barriers
   - x86 fixes: page tracking oops, support for old buggy KVM nested on 4.5
   - support for protection keys in guests
   - lockdep fix
   - another conversion to simple wait queues and raw spinlocks,
     backported from PREEMPT_RT"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (27 commits)
  KVM: page_track: fix access to NULL slot
  KVM: PPC: do not compile in vfio.o unconditionally
  kvm, rt: change async pagefault code locking for PREEMPT_RT
  KVM/PPC: update the comment of memory barrier in the kvmppc_prepare_to_enter()
  KVM/x86: update the comment of memory barrier in the vcpu_enter_guest()
  KVM: Replace smp_mb() with smp_load_acquire() in the kvm_flush_remote_tlbs()
  KVM/x86: Call smp_wmb() before increasing tlbs_dirty
  KVM: Replace smp_mb() with smp_mb_after_atomic() in the kvm_make_all_cpus_request()
  KVM/x86: Replace smp_mb() with smp_store_mb/release() in the walk_shadow_page_lockless_begin/end()
  KVM: Remove redundant smp_mb() in the kvm_mmu_commit_zap_page()
  KVM, pkeys: expose CPUID/CR4 to guest
  KVM, pkeys: add pkeys support for permission_fault
  KVM, pkeys: introduce pkru_mask to cache conditions
  KVM, pkeys: save/restore PKRU when guest/host switches
  x86: pkey: introduce write_pkru() for KVM
  KVM, pkeys: add pkeys support for xsave state
  KVM, pkeys: disable pkeys for guests in non-paging mode
  KVM: x86: remove magic number with enum cpuid_leafs
  KVM: MMU: return page fault error code from permission_fault
  KVM: fix spin_lock_init order on x86
  ...
2016-03-22 16:28:22 -07:00
Linus Torvalds b4af7f773e IOMMU Updates for Linux v4.6
This time with:
 
 	* Updates for the Exynos IOMMU driver to make use of default
 	  domains and to add support for the SYSMMU v5
 
 	* New Mediatek IOMMU driver
 
 	* Support for the ARMv7 short descriptor format in the
 	  io-pgtable code
 
 	* Default domain support for the ARM SMMU
 
 	* Couple of other small fixes all over the place
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Merge tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu

Pull IOMMU updates from Joerg Roedel:

 - updates for the Exynos IOMMU driver to make use of default domains
   and to add support for the SYSMMU v5

 - new Mediatek IOMMU driver

 - support for the ARMv7 short descriptor format in the io-pgtable code

 - default domain support for the ARM SMMU

 - couple of other small fixes all over the place

* tag 'iommu-updates-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/joro/iommu: (41 commits)
  iommu/ipmmu-vmsa: Add r8a7795 DT binding
  iommu/mediatek: Check for NULL instead of IS_ERR()
  iommu/io-pgtable-armv7s: Fix kmem_cache_alloc() flags
  iommu/mediatek: Fix handling of of_count_phandle_with_args result
  iommu/dma: Fix NEED_SG_DMA_LENGTH dependency
  iommu/mediatek: Mark PM functions as __maybe_unused
  iommu/mediatek: Select ARM_DMA_USE_IOMMU
  iommu/exynos: Use proper readl/writel register interface
  iommu/exynos: Pointers are nto physical addresses
  dts: mt8173: Add iommu/smi nodes for mt8173
  iommu/mediatek: Add mt8173 IOMMU driver
  memory: mediatek: Add SMI driver
  dt-bindings: mediatek: Add smi dts binding
  dt-bindings: iommu: Add binding for mediatek IOMMU
  iommu/ipmmu-vmsa: Use ARCH_RENESAS
  iommu/exynos: Support multiple attach_device calls
  iommu/exynos: Add Maintainers entry for Exynos SYSMMU driver
  iommu/exynos: Add support for v5 SYSMMU
  iommu/exynos: Update device tree documentation
  iommu/exynos: Add support for SYSMMU controller with bogus version reg
  ...
2016-03-22 11:57:43 -07:00
Linus Torvalds 2c856e14da arm[64] perf updates for 4.6:
- Initial support for ARMv8.1 CPU PMUs
 
 - Support for the CPU PMU in Cavium ThunderX
 
 - CPU PMU support for systems running 32-bit Linux in secure mode
 
 - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)
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Merge tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm[64] perf updates from Will Deacon:
 "I have another mixed bag of ARM-related perf patches here.

  It's about 25% CPU and 75% interconnect, but with drivers/bus/
  languishing without an obvious maintainer or tree, Olof and I agreed
  to keep all of these PMU patches together.  I suspect a whole load of
  code from drivers/bus/arm-* can be moved under drivers/perf/, so
  that's on the radar for the future.

  Summary:

   - Initial support for ARMv8.1 CPU PMUs

   - Support for the CPU PMU in Cavium ThunderX

   - CPU PMU support for systems running 32-bit Linux in secure mode

   - Support for the system PMU in ARM CCI-550 (Cache Coherent Interconnect)"

* tag 'arm64-perf' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (26 commits)
  drivers/perf: arm_pmu: avoid NULL dereference when not using devicetree
  arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC
  arm-cci: remove unused variable
  arm-cci: don't return value from void function
  arm-cci: make private functions static
  arm-cci: CoreLink CCI-550 PMU driver
  arm-cci500: Rearrange PMU driver for code sharing with CCI-550 PMU
  arm-cci: CCI-500: Work around PMU counter writes
  arm-cci: Provide hook for writing to PMU counters
  arm-cci: Add helper to enable PMU without synchornising counters
  arm-cci: Add routines to save/restore all counters
  arm-cci: Get the status of a counter
  arm-cci: write_counter: Remove redundant check
  arm-cci: Delay PMU counter writes to pmu::pmu_enable
  arm-cci: Refactor CCI PMU enable/disable methods
  arm-cci: Group writes to counter
  arm-cci: fix handling cpumask_any_but return value
  arm-cci: simplify sysfs attr handling
  drivers/perf: arm_pmu: implement CPU_PM notifier
  arm64: dts: Add Cavium ThunderX specific PMU
  ...
2016-03-21 13:14:16 -07:00
Joerg Roedel 70cf769c5b Merge branches 'arm/rockchip', 'arm/exynos', 'arm/smmu', 'arm/mediatek', 'arm/io-pgtable', 'arm/renesas' and 'core' into next 2016-03-21 14:58:47 +01:00
Catalin Marinas a6cdf1c08c kvm: arm64: Disable compiler instrumentation for hypervisor code
With the recent rewrite of the arm64 KVM hypervisor code in C, enabling
certain options like KASAN would allow the compiler to generate memory
accesses or function calls to addresses not mapped at EL2. This patch
disables the compiler instrumentation on the arm64 hypervisor code for
gcov-based profiling (GCOV_KERNEL), undefined behaviour sanity checker
(UBSAN) and kernel address sanitizer (KASAN).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Christoffer Dall <christoffer.dall@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Paolo Bonzini <pbonzini@redhat.com>
Cc: <stable@vger.kernel.org> # 4.5+
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2016-03-21 14:02:17 +01:00
Catalin Marinas f09f1bacfe arm64: Split pr_notice("Virtual kernel memory layout...") into multiple pr_cont()
The printk() implementation has a limit of LOG_LINE_MAX (== 1024 - 32)
buffer per call which the arm64 mem_init() breaches when printing the
virtual memory layout with CONFIG_KASAN enabled. The result is that the
last line is no longer printed. This patch splits the call into a
pr_notice() + additional pr_cont() calls.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2016-03-21 12:19:12 +00:00
Kefeng Wang cc7c0cda8f arm64: drop unused __local_flush_icache_all()
After commit 65da0a8e34 ("arm64: use non-global mappings for UEFI
runtime regions"), nobody use __local_flush_icache_all() anymore,
so drop it.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-21 12:10:03 +00:00
Mark Rutland b90b4a608e arm64: fix KASLR boot-time I-cache maintenance
Commit f80fb3a3d5 ("arm64: add support for kernel ASLR") missed a
DSB necessary to complete I-cache maintenance in the primary boot path,
and hence stale instructions may still be present in the I-cache and may
be executed until the I-cache maintenance naturally completes.

Since commit 8ec4198743 ("arm64: mm: ensure patched kernel text is
fetched from PoU"), all CPUs invalidate their I-caches after their MMU
is enabled. Prior a CPU's MMU having been enabled, arbitrary lines may
have been fetched from the PoC into I-caches. We never patch text
expected to be executed with the MMU off. Thus, it is unnecessary to
perform broadcast I-cache maintenance in the primary boot path.

This patch reduces the scope of the I-cache maintenance to the local
CPU, and adds the missing DSB with similar scope, matching prior
maintenance in the primary boot path.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Ard Biesehvuel <ard.biesheuvel@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-21 12:08:50 +00:00
Ard Biesheuvel b660950c60 arm64/kernel: fix incorrect EL0 check in inv_entry macro
The implementation of macro inv_entry refers to its 'el' argument without
the required leading backslash, which results in an undefined symbol
'el' to be passed into the kernel_entry macro rather than the index of
the exception level as intended.

This undefined symbol strangely enough does not result in build failures,
although it is visible in vmlinux:

     $ nm -n vmlinux |head
                      U el
     0000000000000000 A _kernel_flags_le_hi32
     0000000000000000 A _kernel_offset_le_hi32
     0000000000000000 A _kernel_size_le_hi32
     000000000000000a A _kernel_flags_le_lo32
     .....

However, it does result in incorrect code being generated for invalid
exceptions taken from EL0, since the argument check in kernel_entry
assumes EL1 if its argument does not equal '0'.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-21 12:05:34 +00:00
Marc Zyngier 2510ffe17f arm64: KVM: Turn kvm_ksym_ref into a NOP on VHE
When running with VHE, there is no need to translate kernel pointers
to the EL2 memory space, since we're already there (and we have a much
saner memory map to start with).

Unfortunately, kvm_ksym_ref is getting in the way, and the first
call into the "hypervisor" section is going to end up in fireworks,
since we're now branching into nowhereland. Meh.

A potential solution is to test if VHE is engaged or not, and only
perform the translation in the negative case. With this in place,
VHE is able to run again.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
2016-03-21 10:47:18 +01:00
Linus Torvalds 24b5e20f11 Merge branch 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull EFI updates from Ingo Molnar:
 "The main changes are:

   - Use separate EFI page tables when executing EFI firmware code.
     This isolates the EFI context from the rest of the kernel, which
     has security and general robustness advantages.  (Matt Fleming)

   - Run regular UEFI firmware with interrupts enabled.  This is already
     the status quo under other OSs.  (Ard Biesheuvel)

   - Various x86 EFI enhancements, such as the use of non-executable
     attributes for EFI memory mappings.  (Sai Praneeth Prakhya)

   - Various arm64 UEFI enhancements.  (Ard Biesheuvel)

   - ... various fixes and cleanups.

  The separate EFI page tables feature got delayed twice already,
  because it's an intrusive change and we didn't feel confident about
  it - third time's the charm we hope!"

* 'efi-core-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (37 commits)
  x86/mm/pat: Fix boot crash when 1GB pages are not supported by the CPU
  x86/efi: Only map kernel text for EFI mixed mode
  x86/efi: Map EFI_MEMORY_{XP,RO} memory region bits to EFI page tables
  x86/mm/pat: Don't implicitly allow _PAGE_RW in kernel_map_pages_in_pgd()
  efi/arm*: Perform hardware compatibility check
  efi/arm64: Check for h/w support before booting a >4 KB granular kernel
  efi/arm: Check for LPAE support before booting a LPAE kernel
  efi/arm-init: Use read-only early mappings
  efi/efistub: Prevent __init annotations from being used
  arm64/vmlinux.lds.S: Handle .init.rodata.xxx and .init.bss sections
  efi/arm64: Drop __init annotation from handle_kernel_image()
  x86/mm/pat: Use _PAGE_GLOBAL bit for EFI page table mappings
  efi/runtime-wrappers: Run UEFI Runtime Services with interrupts enabled
  efi: Reformat GUID tables to follow the format in UEFI spec
  efi: Add Persistent Memory type name
  efi: Add NV memory attribute
  x86/efi: Show actual ending addresses in efi_print_memmap
  x86/efi/bgrt: Don't ignore the BGRT if the 'valid' bit is 0
  efivars: Use to_efivar_entry
  efi: Runtime-wrapper: Get rid of the rtc_lock spinlock
  ...
2016-03-20 18:58:18 -07:00
Linus Torvalds 915c56bc01 ARM: 64-bit DT updates for v4.6
The arm64 device tree changes make up an increasing portion of
 the overall changes, so they are kept separate from the 32-bit
 devicetree changes and from the other arm64 updates.
 
 Newly added SoCs and boards are:
  - 96Boards Husky board
  - AMD Overdrive board
  - Amlogic S905 SoC and related Tronsmart boxes
  - Annapurna Labs Alpine family and development board
  - Broadcom Vulcan servers
  - Broadcom Northstar 2 SoC
  - Marvell Armada 3700 family and development board
  - Qualcomm MSM8996 SoC
 
 Additional devices are enabled for existing platforms from
 Applied Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and
 there are a couple of other updates for Rockchip, Xilinx and
 NXP/Freescale.
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Merge tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM 64-bit DT updates from Arnd Bergmann:
 "The arm64 device tree changes make up an increasing portion of the
  overall changes, so they are kept separate from the 32-bit devicetree
  changes and from the other arm64 updates.

  Newly added SoCs and boards are:
   - 96Boards Husky board
   - AMD Overdrive board
   - Amlogic S905 SoC and related Tronsmart boxes
   - Annapurna Labs Alpine family and development board
   - Broadcom Vulcan servers
   - Broadcom Northstar 2 SoC
   - Marvell Armada 3700 family and development board
   - Qualcomm MSM8996 SoC

  Additional devices are enabled for existing platforms from Applied
  Micro, Hisilicon, Mediatek, Qualcomm, and Renesas and there are a
  couple of other updates for Rockchip, Xilinx and NXP/Freescale"

* tag 'armsoc-dt64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (102 commits)
  ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
  Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards
  ARM64: dts: Prepare configs for Amlogic Meson GXBaby
  Documentation: devicetree: amlogic: Document Meson GXBaby
  devicetree: bindings: Add vendor prefix for Tronsmart
  arm64: dts: qcom: Fix MPP's function used for LED control
  arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
  arm64: dts: add the Alpine v2 EVP
  arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
  arm64: dts: marvell: update Armada AP806 clock description
  arm64: dts: marvell: add Device Tree files for Armada 7K/8K
  arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
  arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
  arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
  arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
  arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
  ...
2016-03-20 15:26:57 -07:00
Linus Torvalds 5a6b7e53d0 ARM: DT updates for v4.6
These are all the updates to device tree files for 32-bit platforms,
 plus a couple of related 64-bit updates:
 
 New SoC support:
  - Allwinner A83T
  - Axis Artpec-6 SoC
  - Mediatek MT7623 SoC
  - TI Keystone K2G SoC
  - ST Microelectronics stm32f469
 
 New board or machine support:
  - ARM Juno R2
  - Buffalo Linkstation LS-QVL and LS-GL
  - Cubietruck plus
  - D-Link DIR-885L
  - DT support for ARM RealView PB1176 and PB11MPCore
  - Google Nexus 7
  - Homlet v2
  - Itead Ibox
  - Lamobo R1
  - LG Optimus Black
  - Logicpd dm3730
  - Raspberry Pi Model A
 
 Other changes include
  - Lots of updates for Qualcomm APQ8064, MSM8974 and others
  - Improved support for Nokia N900 and other OMAP machines
  - Common clk support for lpc32xx
  - HDLCD display on ARM
  - Improved stm32f429 support
  - Improved Renesas device support, r8a779x and others
  - Lots of Rockchip updates
  - Samsung cleanups
  - ADC support for Atmel SAMA5D2
  - BCM2835 (Raspberry Pi) improvements
  - Broadcom Northstar Plus enhancements
  - OMAP GPMC rework
  - Several improvements for Atmel SAMA5D2 / Xplained
  - Global change to remove inofficial "arm,amba-bus" compatible string
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Merge tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM DT updates from Arnd Bergmann:
 "These are all the updates to device tree files for 32-bit platforms,
  plus a couple of related 64-bit updates:

  New SoC support:
   - Allwinner A83T
   - Axis Artpec-6 SoC
   - Mediatek MT7623 SoC
   - TI Keystone K2G SoC
   - ST Microelectronics stm32f469

  New board or machine support:
   - ARM Juno R2
   - Buffalo Linkstation LS-QVL and LS-GL
   - Cubietruck plus
   - D-Link DIR-885L
   - DT support for ARM RealView PB1176 and PB11MPCore
   - Google Nexus 7
   - Homlet v2
   - Itead Ibox
   - Lamobo R1
   - LG Optimus Black
   - Logicpd dm3730
   - Raspberry Pi Model A

  Other changes include
   - Lots of updates for Qualcomm APQ8064, MSM8974 and others
   - Improved support for Nokia N900 and other OMAP machines
   - Common clk support for lpc32xx
   - HDLCD display on ARM
   - Improved stm32f429 support
   - Improved Renesas device support, r8a779x and others
   - Lots of Rockchip updates
   - Samsung cleanups
   - ADC support for Atmel SAMA5D2
   - BCM2835 (Raspberry Pi) improvements
   - Broadcom Northstar Plus enhancements
   - OMAP GPMC rework
   - Several improvements for Atmel SAMA5D2 / Xplained
   - Global change to remove inofficial "arm,amba-bus" compatible
     string"

* tag 'armsoc-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (350 commits)
  ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
  ARM: dts: artpec: dual-license on artpec6.dtsi
  ARM: dts: ux500: add synaptics RMI4 for Ux500 TVK DT
  arm64: dts: juno/vexpress: fix node name unit-address presence warnings
  arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
  ARM: dts: at91: sama5d2 Xplained: add leds node
  ARM: dts: at91: sama5d2 Xplained: add user push button
  ARM: dts: at91: sama5d2 Xplained: set pin muxing for usb gadget and usb host
  ARM: dts: stm32f429: Enable Ethernet on Eval board
  ARM: dts: omap3-sniper: TWL4030 keypad support
  Revert "ARM: dts: DRA7: Add dt nodes for PWMSS"
  ARM: dts: dm814x: dra62x: Disable wait pin monitoring for NAND
  ARM: dts: dm814x: dra62x: Fix NAND device nodes
  ARM: dts: stm32f429: Add Ethernet support
  ARM: dts: stm32f429: Add system config bank node
  ARM: dts: at91: sama5d2: add nand0 and nfc0 nodes
  ARM: dts: at91: sama5d2: add dma properties to UART nodes
  ARM: dts: at91: sama5d2 Xplained: Correct the macb irq pinctrl node
  ARM: dts: exynos: Don't overheat the Odroid XU3-Lite on high load
  ARM: dts: exynos: Add cooling levels for Exynos5422/5800 CPUs
  ...
2016-03-20 15:15:48 -07:00
Linus Torvalds 8c6d4082fc ARM: SoC 64-bit changes for v4.6
Here's our branch of ARM64 contents for this merge window, now
 containing all ARM64 changes other than device tree files.
 
 - Various new platforms get added
   - Allwinner A64 SoC
   - Annapurna Labs Alpine SoCs
   - Broadcom Vulcan
   - Marvell Armada 3700 SoCs
   - Amlogic S905
 
 - Various defconfig changes to enable platform specific drivers
 
 This branch includes the clk git tree to resolve a build-time
 dependency.
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Merge tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc

Pull ARM SoC 64-bit changes from Arnd Bergmann:
 "Here's our branch of ARM64 contents for this merge window, now
  containing all ARM64 changes other than device tree files.

   - Various new platforms get added:
      * Allwinner A64 SoC
      * Annapurna Labs Alpine SoCs
      * Broadcom Vulcan
      * Marvell Armada 3700 SoCs
      * Amlogic S905

   - Various defconfig changes to enable platform specific drivers

  This branch includes the clk git tree to resolve a build-time
  dependency"

* tag 'armsoc-arm64' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (48 commits)
  arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
  arm64: defconfig: Add Qualcomm sdhci and restart functionality
  ARM64: Enable Amlogic Meson GXBaby platform
  arm64: defconfig: Enable Samsung MFD and related configs
  arm64: alpine: select the Alpine MSI controller driver
  arm64: defconfig: enable the Alpine family
  arm64: add Alpine SoC family
  arm64: defconfig: Enable exynos thermal config
  arm64: add defconfig options for Allwinner SoCs
  arm64: defconfig: Enable DesignWare APB GPIO controller
  arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
  arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
  clk: samsung: Don't build ARMv8 clock drivers on ARMv7
  MAINTAINERS: Add entry for Broadcom Vulcan SoC
  arm64: cputype info for Broadcom Vulcan
  arm64: Broadcom Vulcan support
  arm64: defconfig: Add Broadcom Vulcan to defconfig
  arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
  Documentation: arm: add Marvell Armada 7K and 8K families
  Documentation: arm: add link to Armada 38x Functional Spec
  ...
2016-03-20 15:08:45 -07:00
Linus Torvalds de06dbfa78 Merge branch 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm
Pull ARM updates from Russell King:
 "Another mixture of changes this time around:

   - Split XIP linker file from main linker file to make it more
     maintainable, and various XIP fixes, and clean up a resulting
     macro.

   - Decompressor cleanups from Masahiro Yamada

   - Avoid printing an error for a missing L2 cache

   - Remove some duplicated symbols in System.map, and move
     vectors/stubs back into kernel VMA

   - Various low priority fixes from Arnd

   - Updates to allow bus match functions to return negative errno
     values, touching some drivers and the driver core.  Greg has acked
     these changes.

   - Virtualisation platform udpates form Jean-Philippe Brucker.

   - Security enhancements from Kees Cook

   - Rework some Kconfig dependencies and move PSCI idle management code
     out of arch/arm into drivers/firmware/psci.c

   - ARM DMA mapping updates, touching media, acked by Mauro.

   - Fix places in ARM code which should be using virt_to_idmap() so
     that Keystone2 can work.

   - Fix Marvell Tauros2 to work again with non-DT boots.

   - Provide a delay timer for ARM Orion platforms"

* 'for-linus' of git://ftp.arm.linux.org.uk/~rmk/linux-arm: (45 commits)
  ARM: 8546/1: dma-mapping: refactor to fix coherent+cma+gfp=0
  ARM: 8547/1: dma-mapping: store buffer information
  ARM: 8543/1: decompressor: rename suffix_y to compress-y
  ARM: 8542/1: decompressor: merge piggy.*.S and simplify Makefile
  ARM: 8541/1: decompressor: drop redundant FORCE in Makefile
  ARM: 8540/1: decompressor: use clean-files instead of extra-y to clean files
  ARM: 8539/1: decompressor: drop more unneeded assignments to "targets"
  ARM: 8538/1: decompressor: drop unneeded assignments to "targets"
  ARM: 8532/1: uncompress: mark putc as inline
  ARM: 8531/1: turn init_new_context into an inline function
  ARM: 8530/1: remove VIRT_TO_BUS
  ARM: 8537/1: drop unused DEBUG_RODATA from XIP_KERNEL
  ARM: 8536/1: mm: hide __start_rodata_section_aligned for non-debug builds
  ARM: 8535/1: mm: DEBUG_RODATA makes no sense with XIP_KERNEL
  ARM: 8534/1: virt: fix hyp-stub build for pre-ARMv7 CPUs
  ARM: make the physical-relative calculation more obvious
  ARM: 8512/1: proc-v7.S: Adjust stack address when XIP_KERNEL
  ARM: 8411/1: Add default SPARSEMEM settings
  ARM: 8503/1: clk_register_clkdev: remove format string interface
  ARM: 8529/1: remove 'i' and 'zi' targets
  ...
2016-03-19 16:31:54 -07:00
Linus Torvalds 1200b6809d Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next
Pull networking updates from David Miller:
 "Highlights:

   1) Support more Realtek wireless chips, from Jes Sorenson.

   2) New BPF types for per-cpu hash and arrap maps, from Alexei
      Starovoitov.

   3) Make several TCP sysctls per-namespace, from Nikolay Borisov.

   4) Allow the use of SO_REUSEPORT in order to do per-thread processing
   of incoming TCP/UDP connections.  The muxing can be done using a
   BPF program which hashes the incoming packet.  From Craig Gallek.

   5) Add a multiplexer for TCP streams, to provide a messaged based
      interface.  BPF programs can be used to determine the message
      boundaries.  From Tom Herbert.

   6) Add 802.1AE MACSEC support, from Sabrina Dubroca.

   7) Avoid factorial complexity when taking down an inetdev interface
      with lots of configured addresses.  We were doing things like
      traversing the entire address less for each address removed, and
      flushing the entire netfilter conntrack table for every address as
      well.

   8) Add and use SKB bulk free infrastructure, from Jesper Brouer.

   9) Allow offloading u32 classifiers to hardware, and implement for
      ixgbe, from John Fastabend.

  10) Allow configuring IRQ coalescing parameters on a per-queue basis,
      from Kan Liang.

  11) Extend ethtool so that larger link mode masks can be supported.
      From David Decotigny.

  12) Introduce devlink, which can be used to configure port link types
      (ethernet vs Infiniband, etc.), port splitting, and switch device
      level attributes as a whole.  From Jiri Pirko.

  13) Hardware offload support for flower classifiers, from Amir Vadai.

  14) Add "Local Checksum Offload".  Basically, for a tunneled packet
      the checksum of the outer header is 'constant' (because with the
      checksum field filled into the inner protocol header, the payload
      of the outer frame checksums to 'zero'), and we can take advantage
      of that in various ways.  From Edward Cree"

* git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-next: (1548 commits)
  bonding: fix bond_get_stats()
  net: bcmgenet: fix dma api length mismatch
  net/mlx4_core: Fix backward compatibility on VFs
  phy: mdio-thunder: Fix some Kconfig typos
  lan78xx: add ndo_get_stats64
  lan78xx: handle statistics counter rollover
  RDS: TCP: Remove unused constant
  RDS: TCP: Add sysctl tunables for sndbuf/rcvbuf on rds-tcp socket
  net: smc911x: convert pxa dma to dmaengine
  team: remove duplicate set of flag IFF_MULTICAST
  bonding: remove duplicate set of flag IFF_MULTICAST
  net: fix a comment typo
  ethernet: micrel: fix some error codes
  ip_tunnels, bpf: define IP_TUNNEL_OPTS_MAX and use it
  bpf, dst: add and use dst_tclassid helper
  bpf: make skb->tc_classid also readable
  net: mvneta: bm: clarify dependencies
  cls_bpf: reset class and reuse major in da
  ldmvsw: Checkpatch sunvnet.c and sunvnet_common.c
  ldmvsw: Add ldmvsw.c driver code
  ...
2016-03-19 10:05:34 -07:00
Linus Torvalds 814a2bf957 Merge branch 'akpm' (patches from Andrew)
Merge second patch-bomb from Andrew Morton:

 - a couple of hotfixes

 - the rest of MM

 - a new timer slack control in procfs

 - a couple of procfs fixes

 - a few misc things

 - some printk tweaks

 - lib/ updates, notably to radix-tree.

 - add my and Nick Piggin's old userspace radix-tree test harness to
   tools/testing/radix-tree/.  Matthew said it was a godsend during the
   radix-tree work he did.

 - a few code-size improvements, switching to __always_inline where gcc
   screwed up.

 - partially implement character sets in sscanf

* emailed patches from Andrew Morton <akpm@linux-foundation.org>: (118 commits)
  sscanf: implement basic character sets
  lib/bug.c: use common WARN helper
  param: convert some "on"/"off" users to strtobool
  lib: add "on"/"off" support to kstrtobool
  lib: update single-char callers of strtobool()
  lib: move strtobool() to kstrtobool()
  include/linux/unaligned: force inlining of byteswap operations
  include/uapi/linux/byteorder, swab: force inlining of some byteswap operations
  include/asm-generic/atomic-long.h: force inlining of some atomic_long operations
  usb: common: convert to use match_string() helper
  ide: hpt366: convert to use match_string() helper
  ata: hpt366: convert to use match_string() helper
  power: ab8500: convert to use match_string() helper
  power: charger_manager: convert to use match_string() helper
  drm/edid: convert to use match_string() helper
  pinctrl: convert to use match_string() helper
  device property: convert to use match_string() helper
  lib/string: introduce match_string() helper
  radix-tree tests: add test for radix_tree_iter_next
  radix-tree tests: add regression3 test
  ...
2016-03-18 19:26:54 -07:00
Masahiro Yamada 14bae133b8 ARM: dts: uniphier: rework UniPhier System Bus nodes
During the review process of the UniPhier System Bus driver
(drivers/bus/uniphier.c), the current binding of the System Bus
Controller turned out to be no good.  In order to make the driver
really usable, we have to switch over to the new binding defined by
Documentation/devicetree/bindings/bus/uniphier-system-bus.txt.
The old binding will be still supported for a while to keep the
backward compatibility.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:52 +01:00
Masahiro Yamada 5c5154e429 ARM: dts: uniphier: factor out ranges property of support card
This property is used in common by several boards.  Move it to the
common place (uniphier-support-card.dtsi).  If necessary, each board
can still override the property.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:45 +01:00
Masahiro Yamada 65e43389c3 arm64: dts: uniphier: rename PH1-LD10 to PH1-LD20
Due to the company's awful projecting, this chip has been renamed to
PH1-LD20.  It has not been shipped yet, this change would have no
impact on our customers.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-18 17:37:36 +01:00
Linus Torvalds 588ab3f9af arm64 updates for 4.6:
- Initial page table creation reworked to avoid breaking large block
   mappings (huge pages) into smaller ones. The ARM architecture requires
   break-before-make in such cases to avoid TLB conflicts but that's not
   always possible on live page tables
 
 - Kernel virtual memory layout: the kernel image is no longer linked to
   the bottom of the linear mapping (PAGE_OFFSET) but at the bottom of
   the vmalloc space, allowing the kernel to be loaded (nearly) anywhere
   in physical RAM
 
 - Kernel ASLR: position independent kernel Image and modules being
   randomly mapped in the vmalloc space with the randomness is provided
   by UEFI (efi_get_random_bytes() patches merged via the arm64 tree,
   acked by Matt Fleming)
 
 - Implement relative exception tables for arm64, required by KASLR
   (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c but
   actual x86 conversion to deferred to 4.7 because of the merge
   dependencies)
 
 - Support for the User Access Override feature of ARMv8.2: this allows
   uaccess functions (get_user etc.) to be implemented using LDTR/STTR
   instructions. Such instructions, when run by the kernel, perform
   unprivileged accesses adding an extra level of protection. The
   set_fs() macro is used to "upgrade" such instruction to privileged
   accesses via the UAO bit
 
 - Half-precision floating point support (part of ARMv8.2)
 
 - Optimisations for CPUs with or without a hardware prefetcher (using
   run-time code patching)
 
 - copy_page performance improvement to deal with 128 bytes at a time
 
 - Sanity checks on the CPU capabilities (via CPUID) to prevent
   incompatible secondary CPUs from being brought up (e.g. weird
   big.LITTLE configurations)
 
 - valid_user_regs() reworked for better sanity check of the sigcontext
   information (restored pstate information)
 
 - ACPI parking protocol implementation
 
 - CONFIG_DEBUG_RODATA enabled by default
 
 - VDSO code marked as read-only
 
 - DEBUG_PAGEALLOC support
 
 - ARCH_HAS_UBSAN_SANITIZE_ALL enabled
 
 - Erratum workaround Cavium ThunderX SoC
 
 - set_pte_at() fix for PROT_NONE mappings
 
 - Code clean-ups
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Merge tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 updates from Catalin Marinas:
 "Here are the main arm64 updates for 4.6.  There are some relatively
  intrusive changes to support KASLR, the reworking of the kernel
  virtual memory layout and initial page table creation.

  Summary:

   - Initial page table creation reworked to avoid breaking large block
     mappings (huge pages) into smaller ones.  The ARM architecture
     requires break-before-make in such cases to avoid TLB conflicts but
     that's not always possible on live page tables

   - Kernel virtual memory layout: the kernel image is no longer linked
     to the bottom of the linear mapping (PAGE_OFFSET) but at the bottom
     of the vmalloc space, allowing the kernel to be loaded (nearly)
     anywhere in physical RAM

   - Kernel ASLR: position independent kernel Image and modules being
     randomly mapped in the vmalloc space with the randomness is
     provided by UEFI (efi_get_random_bytes() patches merged via the
     arm64 tree, acked by Matt Fleming)

   - Implement relative exception tables for arm64, required by KASLR
     (initial code for ARCH_HAS_RELATIVE_EXTABLE added to lib/extable.c
     but actual x86 conversion to deferred to 4.7 because of the merge
     dependencies)

   - Support for the User Access Override feature of ARMv8.2: this
     allows uaccess functions (get_user etc.) to be implemented using
     LDTR/STTR instructions.  Such instructions, when run by the kernel,
     perform unprivileged accesses adding an extra level of protection.
     The set_fs() macro is used to "upgrade" such instruction to
     privileged accesses via the UAO bit

   - Half-precision floating point support (part of ARMv8.2)

   - Optimisations for CPUs with or without a hardware prefetcher (using
     run-time code patching)

   - copy_page performance improvement to deal with 128 bytes at a time

   - Sanity checks on the CPU capabilities (via CPUID) to prevent
     incompatible secondary CPUs from being brought up (e.g.  weird
     big.LITTLE configurations)

   - valid_user_regs() reworked for better sanity check of the
     sigcontext information (restored pstate information)

   - ACPI parking protocol implementation

   - CONFIG_DEBUG_RODATA enabled by default

   - VDSO code marked as read-only

   - DEBUG_PAGEALLOC support

   - ARCH_HAS_UBSAN_SANITIZE_ALL enabled

   - Erratum workaround Cavium ThunderX SoC

   - set_pte_at() fix for PROT_NONE mappings

   - Code clean-ups"

* tag 'arm64-upstream' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux: (99 commits)
  arm64: kasan: Fix zero shadow mapping overriding kernel image shadow
  arm64: kasan: Use actual memory node when populating the kernel image shadow
  arm64: Update PTE_RDONLY in set_pte_at() for PROT_NONE permission
  arm64: Fix misspellings in comments.
  arm64: efi: add missing frame pointer assignment
  arm64: make mrs_s prefixing implicit in read_cpuid
  arm64: enable CONFIG_DEBUG_RODATA by default
  arm64: Rework valid_user_regs
  arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly
  arm64: KVM: Move kvm_call_hyp back to its original localtion
  arm64: mm: treat memstart_addr as a signed quantity
  arm64: mm: list kernel sections in order
  arm64: lse: deal with clobbered IP registers after branch via PLT
  arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR
  arm64: kconfig: add submenu for 8.2 architectural features
  arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postboot
  arm64: Add support for Half precision floating point
  arm64: Remove fixmap include fragility
  arm64: Add workaround for Cavium erratum 27456
  arm64: mm: Mark .rodata as RO
  ...
2016-03-17 20:03:47 -07:00
Jan Kara 0e8fb9312f mm: remove VM_FAULT_MINOR
The define has a comment from Nick Piggin from 2007:

 /* For backwards compat. Remove me quickly. */

I guess 9 years should not be too hurried sense of 'quickly' even for
kernel measures.

Signed-off-by: Jan Kara <jack@suse.cz>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-03-17 15:09:34 -07:00
Kirill A. Shutemov 3ed3a4f0dd mm: cleanup *pte_alloc* interfaces
There are few things about *pte_alloc*() helpers worth cleaning up:

 - 'vma' argument is unused, let's drop it;

 - most __pte_alloc() callers do speculative check for pmd_none(),
   before taking ptl: let's introduce pte_alloc() macro which does
   the check.

   The only direct user of __pte_alloc left is userfaultfd, which has
   different expectation about atomicity wrt pmd.

 - pte_alloc_map() and pte_alloc_map_lock() are redefined using
   pte_alloc().

[sudeep.holla@arm.com: fix build for arm64 hugetlbpage]
[sfr@canb.auug.org.au: fix arch/arm/mm/mmu.c some more]
Signed-off-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Cc: Dave Hansen <dave.hansen@intel.com>
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Acked-by: Kirill A. Shutemov <kirill.shutemov@linux.intel.com>
Signed-off-by: Stephen Rothwell <sfr@canb.auug.org.au>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-03-17 15:09:34 -07:00
Linus Torvalds 70477371dc Merge branch 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6
Pull crypto update from Herbert Xu:
 "Here is the crypto update for 4.6:

  API:
   - Convert remaining crypto_hash users to shash or ahash, also convert
     blkcipher/ablkcipher users to skcipher.
   - Remove crypto_hash interface.
   - Remove crypto_pcomp interface.
   - Add crypto engine for async cipher drivers.
   - Add akcipher documentation.
   - Add skcipher documentation.

  Algorithms:
   - Rename crypto/crc32 to avoid name clash with lib/crc32.
   - Fix bug in keywrap where we zero the wrong pointer.

  Drivers:
   - Support T5/M5, T7/M7 SPARC CPUs in n2 hwrng driver.
   - Add PIC32 hwrng driver.
   - Support BCM6368 in bcm63xx hwrng driver.
   - Pack structs for 32-bit compat users in qat.
   - Use crypto engine in omap-aes.
   - Add support for sama5d2x SoCs in atmel-sha.
   - Make atmel-sha available again.
   - Make sahara hashing available again.
   - Make ccp hashing available again.
   - Make sha1-mb available again.
   - Add support for multiple devices in ccp.
   - Improve DMA performance in caam.
   - Add hashing support to rockchip"

* 'linus' of git://git.kernel.org/pub/scm/linux/kernel/git/herbert/crypto-2.6: (116 commits)
  crypto: qat - remove redundant arbiter configuration
  crypto: ux500 - fix checks of error code returned by devm_ioremap_resource()
  crypto: atmel - fix checks of error code returned by devm_ioremap_resource()
  crypto: qat - Change the definition of icp_qat_uof_regtype
  hwrng: exynos - use __maybe_unused to hide pm functions
  crypto: ccp - Add abstraction for device-specific calls
  crypto: ccp - CCP versioning support
  crypto: ccp - Support for multiple CCPs
  crypto: ccp - Remove check for x86 family and model
  crypto: ccp - memset request context to zero during import
  lib/mpi: use "static inline" instead of "extern inline"
  lib/mpi: avoid assembler warning
  hwrng: bcm63xx - fix non device tree compatibility
  crypto: testmgr - allow rfc3686 aes-ctr variants in fips mode.
  crypto: qat - The AE id should be less than the maximal AE number
  lib/mpi: Endianness fix
  crypto: rockchip - add hash support for crypto engine in rk3288
  crypto: xts - fix compile errors
  crypto: doc - add skcipher API documentation
  crypto: doc - update AEAD AD handling
  ...
2016-03-17 11:22:54 -07:00
Linus Torvalds 63e30271b0 PCI changes for the v4.6 merge window:
Enumeration
     Disable IO/MEM decoding for devices with non-compliant BARs (Bjorn Helgaas)
     Mark Broadwell-EP Home Agent & PCU as having non-compliant BARs (Bjorn Helgaas
 
   Resource management
     Mark shadow copy of VGA ROM as IORESOURCE_PCI_FIXED (Bjorn Helgaas)
     Don't assign or reassign immutable resources (Bjorn Helgaas)
     Don't enable/disable ROM BAR if we're using a RAM shadow copy (Bjorn Helgaas)
     Set ROM shadow location in arch code, not in PCI core (Bjorn Helgaas)
     Remove arch-specific IORESOURCE_ROM_SHADOW size from sysfs (Bjorn Helgaas)
     ia64: Use ioremap() instead of open-coded equivalent (Bjorn Helgaas)
     ia64: Keep CPU physical (not virtual) addresses in shadow ROM resource (Bjorn Helgaas)
     MIPS: Keep CPU physical (not virtual) addresses in shadow ROM resource (Bjorn Helgaas)
     Remove unused IORESOURCE_ROM_COPY and IORESOURCE_ROM_BIOS_COPY (Bjorn Helgaas)
     Don't leak memory if sysfs_create_bin_file() fails (Bjorn Helgaas)
     rcar: Remove PCI_PROBE_ONLY handling (Lorenzo Pieralisi)
     designware: Remove PCI_PROBE_ONLY handling (Lorenzo Pieralisi)
 
   Virtualization
     Wait for up to 1000ms after FLR reset (Alex Williamson)
     Support SR-IOV on any function type (Kelly Zytaruk)
     Add ACS quirk for all Cavium devices (Manish Jaggi)
 
   AER
     Rename pci_ops_aer to aer_inj_pci_ops (Bjorn Helgaas)
     Restore pci_ops pointer while calling original pci_ops (David Daney)
     Fix aer_inject error codes (Jean Delvare)
     Use dev_warn() in aer_inject (Jean Delvare)
     Log actual error causes in aer_inject (Jean Delvare)
     Log aer_inject error injections (Jean Delvare)
 
   VPD
     Prevent VPD access for buggy devices (Babu Moger)
     Move pci_read_vpd() and pci_write_vpd() close to other VPD code (Bjorn Helgaas)
     Move pci_vpd_release() from header file to pci/access.c (Bjorn Helgaas)
     Remove struct pci_vpd_ops.release function pointer (Bjorn Helgaas)
     Rename VPD symbols to remove unnecessary "pci22" (Bjorn Helgaas)
     Fold struct pci_vpd_pci22 into struct pci_vpd (Bjorn Helgaas)
     Sleep rather than busy-wait for VPD access completion (Bjorn Helgaas)
     Update VPD definitions (Hannes Reinecke)
     Allow access to VPD attributes with size 0 (Hannes Reinecke)
     Determine actual VPD size on first access (Hannes Reinecke)
 
   Generic host bridge driver
     Move structure definitions to separate header file (David Daney)
     Add pci_host_common_probe(), based on gen_pci_probe() (David Daney)
     Expose pci_host_common_probe() for use by other drivers (David Daney)
 
   Altera host bridge driver
     Fix altera_pcie_link_is_up() (Ley Foon Tan)
 
   Cavium ThunderX host bridge driver
     Add PCIe host driver for ThunderX processors (David Daney)
     Add driver for ThunderX-pass{1,2} on-chip devices (David Daney)
 
   Freescale i.MX6 host bridge driver
     Add DT bindings to configure PHY Tx driver settings (Justin Waters)
     Move imx6_pcie_reset_phy() near other PHY handling functions (Lucas Stach)
     Move PHY reset into imx6_pcie_establish_link() (Lucas Stach)
     Remove broken Gen2 workaround (Lucas Stach)
     Move link up check into imx6_pcie_wait_for_link() (Lucas Stach)
 
   Freescale Layerscape host bridge driver
     Add "fsl,ls2085a-pcie" compatible ID (Yang Shi)
 
   Intel VMD host bridge driver
     Attach VMD resources to parent domain's resource tree (Jon Derrick)
     Set bus resource start to 0 (Keith Busch)
 
   Microsoft Hyper-V host bridge driver
     Add fwnode_handle to x86 pci_sysdata (Jake Oshins)
     Look up IRQ domain by fwnode_handle (Jake Oshins)
     Add paravirtual PCI front-end for Microsoft Hyper-V VMs (Jake Oshins)
 
   NVIDIA Tegra host bridge driver
     Add pci_ops.{add,remove}_bus() callbacks (Thierry Reding)
     Implement ->{add,remove}_bus() callbacks (Thierry Reding)
     Remove unused struct tegra_pcie.num_ports field (Thierry Reding)
     Track bus -> CPU mapping (Thierry Reding)
     Remove misleading PHYS_OFFSET (Thierry Reding)
 
   Renesas R-Car host bridge driver
     Depend on ARCH_RENESAS, not ARCH_SHMOBILE (Simon Horman)
 
   Synopsys DesignWare host bridge driver
     ARC: Add PCI support (Joao Pinto)
     Add generic dw_pcie_wait_for_link() (Joao Pinto)
     Add default link up check if sub-driver doesn't override (Joao Pinto)
     Add driver for prototyping kits based on ARC SDP (Joao Pinto)
 
   TI Keystone host bridge driver
     Defer probing if devm_phy_get() returns -EPROBE_DEFER (Shawn Lin)
 
   Xilinx AXI host bridge driver
     Use of_pci_get_host_bridge_resources() to parse DT (Bharat Kumar Gogada)
     Remove dependency on ARM-specific struct hw_pci (Bharat Kumar Gogada)
     Don't call pci_fixup_irqs() on Microblaze (Bharat Kumar Gogada)
     Update Zynq binding with Microblaze node (Bharat Kumar Gogada)
     microblaze: Support generic Xilinx AXI PCIe Host Bridge IP driver (Bharat Kumar Gogada)
 
   Xilinx NWL host bridge driver
     Add support for Xilinx NWL PCIe Host Controller (Bharat Kumar Gogada)
 
   Miscellaneous
     Check device_attach() return value always (Bjorn Helgaas)
     Move pci_set_flags() from asm-generic/pci-bridge.h to linux/pci.h (Bjorn Helgaas)
     Remove includes of empty asm-generic/pci-bridge.h (Bjorn Helgaas)
     ARM64: Remove generated include of asm-generic/pci-bridge.h (Bjorn Helgaas)
     Remove empty asm-generic/pci-bridge.h (Bjorn Helgaas)
     Remove includes of asm/pci-bridge.h (Bjorn Helgaas)
     Consolidate PCI DMA constants and interfaces in linux/pci-dma-compat.h (Bjorn Helgaas)
     unicore32: Remove unused HAVE_ARCH_PCI_SET_DMA_MASK definition (Bjorn Helgaas)
     Cleanup pci/pcie/Kconfig whitespace (Andreas Ziegler)
     Include pci/hotplug Kconfig directly from pci/Kconfig (Bjorn Helgaas)
     Include pci/pcie/Kconfig directly from pci/Kconfig (Bogicevic Sasa)
     frv: Remove stray pci_{alloc,free}_consistent() declaration (Christoph Hellwig)
     Move pci_dma_* helpers to common code (Christoph Hellwig)
     Add PCI_CLASS_SERIAL_USB_DEVICE definition (Heikki Krogerus)
     Add QEMU top-level IDs for (sub)vendor & device (Robin H. Johnson)
     Fix broken URL for Dell biosdevname (Naga Venkata Sai Indubhaskar Jupudi)
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Merge tag 'pci-v4.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci

Pull PCI updates from Bjorn Helgaas:
 "PCI changes for v4.6:

  Enumeration:
   - Disable IO/MEM decoding for devices with non-compliant BARs (Bjorn Helgaas)
   - Mark Broadwell-EP Home Agent & PCU as having non-compliant BARs (Bjorn Helgaas

  Resource management:
   - Mark shadow copy of VGA ROM as IORESOURCE_PCI_FIXED (Bjorn Helgaas)
   - Don't assign or reassign immutable resources (Bjorn Helgaas)
   - Don't enable/disable ROM BAR if we're using a RAM shadow copy (Bjorn Helgaas)
   - Set ROM shadow location in arch code, not in PCI core (Bjorn Helgaas)
   - Remove arch-specific IORESOURCE_ROM_SHADOW size from sysfs (Bjorn Helgaas)
   - ia64: Use ioremap() instead of open-coded equivalent (Bjorn Helgaas)
   - ia64: Keep CPU physical (not virtual) addresses in shadow ROM resource (Bjorn Helgaas)
   - MIPS: Keep CPU physical (not virtual) addresses in shadow ROM resource (Bjorn Helgaas)
   - Remove unused IORESOURCE_ROM_COPY and IORESOURCE_ROM_BIOS_COPY (Bjorn Helgaas)
   - Don't leak memory if sysfs_create_bin_file() fails (Bjorn Helgaas)
   - rcar: Remove PCI_PROBE_ONLY handling (Lorenzo Pieralisi)
   - designware: Remove PCI_PROBE_ONLY handling (Lorenzo Pieralisi)

  Virtualization:
   - Wait for up to 1000ms after FLR reset (Alex Williamson)
   - Support SR-IOV on any function type (Kelly Zytaruk)
   - Add ACS quirk for all Cavium devices (Manish Jaggi)

  AER:
   - Rename pci_ops_aer to aer_inj_pci_ops (Bjorn Helgaas)
   - Restore pci_ops pointer while calling original pci_ops (David Daney)
   - Fix aer_inject error codes (Jean Delvare)
   - Use dev_warn() in aer_inject (Jean Delvare)
   - Log actual error causes in aer_inject (Jean Delvare)
   - Log aer_inject error injections (Jean Delvare)

  VPD:
   - Prevent VPD access for buggy devices (Babu Moger)
   - Move pci_read_vpd() and pci_write_vpd() close to other VPD code (Bjorn Helgaas)
   - Move pci_vpd_release() from header file to pci/access.c (Bjorn Helgaas)
   - Remove struct pci_vpd_ops.release function pointer (Bjorn Helgaas)
   - Rename VPD symbols to remove unnecessary "pci22" (Bjorn Helgaas)
   - Fold struct pci_vpd_pci22 into struct pci_vpd (Bjorn Helgaas)
   - Sleep rather than busy-wait for VPD access completion (Bjorn Helgaas)
   - Update VPD definitions (Hannes Reinecke)
   - Allow access to VPD attributes with size 0 (Hannes Reinecke)
   - Determine actual VPD size on first access (Hannes Reinecke)

  Generic host bridge driver:
   - Move structure definitions to separate header file (David Daney)
   - Add pci_host_common_probe(), based on gen_pci_probe() (David Daney)
   - Expose pci_host_common_probe() for use by other drivers (David Daney)

  Altera host bridge driver:
   - Fix altera_pcie_link_is_up() (Ley Foon Tan)

  Cavium ThunderX host bridge driver:
   - Add PCIe host driver for ThunderX processors (David Daney)
   - Add driver for ThunderX-pass{1,2} on-chip devices (David Daney)

  Freescale i.MX6 host bridge driver:
   - Add DT bindings to configure PHY Tx driver settings (Justin Waters)
   - Move imx6_pcie_reset_phy() near other PHY handling functions (Lucas Stach)
   - Move PHY reset into imx6_pcie_establish_link() (Lucas Stach)
   - Remove broken Gen2 workaround (Lucas Stach)
   - Move link up check into imx6_pcie_wait_for_link() (Lucas Stach)

  Freescale Layerscape host bridge driver:
   - Add "fsl,ls2085a-pcie" compatible ID (Yang Shi)

  Intel VMD host bridge driver:
   - Attach VMD resources to parent domain's resource tree (Jon Derrick)
   - Set bus resource start to 0 (Keith Busch)

  Microsoft Hyper-V host bridge driver:
   - Add fwnode_handle to x86 pci_sysdata (Jake Oshins)
   - Look up IRQ domain by fwnode_handle (Jake Oshins)
   - Add paravirtual PCI front-end for Microsoft Hyper-V VMs (Jake Oshins)

  NVIDIA Tegra host bridge driver:
   - Add pci_ops.{add,remove}_bus() callbacks (Thierry Reding)
   - Implement ->{add,remove}_bus() callbacks (Thierry Reding)
   - Remove unused struct tegra_pcie.num_ports field (Thierry Reding)
   - Track bus -> CPU mapping (Thierry Reding)
   - Remove misleading PHYS_OFFSET (Thierry Reding)

  Renesas R-Car host bridge driver:
   - Depend on ARCH_RENESAS, not ARCH_SHMOBILE (Simon Horman)

  Synopsys DesignWare host bridge driver:
   - ARC: Add PCI support (Joao Pinto)
   - Add generic dw_pcie_wait_for_link() (Joao Pinto)
   - Add default link up check if sub-driver doesn't override (Joao Pinto)
   - Add driver for prototyping kits based on ARC SDP (Joao Pinto)

  TI Keystone host bridge driver:
   - Defer probing if devm_phy_get() returns -EPROBE_DEFER (Shawn Lin)

  Xilinx AXI host bridge driver:
   - Use of_pci_get_host_bridge_resources() to parse DT (Bharat Kumar Gogada)
   - Remove dependency on ARM-specific struct hw_pci (Bharat Kumar Gogada)
   - Don't call pci_fixup_irqs() on Microblaze (Bharat Kumar Gogada)
   - Update Zynq binding with Microblaze node (Bharat Kumar Gogada)
   - microblaze: Support generic Xilinx AXI PCIe Host Bridge IP driver (Bharat Kumar Gogada)

  Xilinx NWL host bridge driver:
   - Add support for Xilinx NWL PCIe Host Controller (Bharat Kumar Gogada)

  Miscellaneous:
   - Check device_attach() return value always (Bjorn Helgaas)
   - Move pci_set_flags() from asm-generic/pci-bridge.h to linux/pci.h (Bjorn Helgaas)
   - Remove includes of empty asm-generic/pci-bridge.h (Bjorn Helgaas)
   - ARM64: Remove generated include of asm-generic/pci-bridge.h (Bjorn Helgaas)
   - Remove empty asm-generic/pci-bridge.h (Bjorn Helgaas)
   - Remove includes of asm/pci-bridge.h (Bjorn Helgaas)
   - Consolidate PCI DMA constants and interfaces in linux/pci-dma-compat.h (Bjorn Helgaas)
   - unicore32: Remove unused HAVE_ARCH_PCI_SET_DMA_MASK definition (Bjorn Helgaas)
   - Cleanup pci/pcie/Kconfig whitespace (Andreas Ziegler)
   - Include pci/hotplug Kconfig directly from pci/Kconfig (Bjorn Helgaas)
   - Include pci/pcie/Kconfig directly from pci/Kconfig (Bogicevic Sasa)
   - frv: Remove stray pci_{alloc,free}_consistent() declaration (Christoph Hellwig)
   - Move pci_dma_* helpers to common code (Christoph Hellwig)
   - Add PCI_CLASS_SERIAL_USB_DEVICE definition (Heikki Krogerus)
   - Add QEMU top-level IDs for (sub)vendor & device (Robin H. Johnson)
   - Fix broken URL for Dell biosdevname (Naga Venkata Sai Indubhaskar Jupudi)"

* tag 'pci-v4.6-changes' of git://git.kernel.org/pub/scm/linux/kernel/git/helgaas/pci: (94 commits)
  PCI: Add PCI_CLASS_SERIAL_USB_DEVICE definition
  PCI: designware: Add driver for prototyping kits based on ARC SDP
  PCI: designware: Add default link up check if sub-driver doesn't override
  PCI: designware: Add generic dw_pcie_wait_for_link()
  PCI: Cleanup pci/pcie/Kconfig whitespace
  PCI: Simplify pci_create_attr() control flow
  PCI: Don't leak memory if sysfs_create_bin_file() fails
  PCI: Simplify sysfs ROM cleanup
  PCI: Remove unused IORESOURCE_ROM_COPY and IORESOURCE_ROM_BIOS_COPY
  MIPS: Loongson 3: Keep CPU physical (not virtual) addresses in shadow ROM resource
  MIPS: Loongson 3: Use temporary struct resource * to avoid repetition
  ia64/PCI: Keep CPU physical (not virtual) addresses in shadow ROM resource
  ia64/PCI: Use ioremap() instead of open-coded equivalent
  ia64/PCI: Use temporary struct resource * to avoid repetition
  PCI: Clean up pci_map_rom() whitespace
  PCI: Remove arch-specific IORESOURCE_ROM_SHADOW size from sysfs
  PCI: thunder: Add driver for ThunderX-pass{1,2} on-chip devices
  PCI: thunder: Add PCIe host driver for ThunderX processors
  PCI: generic: Expose pci_host_common_probe() for use by other drivers
  PCI: generic: Add pci_host_common_probe(), based on gen_pci_probe()
  ...
2016-03-16 14:45:55 -07:00
Linus Torvalds 10dc374766 One of the largest releases for KVM... Hardly any generic improvement,
but lots of architecture-specific changes.
 
 * ARM:
 - VHE support so that we can run the kernel at EL2 on ARMv8.1 systems
 - PMU support for guests
 - 32bit world switch rewritten in C
 - various optimizations to the vgic save/restore code.
 
 * PPC:
 - enabled KVM-VFIO integration ("VFIO device")
 - optimizations to speed up IPIs between vcpus
 - in-kernel handling of IOMMU hypercalls
 - support for dynamic DMA windows (DDW).
 
 * s390:
 - provide the floating point registers via sync regs;
 - separated instruction vs. data accesses
 - dirty log improvements for huge guests
 - bugfixes and documentation improvements.
 
 * x86:
 - Hyper-V VMBus hypercall userspace exit
 - alternative implementation of lowest-priority interrupts using vector
 hashing (for better VT-d posted interrupt support)
 - fixed guest debugging with nested virtualizations
 - improved interrupt tracking in the in-kernel IOAPIC
 - generic infrastructure for tracking writes to guest memory---currently
 its only use is to speedup the legacy shadow paging (pre-EPT) case, but
 in the future it will be used for virtual GPUs as well
 - much cleanup (LAPIC, kvmclock, MMU, PIT), including ubsan fixes.
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM updates from Paolo Bonzini:
 "One of the largest releases for KVM...  Hardly any generic
  changes, but lots of architecture-specific updates.

  ARM:
   - VHE support so that we can run the kernel at EL2 on ARMv8.1 systems
   - PMU support for guests
   - 32bit world switch rewritten in C
   - various optimizations to the vgic save/restore code.

  PPC:
   - enabled KVM-VFIO integration ("VFIO device")
   - optimizations to speed up IPIs between vcpus
   - in-kernel handling of IOMMU hypercalls
   - support for dynamic DMA windows (DDW).

  s390:
   - provide the floating point registers via sync regs;
   - separated instruction vs.  data accesses
   - dirty log improvements for huge guests
   - bugfixes and documentation improvements.

  x86:
   - Hyper-V VMBus hypercall userspace exit
   - alternative implementation of lowest-priority interrupts using
     vector hashing (for better VT-d posted interrupt support)
   - fixed guest debugging with nested virtualizations
   - improved interrupt tracking in the in-kernel IOAPIC
   - generic infrastructure for tracking writes to guest
     memory - currently its only use is to speedup the legacy shadow
     paging (pre-EPT) case, but in the future it will be used for
     virtual GPUs as well
   - much cleanup (LAPIC, kvmclock, MMU, PIT), including ubsan fixes"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm: (217 commits)
  KVM: x86: remove eager_fpu field of struct kvm_vcpu_arch
  KVM: x86: disable MPX if host did not enable MPX XSAVE features
  arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit
  arm64: KVM: vgic-v3: Reset LRs at boot time
  arm64: KVM: vgic-v3: Do not save an LR known to be empty
  arm64: KVM: vgic-v3: Save maintenance interrupt state only if required
  arm64: KVM: vgic-v3: Avoid accessing ICH registers
  KVM: arm/arm64: vgic-v2: Make GICD_SGIR quicker to hit
  KVM: arm/arm64: vgic-v2: Only wipe LRs on vcpu exit
  KVM: arm/arm64: vgic-v2: Reset LRs at boot time
  KVM: arm/arm64: vgic-v2: Do not save an LR known to be empty
  KVM: arm/arm64: vgic-v2: Move GICH_ELRSR saving to its own function
  KVM: arm/arm64: vgic-v2: Save maintenance interrupt state only if required
  KVM: arm/arm64: vgic-v2: Avoid accessing GICH registers
  KVM: s390: allocate only one DMA page per VM
  KVM: s390: enable STFLE interpretation only if enabled for the guest
  KVM: s390: wake up when the VCPU cpu timer expires
  KVM: s390: step the VCPU timer while in enabled wait
  KVM: s390: protect VCPU cpu timer with a seqcount
  KVM: s390: step VCPU cpu timer during kvm_run ioctl
  ...
2016-03-16 09:55:35 -07:00
Linus Torvalds 047486d8e7 EDAC queue for 4.6
* Altera: L2 cache and On-Chip RAM support (Thor Thayer).
 
 * EDAC: Workqueue handling cleanups (Borislav Petkov).
 
 * Xgene: Register bus error handling (Loc Ho).
 
 * Misc small fixes.
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Merge tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp

Pull EDAC updates from Borislav Petkov:

 - Altera: L2 cache and On-Chip RAM support (Thor Thayer).

 - EDAC: Workqueue handling cleanups (Borislav Petkov).

 - Xgene: Register bus error handling (Loc Ho).

 - Misc small fixes.

* tag 'edac_for_4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/bp/bp:
  ARM: socfpga: Enable OCRAM ECC on startup
  ARM: socfpga: Enable L2 cache ECC on startup
  ARM: dts: Add Altera L2 Cache and OCRAM EDAC entries
  EDAC, altera: Add Altera L2 cache and OCRAM support
  EDAC: Use edac_debugfs_remove_recursive() in edac_debugfs_exit()
  EDAC, mpc85xx: Silence unused variable warning
  EDAC: Cleanup/sync workqueue functions
  EDAC: Kill workqueue setup/teardown functions
  EDAC: Balance workqueue setup and teardown
  arm64: Update the APM X-Gene EDAC node with the RB register resource
  EDAC, xgene: Add missing SoC register bus error handling
  Documentation, EDAC: Update xgene binding for missing register bus
  EDAC, amd64_edac: Shift wrapping issue in f1x_get_norm_dct_addr()
2016-03-16 08:36:55 -07:00
Linus Torvalds 710d60cbf1 Merge branch 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull cpu hotplug updates from Thomas Gleixner:
 "This is the first part of the ongoing cpu hotplug rework:

   - Initial implementation of the state machine

   - Runs all online and prepare down callbacks on the plugged cpu and
     not on some random processor

   - Replaces busy loop waiting with completions

   - Adds tracepoints so the states can be followed"

More detailed commentary on this work from an earlier email:
 "What's wrong with the current cpu hotplug infrastructure?

   - Asymmetry

     The hotplug notifier mechanism is asymmetric versus the bringup and
     teardown.  This is mostly caused by the notifier mechanism.

   - Largely undocumented dependencies

     While some notifiers use explicitely defined notifier priorities,
     we have quite some notifiers which use numerical priorities to
     express dependencies without any documentation why.

   - Control processor driven

     Most of the bringup/teardown of a cpu is driven by a control
     processor.  While it is understandable, that preperatory steps,
     like idle thread creation, memory allocation for and initialization
     of essential facilities needs to be done before a cpu can boot,
     there is no reason why everything else must run on a control
     processor.  Before this patch series, bringup looks like this:

       Control CPU                     Booting CPU

       do preparatory steps
       kick cpu into life

                                       do low level init

       sync with booting cpu           sync with control cpu

       bring the rest up

   - All or nothing approach

     There is no way to do partial bringups.  That's something which is
     really desired because we waste e.g.  at boot substantial amount of
     time just busy waiting that the cpu comes to life.  That's stupid
     as we could very well do preparatory steps and the initial IPI for
     other cpus and then go back and do the necessary low level
     synchronization with the freshly booted cpu.

   - Minimal debuggability

     Due to the notifier based design, it's impossible to switch between
     two stages of the bringup/teardown back and forth in order to test
     the correctness.  So in many hotplug notifiers the cancel
     mechanisms are either not existant or completely untested.

   - Notifier [un]registering is tedious

     To [un]register notifiers we need to protect against hotplug at
     every callsite.  There is no mechanism that bringup/teardown
     callbacks are issued on the online cpus, so every caller needs to
     do it itself.  That also includes error rollback.

  What's the new design?

     The base of the new design is a symmetric state machine, where both
     the control processor and the booting/dying cpu execute a well
     defined set of states.  Each state is symmetric in the end, except
     for some well defined exceptions, and the bringup/teardown can be
     stopped and reversed at almost all states.

     So the bringup of a cpu will look like this in the future:

       Control CPU                     Booting CPU

       do preparatory steps
       kick cpu into life

                                       do low level init

       sync with booting cpu           sync with control cpu

                                       bring itself up

     The synchronization step does not require the control cpu to wait.
     That mechanism can be done asynchronously via a worker or some
     other mechanism.

     The teardown can be made very similar, so that the dying cpu cleans
     up and brings itself down.  Cleanups which need to be done after
     the cpu is gone, can be scheduled asynchronously as well.

  There is a long way to this, as we need to refactor the notion when a
  cpu is available.  Today we set the cpu online right after it comes
  out of the low level bringup, which is not really correct.

  The proper mechanism is to set it to available, i.e. cpu local
  threads, like softirqd, hotplug thread etc. can be scheduled on that
  cpu, and once it finished all booting steps, it's set to online, so
  general workloads can be scheduled on it.  The reverse happens on
  teardown.  First thing to do is to forbid scheduling of general
  workloads, then teardown all the per cpu resources and finally shut it
  off completely.

  This patch series implements the basic infrastructure for this at the
  core level.  This includes the following:

   - Basic state machine implementation with well defined states, so
     ordering and prioritization can be expressed.

   - Interfaces to [un]register state callbacks

     This invokes the bringup/teardown callback on all online cpus with
     the proper protection in place and [un]installs the callbacks in
     the state machine array.

     For callbacks which have no particular ordering requirement we have
     a dynamic state space, so that drivers don't have to register an
     explicit hotplug state.

     If a callback fails, the code automatically does a rollback to the
     previous state.

   - Sysfs interface to drive the state machine to a particular step.

     This is only partially functional today.  Full functionality and
     therefor testability will be achieved once we converted all
     existing hotplug notifiers over to the new scheme.

   - Run all CPU_ONLINE/DOWN_PREPARE notifiers on the booting/dying
     processor:

       Control CPU                     Booting CPU

       do preparatory steps
       kick cpu into life

                                       do low level init

       sync with booting cpu           sync with control cpu
       wait for boot
                                       bring itself up

                                       Signal completion to control cpu

     In a previous step of this work we've done a full tree mechanical
     conversion of all hotplug notifiers to the new scheme.  The balance
     is a net removal of about 4000 lines of code.

     This is not included in this series, as we decided to take a
     different approach.  Instead of mechanically converting everything
     over, we will do a proper overhaul of the usage sites one by one so
     they nicely fit into the symmetric callback scheme.

     I decided to do that after I looked at the ugliness of some of the
     converted sites and figured out that their hotplug mechanism is
     completely buggered anyway.  So there is no point to do a
     mechanical conversion first as we need to go through the usage
     sites one by one again in order to achieve a full symmetric and
     testable behaviour"

* 'smp-hotplug-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip: (23 commits)
  cpu/hotplug: Document states better
  cpu/hotplug: Fix smpboot thread ordering
  cpu/hotplug: Remove redundant state check
  cpu/hotplug: Plug death reporting race
  rcu: Make CPU_DYING_IDLE an explicit call
  cpu/hotplug: Make wait for dead cpu completion based
  cpu/hotplug: Let upcoming cpu bring itself fully up
  arch/hotplug: Call into idle with a proper state
  cpu/hotplug: Move online calls to hotplugged cpu
  cpu/hotplug: Create hotplug threads
  cpu/hotplug: Split out the state walk into functions
  cpu/hotplug: Unpark smpboot threads from the state machine
  cpu/hotplug: Move scheduler cpu_online notifier to hotplug core
  cpu/hotplug: Implement setup/removal interface
  cpu/hotplug: Make target state writeable
  cpu/hotplug: Add sysfs state interface
  cpu/hotplug: Hand in target state to _cpu_up/down
  cpu/hotplug: Convert the hotplugged cpu work to a state machine
  cpu/hotplug: Convert to a state machine for the control processor
  cpu/hotplug: Add tracepoints
  ...
2016-03-15 13:50:29 -07:00
Bjorn Helgaas 18e5e6913b Merge branches 'pci/aer', 'pci/enumeration', 'pci/kconfig', 'pci/misc', 'pci/virtualization' and 'pci/vpd' into next
* pci/aer:
  PCI/AER: Log aer_inject error injections
  PCI/AER: Log actual error causes in aer_inject
  PCI/AER: Use dev_warn() in aer_inject
  PCI/AER: Fix aer_inject error codes

* pci/enumeration:
  PCI: Fix broken URL for Dell biosdevname

* pci/kconfig:
  PCI: Cleanup pci/pcie/Kconfig whitespace
  PCI: Include pci/hotplug Kconfig directly from pci/Kconfig
  PCI: Include pci/pcie/Kconfig directly from pci/Kconfig

* pci/misc:
  PCI: Add PCI_CLASS_SERIAL_USB_DEVICE definition
  PCI: Add QEMU top-level IDs for (sub)vendor & device
  unicore32: Remove unused HAVE_ARCH_PCI_SET_DMA_MASK definition
  PCI: Consolidate PCI DMA constants and interfaces in linux/pci-dma-compat.h
  PCI: Move pci_dma_* helpers to common code
  frv/PCI: Remove stray pci_{alloc,free}_consistent() declaration

* pci/virtualization:
  PCI: Wait for up to 1000ms after FLR reset
  PCI: Support SR-IOV on any function type

* pci/vpd:
  PCI: Prevent VPD access for buggy devices
  PCI: Sleep rather than busy-wait for VPD access completion
  PCI: Fold struct pci_vpd_pci22 into struct pci_vpd
  PCI: Rename VPD symbols to remove unnecessary "pci22"
  PCI: Remove struct pci_vpd_ops.release function pointer
  PCI: Move pci_vpd_release() from header file to pci/access.c
  PCI: Move pci_read_vpd() and pci_write_vpd() close to other VPD code
  PCI: Determine actual VPD size on first access
  PCI: Use bitfield instead of bool for struct pci_vpd_pci22.busy
  PCI: Allow access to VPD attributes with size 0
  PCI: Update VPD definitions
2016-03-15 08:55:02 -05:00
Linus Torvalds d09e356ad0 Merge branch 'mm-readonly-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull read-only kernel memory updates from Ingo Molnar:
 "This tree adds two (security related) enhancements to the kernel's
  handling of read-only kernel memory:

   - extend read-only kernel memory to a new class of formerly writable
     kernel data: 'post-init read-only memory' via the __ro_after_init
     attribute, and mark the ARM and x86 vDSO as such read-only memory.

     This kind of attribute can be used for data that requires a once
     per bootup initialization sequence, but is otherwise never modified
     after that point.

     This feature was based on the work by PaX Team and Brad Spengler.

     (by Kees Cook, the ARM vDSO bits by David Brown.)

   - make CONFIG_DEBUG_RODATA always enabled on x86 and remove the
     Kconfig option.  This simplifies the kernel and also signals that
     read-only memory is the default model and a first-class citizen.
     (Kees Cook)"

* 'mm-readonly-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  ARM/vdso: Mark the vDSO code read-only after init
  x86/vdso: Mark the vDSO code read-only after init
  lkdtm: Verify that '__ro_after_init' works correctly
  arch: Introduce post-init read-only memory
  x86/mm: Always enable CONFIG_DEBUG_RODATA and remove the Kconfig option
  mm/init: Add 'rodata=off' boot cmdline parameter to disable read-only kernel mappings
  asm-generic: Consolidate mark_rodata_ro()
2016-03-14 16:58:50 -07:00
Linus Torvalds d37a14bb5f Merge branch 'core-resources-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip
Pull ram resource handling changes from Ingo Molnar:
 "Core kernel resource handling changes to support NVDIMM error
  injection.

  This tree introduces a new I/O resource type, IORESOURCE_SYSTEM_RAM,
  for System RAM while keeping the current IORESOURCE_MEM type bit set
  for all memory-mapped ranges (including System RAM) for backward
  compatibility.

  With this resource flag it no longer takes a strcmp() loop through the
  resource tree to find "System RAM" resources.

  The new resource type is then used to extend ACPI/APEI error injection
  facility to also support NVDIMM"

* 'core-resources-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip:
  ACPI/EINJ: Allow memory error injection to NVDIMM
  resource: Kill walk_iomem_res()
  x86/kexec: Remove walk_iomem_res() call with GART type
  x86, kexec, nvdimm: Use walk_iomem_res_desc() for iomem search
  resource: Add walk_iomem_res_desc()
  memremap: Change region_intersects() to take @flags and @desc
  arm/samsung: Change s3c_pm_run_res() to use System RAM type
  resource: Change walk_system_ram() to use System RAM type
  drivers: Initialize resource entry to zero
  xen, mm: Set IORESOURCE_SYSTEM_RAM to System RAM
  kexec: Set IORESOURCE_SYSTEM_RAM for System RAM
  arch: Set IORESOURCE_SYSTEM_RAM flag for System RAM
  ia64: Set System RAM type and descriptor
  x86/e820: Set System RAM type and descriptor
  resource: Add I/O resource descriptor
  resource: Handle resource flags properly
  resource: Add System RAM resource type
2016-03-14 15:15:51 -07:00
Olof Johansson a86e56cb39 Provide the ARCH_MESON Kconfig symbol for the Amlogic S905 SoCs.
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Merge tag 'for-v4.6/gxbb-arm64' of https://github.com/carlocaione/linux-meson into next/arm64

Provide the ARCH_MESON Kconfig symbol for the Amlogic S905 SoCs.

* tag 'for-v4.6/gxbb-arm64' of https://github.com/carlocaione/linux-meson:
  ARM64: Enable Amlogic Meson GXBaby platform

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:44:51 -08:00
Olof Johansson 8061a17ee3 This series adds initial support for the Amlogic S905 based
Tronsmart Vega S95 Pro, Meta and Telos TV boxes.
 
 - Add new DTS to enable support for the boards
 - Add documentation for compatibles and vendor prefix
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Merge tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson into next/dt64

This series adds initial support for the Amlogic S905 based
Tronsmart Vega S95 Pro, Meta and Telos TV boxes.

- Add new DTS to enable support for the boards
- Add documentation for compatibles and vendor prefix

* tag 'for-v4.6/gxbb-dt' of https://github.com/carlocaione/linux-meson:
  ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
  Documentation: devicetree: amlogic: Document Tronsmart Vega S95 boards
  ARM64: dts: Prepare configs for Amlogic Meson GXBaby
  Documentation: devicetree: amlogic: Document Meson GXBaby
  devicetree: bindings: Add vendor prefix for Tronsmart

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:43:08 -08:00
Masahiro Yamada 2ef7d5f342 ARM, ARM64: dts: drop "arm,amba-bus" in favor of "simple-bus"
The compatible string "simple-bus" is well defined in ePAPR, while
I see no documentation for the "arm,amba-bus" arnywhere in ePAPR or
Documentation/devicetree/.

DT is also used by other projects than Linux kernel.  It is not a
good idea to rely on such an unofficial binding.

This commit
  - replaces "arm,amba-bus" with "simple-bus"
  - drops "arm,amba-bus" where it is used along with "simple-bus"

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:40:34 -08:00
Olof Johansson 301c6e0b16 Additional updates for ARM VExpress/Juno platforms
1. Add support for SBSA Generic Watchdog on foundation models
 
 2. Fix node name unit-address presence/absence mismatch warnings in
    all the device trees
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Merge tag 'vexpress-for-v4.6/dt-updates-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt

Additional updates for ARM VExpress/Juno platforms

1. Add support for SBSA Generic Watchdog on foundation models

2. Fix node name unit-address presence/absence mismatch warnings in
   all the device trees

* tag 'vexpress-for-v4.6/dt-updates-2' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: juno/vexpress: fix node name unit-address presence warnings
  arm64: dts: foundation-v8: add SBSA Generic Watchdog device node

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:26:37 -08:00
Olof Johansson c7e1d89b34 Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
    one ARCH_EXYNOS.
    This depends on clk tree: removal of last presence of ARCH_EXYNOS7.
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Merge tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64

Samsung Exynos ARM64 improvements for v4.6:
1. Remove separate ARCH_EXYNOS7 symbol and consolidate it into
   one ARCH_EXYNOS.

This depends on clk tree: removal of last presence of ARCH_EXYNOS7.

* tag 'samsung-soc64-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
  clk: samsung: Don't build ARMv8 clock drivers on ARMv7
  clk: samsung: Enable COMPILE_TEST for Samsung clocks
  clk: Move vendor's Kconfig into CCF menu section
  clk: mediatek: Fix memory leak on clock init fail
  clk: move the common clock's to_clk_*(_hw) macros to clk-provider.h
  clk: xgene: Remove return from void function
  clk: xgene: Add SoC and PMD PLL clocks with v2 hardware
  Documentation: Update APM X-Gene clock binding for v2 hardware
  clk: s2mps11: remove redundant code
  clk: s2mps11: remove redundant static variables declaration
  clk: s2mps11: allocate only one structure for clock init
  clk: s2mps11: merge two for loops in one
  clk-divider: make sure read-only dividers do not write to their register
  clk: tango4: rename ARCH_TANGOX to ARCH_TANGO
  clk: scpi: Fix checking return value of platform_device_register_simple()
  clk: mvebu: Mark ioremapped memory as __iomem

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:13:34 -08:00
Olof Johansson c8c904471a mvebu dt64 for 4.6 (part 2)
Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board
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Merge tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.6 (part 2)

Add support for the Armada 7K and 8K SoCs and the Armada 8040 DB board

* tag 'mvebu-dt64-4.6-2' of git://git.infradead.org/linux-mvebu:
  arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
  arm64: dts: marvell: update Armada AP806 clock description
  arm64: dts: marvell: add Device Tree files for Armada 7K/8K

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 17:05:27 -08:00
Georgi Djakov 2f85bb09d9 arm64: defconfig: Increase MMC_BLOCK_MINORS to 16
Increase the block minors from the default 8 to 16. The db410c board
by default has eMMC rootfs on the 10th partition.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 16:16:27 -08:00
Georgi Djakov d1be05ab23 arm64: defconfig: Add Qualcomm sdhci and restart functionality
Enable sdhci and restart functionality for devices based on msm8916 platform.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-03-12 16:16:15 -08:00
Catalin Marinas 2776e0e8ef arm64: kasan: Fix zero shadow mapping overriding kernel image shadow
With the 16KB and 64KB page size configurations, SWAPPER_BLOCK_SIZE is
PAGE_SIZE and ARM64_SWAPPER_USES_SECTION_MAPS is 0. Since
kimg_shadow_end is not page aligned (_end shifted by
KASAN_SHADOW_SCALE_SHIFT), the edges of previously mapped kernel image
shadow via vmemmap_populate() may be overridden by subsequent calls to
kasan_populate_zero_shadow(), leading to kernel panics like below:

------------------------------------------------------------------------------
Unable to handle kernel paging request at virtual address fffffc100135068c
pgd = fffffc8009ac0000
[fffffc100135068c] *pgd=00000009ffee0003, *pud=00000009ffee0003, *pmd=00000009ffee0003, *pte=00e0000081a00793
Internal error: Oops: 9600004f [#1] PREEMPT SMP
Modules linked in:
CPU: 0 PID: 1 Comm: swapper/0 Not tainted 4.5.0-rc4+ #1984
Hardware name: Juno (DT)
task: fffffe09001a0000 ti: fffffe0900200000 task.ti: fffffe0900200000
PC is at __memset+0x4c/0x200
LR is at kasan_unpoison_shadow+0x34/0x50
pc : [<fffffc800846f1cc>] lr : [<fffffc800821ff54>] pstate: 00000245
sp : fffffe0900203db0
x29: fffffe0900203db0 x28: 0000000000000000
x27: 0000000000000000 x26: 0000000000000000
x25: fffffc80099b69d0 x24: 0000000000000001
x23: 0000000000000000 x22: 0000000000002000
x21: dffffc8000000000 x20: 1fffff9001350a8c
x19: 0000000000002000 x18: 0000000000000008
x17: 0000000000000147 x16: ffffffffffffffff
x15: 79746972100e041d x14: ffffff0000000000
x13: ffff000000000000 x12: 0000000000000000
x11: 0101010101010101 x10: 1fffffc11c000000
x9 : 0000000000000000 x8 : fffffc100135068c
x7 : 0000000000000000 x6 : 000000000000003f
x5 : 0000000000000040 x4 : 0000000000000004
x3 : fffffc100134f651 x2 : 0000000000000400
x1 : 0000000000000000 x0 : fffffc100135068c

Process swapper/0 (pid: 1, stack limit = 0xfffffe0900200020)
Call trace:
[<fffffc800846f1cc>] __memset+0x4c/0x200
[<fffffc8008220044>] __asan_register_globals+0x5c/0xb0
[<fffffc8008a09d34>] _GLOBAL__sub_I_65535_1_sunrpc_cache_lookup+0x1c/0x28
[<fffffc8008f20d28>] kernel_init_freeable+0x104/0x274
[<fffffc80089e1948>] kernel_init+0x10/0xf8
[<fffffc8008093a00>] ret_from_fork+0x10/0x50
------------------------------------------------------------------------------

This patch aligns kimg_shadow_start and kimg_shadow_end to
SWAPPER_BLOCK_SIZE in all configurations.

Fixes: f9040773b7 ("arm64: move kernel image to base of vmalloc area")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
2016-03-11 11:03:35 +00:00
Catalin Marinas 2f76969f2e arm64: kasan: Use actual memory node when populating the kernel image shadow
With the 16KB or 64KB page configurations, the generic
vmemmap_populate() implementation warns on potential offnode
page_structs via vmemmap_verify() because the arm64 kasan_init() passes
NUMA_NO_NODE instead of the actual node for the kernel image memory.

Fixes: f9040773b7 ("arm64: move kernel image to base of vmalloc area")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: James Morse <james.morse@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
2016-03-11 11:03:34 +00:00
Catalin Marinas fdc69e7df3 arm64: Update PTE_RDONLY in set_pte_at() for PROT_NONE permission
The set_pte_at() function must update the hardware PTE_RDONLY bit
depending on the state of the PTE_WRITE and PTE_DIRTY bits of the given
entry value. However, it currently only performs this for pte_valid()
entries, ignoring PTE_PROT_NONE. The side-effect is that PROT_NONE
mappings would not have the PTE_RDONLY bit set. Without
CONFIG_ARM64_HW_AFDBM, this is not an issue since such PROT_NONE pages
are not accessible anyway.

With commit 2f4b829c62 ("arm64: Add support for hardware updates of
the access and dirty pte bits"), the ptep_set_wrprotect() function was
re-written to cope with automatic hardware updates of the dirty state.
As an optimisation, only PTE_RDONLY is checked to assess the "dirty"
status. Since set_pte_at() does not set this bit for PROT_NONE mappings,
such pages may be considered "dirty" as a result of
ptep_set_wrprotect().

This patch updates the pte_valid() check to pte_present() in
set_pte_at(). It also adds PTE_PROT_NONE to the swap entry bits comment.

Fixes: 2f4b829c62 ("arm64: Add support for hardware updates of the access and dirty pte bits")
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
Reported-by: Ganapatrao Kulkarni <gkulkarni@caviumnetworks.com>
Tested-by: Ganapatrao Kulkarni <gkulkarni@cavium.com>
Cc: <stable@vger.kernel.org>
2016-03-11 11:03:34 +00:00
Linus Torvalds c32c2cb272 arm64 fixes:
- Temporarily disable huge pages built using contiguous ptes
 - Ensure vmemmap region is sufficiently aligned for sparsemem sections
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
 "I thought we were done for 4.5, but then the 64k-page chaps came
  crawling out of the woodwork.  *sigh*

  The vmemmap fix I sent for -rc7 caused a regression with 64k pages and
  sparsemem and at some point during the release cycle the new hugetlb
  code using contiguous ptes started failing the libhugetlbfs tests with
  64k pages enabled.

  So here are a couple of patches that fix the vmemmap alignment and
  disable the new hugetlb page sizes whilst a proper fix is being
  developed:

   - Temporarily disable huge pages built using contiguous ptes

   - Ensure vmemmap region is sufficiently aligned for sparsemem
     sections"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: hugetlb: partial revert of 66b3923a1a
  arm64: account for sparsemem section alignment when choosing vmemmap offset
2016-03-10 10:39:04 -08:00
Mark Rutland 0d97e6d802 arm64: kasan: clear stale stack poison
Functions which the compiler has instrumented for KASAN place poison on
the stack shadow upon entry and remove this poison prior to returning.

In the case of cpuidle, CPUs exit the kernel a number of levels deep in
C code.  Any instrumented functions on this critical path will leave
portions of the stack shadow poisoned.

If CPUs lose context and return to the kernel via a cold path, we
restore a prior context saved in __cpu_suspend_enter are forgotten, and
we never remove the poison they placed in the stack shadow area by
functions calls between this and the actual exit of the kernel.

Thus, (depending on stackframe layout) subsequent calls to instrumented
functions may hit this stale poison, resulting in (spurious) KASAN
splats to the console.

To avoid this, clear any stale poison from the idle thread for a CPU
prior to bringing a CPU online.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Reviewed-by: Andrey Ryabinin <aryabinin@virtuozzo.com>
Reviewed-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Cc: Alexander Potapenko <glider@google.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ingo Molnar <mingo@kernel.org>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-03-09 15:43:42 -08:00
Will Deacon ff7925848b arm64: hugetlb: partial revert of 66b3923a1a
Commit 66b3923a1a ("arm64: hugetlb: add support for PTE contiguous bit")
introduced support for huge pages using the contiguous bit in the PTE
as opposed to block mappings, which may be slightly unwieldy (512M) in
64k page configurations.

Unfortunately, this support has resulted in some late regressions when
running the libhugetlbfs test suite with 64k pages and CONFIG_DEBUG_VM
as a result of a BUG:

 | readback (2M: 64):	------------[ cut here ]------------
 | kernel BUG at fs/hugetlbfs/inode.c:446!
 | Internal error: Oops - BUG: 0 [#1] SMP
 | Modules linked in:
 | CPU: 7 PID: 1448 Comm: readback Not tainted 4.5.0-rc7 #148
 | Hardware name: linux,dummy-virt (DT)
 | task: fffffe0040964b00 ti: fffffe00c2668000 task.ti: fffffe00c2668000
 | PC is at remove_inode_hugepages+0x44c/0x480
 | LR is at remove_inode_hugepages+0x264/0x480

Rather than revert the entire patch, simply avoid advertising the
contiguous huge page sizes for now while people are actively working on
a fix. This patch can then be reverted once things have been sorted out.

Cc: David Woods <dwoods@ezchip.com>
Reported-by: Steve Capper <steve.capper@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-03-09 15:29:29 +00:00
Ard Biesheuvel 36e5cd6b89 arm64: account for sparsemem section alignment when choosing vmemmap offset
Commit dfd55ad85e ("arm64: vmemmap: use virtual projection of linear
region") fixed an issue where the struct page array would overflow into the
adjacent virtual memory region if system RAM was placed so high up in
physical memory that its addresses were not representable in the build time
configured virtual address size.

However, the fix failed to take into account that the vmemmap region needs
to be relatively aligned with respect to the sparsemem section size, so that
a sequence of page structs corresponding with a sparsemem section in the
linear region appears naturally aligned in the vmemmap region.

So round up vmemmap to sparsemem section size. Since this essentially moves
the projection of the linear region up in memory, also revert the reduction
of the size of the vmemmap region.

Cc: <stable@vger.kernel.org>
Fixes: dfd55ad85e ("arm64: vmemmap: use virtual projection of linear region")
Tested-by: Mark Langsdorf <mlangsdo@redhat.com>
Tested-by: David Daney <david.daney@cavium.com>
Tested-by: Robert Richter <rrichter@cavium.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-03-09 14:57:08 +00:00
Marc Zyngier b40c4892d1 arm64: KVM: vgic-v3: Only wipe LRs on vcpu exit
So far, we're always writing all possible LRs, setting the empty
ones with a zero value. This is obvious doing a low of work for
nothing, and we're better off clearing those we've actually
dirtied on the exit path (it is very rare to inject more than one
interrupt at a time anyway).

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09 04:24:16 +00:00
Marc Zyngier 0d98d00b8d arm64: KVM: vgic-v3: Reset LRs at boot time
In order to let the GICv3 code be more lazy in the way it
accesses the LRs, it is necessary to start with a clean slate.

Let's reset the LRs on each CPU when the vgic is probed (which
includes a round trip to EL2...).

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09 04:24:09 +00:00
Marc Zyngier 84e8b9c88d arm64: KVM: vgic-v3: Do not save an LR known to be empty
On exit, any empty LR will be signaled in ICH_ELRSR_EL2. Which
means that we do not have to save it, and we can just clear
its state in the in-memory copy.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09 04:24:07 +00:00
Marc Zyngier b4344545cf arm64: KVM: vgic-v3: Save maintenance interrupt state only if required
Next on our list of useless accesses is the maintenance interrupt
status registers (ICH_MISR_EL2, ICH_EISR_EL2).

It is pointless to save them if we haven't asked for a maintenance
interrupt the first place, which can only happen for two reasons:
- Underflow: ICH_HCR_UIE will be set,
- EOI: ICH_LR_EOI will be set.

These conditions can be checked on the in-memory copies of the regs.
Should any of these two condition be valid, we must read GICH_MISR.
We can then check for ICH_MISR_EOI, and only when set read
ICH_EISR_EL2.

This means that in most case, we don't have to save them at all.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09 04:24:06 +00:00
Marc Zyngier 1b8e83c04e arm64: KVM: vgic-v3: Avoid accessing ICH registers
Just like on GICv2, we're a bit hammer-happy with GICv3, and access
them more often than we should.

Adopt a policy similar to what we do for GICv2, only save/restoring
the minimal set of registers. As we don't access the registers
linearly anymore (we may skip some), the convoluted accessors become
slightly simpler, and we can drop the ugly indexing macro that
tended to confuse the reviewers.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-03-09 04:24:04 +00:00
Bjorn Helgaas e7e127e3c7 PCI: Include pci/hotplug Kconfig directly from pci/Kconfig
Include pci/hotplug/Kconfig directly from pci/Kconfig, so arches don't
have to source both pci/Kconfig and pci/hotplug/Kconfig.

Note that this effectively adds pci/hotplug/Kconfig to the following
arches, because they already sourced drivers/pci/Kconfig but they
previously did not source drivers/pci/hotplug/Kconfig:

  alpha
  arm
  avr32
  frv
  m68k
  microblaze
  mn10300
  sparc
  unicore32

Inspired-by-patch-from: Bogicevic Sasa <brutallesale@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-03-08 15:10:48 -06:00
Bogicevic Sasa 5f8fc43217 PCI: Include pci/pcie/Kconfig directly from pci/Kconfig
Include pci/pcie/Kconfig directly from pci/Kconfig, so arches don't
have to source both pci/Kconfig and pci/pcie/Kconfig.

Note that this effectively adds pci/pcie/Kconfig to the following
arches, because they already sourced drivers/pci/Kconfig but they
previously did not source drivers/pci/pcie/Kconfig:

  alpha
  avr32
  blackfin
  frv
  m32r
  m68k
  microblaze
  mn10300
  parisc
  sparc
  unicore32
  xtensa

[bhelgaas: changelog, source pci/pcie/Kconfig at top of pci/Kconfig, whitespace]
Signed-off-by: Sasa Bogicevic <brutallesale@gmail.com>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-03-08 14:36:48 -06:00
David S. Miller 810813c47a Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Several cases of overlapping changes, as well as one instance
(vxlan) of a bug fix in 'net' overlapping with code movement
in 'net-next'.

Signed-off-by: David S. Miller <davem@davemloft.net>
2016-03-08 12:34:12 -05:00
Sudeep Holla 6d6acd140a arm64: dts: juno/vexpress: fix node name unit-address presence warnings
Commit fa38a82096a1 ("scripts/dtc: Update to upstream version
53bf130b1cdd") added warnings on node name unit-address presence/absence
mismatch in device trees.

This patch fixes those warning on all the juno/vexpress platforms where
unit-address is present in node name while the reg/ranges property is
not present. It also adds unit-address to all smb bus node.

Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-03-08 13:54:27 +00:00
Fu Wei 4739f74453 arm64: dts: foundation-v8: add SBSA Generic Watchdog device node
This can be a example of adding SBSA Generic Watchdog device node
into some dts files for the Soc which contains SBSA Generic Watchdog.

Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Fu Wei <fu.wei@linaro.org>
[edited subject and moved change to dtsi file]
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
2016-03-08 10:35:01 +00:00
Christoph Hellwig bc4b024a8b PCI: Move pci_dma_* helpers to common code
For a long time all architectures implement the pci_dma_* functions using
the generic DMA API, and they all use the same header to do so.

Move this header, pci-dma-compat.h, to include/linux and include it from
the generic pci.h instead of having each arch duplicate this include.

Signed-off-by: Christoph Hellwig <hch@lst.de>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
2016-03-07 10:40:02 -06:00
Andreas Färber cc733bc906 ARM64: dts: amlogic: Add Tronsmart Vega S95 configs
Add Device Trees for Tronsmart Vega S95 Pro, Meta and Telos TV boxes.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
2016-03-07 11:12:40 +01:00
Andreas Färber 4f24eda840 ARM64: dts: Prepare configs for Amlogic Meson GXBaby
Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
2016-03-07 11:12:40 +01:00
Andreas Färber 451e9e54e2 ARM64: Enable Amlogic Meson GXBaby platform
Provide the ARCH_MESON Kconfig symbol to allow enabling existing serial
and i2c drivers.

Signed-off-by: Andreas Färber <afaerber@suse.de>
Signed-off-by: Carlo Caione <carlo@endlessm.com>
2016-03-07 10:44:31 +01:00
Linus Torvalds ed385c7a17 arm64 fix:
- Ensure struct page array fits within vmemmap area
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fix from Will Deacon:
 "Arm64 fix for -rc7.  Without it, our struct page array can overflow
  the vmemmap region on systems with a large PHYS_OFFSET.

  Nothing else on the radar at the moment, so hopefully that's it for
  4.5 from us.

  Summary: Ensure struct page array fits within vmemmap area"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: vmemmap: use virtual projection of linear region
2016-03-04 17:43:40 -08:00
Russell King 1b3bf84797 Merge branches 'amba', 'fixes', 'misc' and 'tauros2' into for-next 2016-03-04 23:36:02 +00:00
Adam Buchbinder ef769e3208 arm64: Fix misspellings in comments.
Signed-off-by: Adam Buchbinder <adam.buchbinder@gmail.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-04 18:19:17 +00:00
Ard Biesheuvel cd1b76bb73 arm64: efi: add missing frame pointer assignment
The prologue of the EFI entry point pushes x29 and x30 onto the stack but
fails to create the stack frame correctly by omitting the assignment of x29
to the new value of the stack pointer. So fix that.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-04 18:12:23 +00:00
Mark Rutland 1cc6ed90dd arm64: make mrs_s prefixing implicit in read_cpuid
Commit 0f54b14e76 ("arm64: cpufeature: Change read_cpuid() to use
sysreg's mrs_s macro") changed read_cpuid to require a SYS_ prefix on
register names, to allow manual assembly of registers unknown by the
toolchain, using tables in sysreg.h.

This interacts poorly with commit 42b5573403 ("efi/arm64: Check
for h/w support before booting a >4 KB granular kernel"), which is
curretly queued via the tip tree, and uses read_cpuid without a SYS_
prefix. Due to this, a build of next-20160304 fails if EFI and 64K pages
are selected.

To avoid this issue when trees are merged, move the required SYS_
prefixing into read_cpuid, and revert all of the updated callsites to
pass plain register names. This effectively reverts the bulk of commit
0f54b14e76.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Cc: James Morse <james.morse@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-04 14:12:46 +00:00
Ingo Molnar bc94b99636 Linux 4.5-rc6
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Merge tag 'v4.5-rc6' into core/resources, to resolve conflict

Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-03-04 12:12:08 +01:00
Linus Torvalds c2687cf950 * ARM/MIPS: Fixes for ioctls when copy_from_user returns nonzero
* x86: Small fix for Skylake TSC scaling
 * x86: Improved fix for last week's missed hardware breakpoint bug
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
 - ARM/MIPS: Fixes for ioctls when copy_from_user returns nonzero
 - x86: Small fix for Skylake TSC scaling
 - x86: Improved fix for last week's missed hardware breakpoint bug

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  kvm: x86: Update tsc multiplier on change.
  mips/kvm: fix ioctl error handling
  arm/arm64: KVM: Fix ioctl error handling
  KVM: x86: fix root cause for missed hardware breakpoints
2016-03-03 11:54:56 -08:00
Ard Biesheuvel 57efac2f71 arm64: enable CONFIG_DEBUG_RODATA by default
In spite of its name, CONFIG_DEBUG_RODATA is an important hardening feature
for production kernels, and distros all enable it by default in their
kernel configs. However, since enabling it used to result in more granular,
and thus less efficient kernel mappings, it is not enabled by default for
performance reasons.

However, since commit 2f39b5f91e ("arm64: mm: Mark .rodata as RO"), the
various kernel segments (.text, .rodata, .init and .data) are already
mapped individually, and the only effect of setting CONFIG_DEBUG_RODATA is
that the existing .text and .rodata mappings are updated late in the boot
sequence to have their read-only attributes set, which means that any
performance concerns related to enabling CONFIG_DEBUG_RODATA are no longer
valid.

So from now on, make CONFIG_DEBUG_RODATA default to 'y'

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Kees Cook <keescook@chromium.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-03 18:14:17 +00:00
Arnd Bergmann c88f7e6a52 ARM64 defconfig changes for Exynos based boards for v4.6:
1. We want thermal for Exynos7 TMU unit to monitor the temperature.
 2. Enable the drivers for PMIC used on Exynos7-based Espresso board.
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Merge tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux into next/arm64

Merge "ARM64 defconfig changes for Exynos based boards for v4.6" from Krzysztof Kozlowski:

1. We want thermal for Exynos7 TMU unit to monitor the temperature.
2. Enable the drivers for PMIC used on Exynos7-based Espresso board.

* tag 'samsung-defconfig-4.6-2' of git://git.kernel.org/pub/scm/linux/kernel/git/krzk/linux:
  arm64: defconfig: Enable Samsung MFD and related configs
  arm64: defconfig: Enable exynos thermal config
  ARM: multi_v7_defconfig: Remove MAX77802 RTC Kconfig symbol
  ARM: exynos_defconfig: Remove MAX77802 RTC Kconfig symbol
  rtc: max77686: Cleanup and reduce dmesg output
  rtc: Remove Maxim 77802 driver
  rtc: max77686: Properly handle regmap_irq_get_virq() error code
  rtc: max77686: Fix unsupported year message
  rtc: max77686: Add max77802 support
  rtc: max77686: Add an indirection level to access RTC registers
  rtc: max77686: Use a driver data struct instead hard-coded values
  rtc: max77686: Use usleep_range() instead of msleep()
  rtc: max77686: Use ARRAY_SIZE() instead of current array length
  rtc: max77686: Fix max77686_rtc_read_alarm() return value
  ARM: exynos_defconfig: Enable s5p-secss driver
  ARM: exynos_defconfig: Enable NEON, accelerated crypto and cpufreq stats

Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-03-02 23:15:48 +01:00
Arnd Bergmann 720721b5de The NXP/Freescale arm64 dts update for 4.6:
- Add "snps,quirk-frame-length-adjustment" property to USB3 node for
   erratum A009116, which affects NXP/Freescale arm64 SoCs LS1043A and
   LS2080A.
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Merge tag 'imx-dt64-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux into next/dt64

Merge "NXP/Freescale arm64 dts update for 4.6" from Shawn Guo:

- Add "snps,quirk-frame-length-adjustment" property to USB3 node for
  erratum A009116, which affects NXP/Freescale arm64 SoCs LS1043A and
  LS2080A.

* tag 'imx-dt64-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/shawnguo/linux:
  arm64: dts: ls1043a: Add quirk for Erratum A009116
  arm64: dts: ls2080a: Add quirk for Erratum A009116
2016-03-02 23:02:27 +01:00
Arnd Bergmann 3bbf58531f Qualcomm ARM64 Updates for v4.6
* Add MSM8996 support
 * Cleanups for MSM8916
 * Updates for APQ8016 SBC
 * Fixup pmic reg properties
 * Add RPMCC node for 8916
 * Add LPASS audio nodes
 * Add USB support on MSM8916
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Merge tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux into next/dt64

Merge "Qualcomm ARM64 Updates for v4.6" from Andy Gross:

* Add MSM8996 support
* Cleanups for MSM8916
* Updates for APQ8016 SBC
* Fixup pmic reg properties
* Add RPMCC node for 8916
* Add LPASS audio nodes
* Add USB support on MSM8916

* tag 'qcom-arm64-for-4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/agross/linux: (24 commits)
  arm64: dts: qcom: Fix MPP's function used for LED control
  arm64: dts: qcom: fix usb digital voltage levels
  arm64: dts: qcom: apq8016-sbc: enable lpass on DB410c
  arm64: dts: qcom: add lpass node
  arm64: dts: qcom: add audio pinctrls
  arm64: dts: qcom: apq8016-sbc: add usb support
  arm64: dts: qcom: add manual pullup setting to otg.
  arm64: dts: qcom: msm8916: Add RPMCC DT node
  ARM64: dts: qcom: Remove size elements from pmic reg properties
  arm64: dts: msm8996: Add #power-domain-cells property
  arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhc
  arm64: dts: apq8016-sbc: move sdhci node under soc node
  arm64: dts: apq8016-sbc: make 1.8v available on LS expansion
  arm64: dts: apq8016-sbc: add regulators support
  arm64: dts: qcom: add lable for smd rpm regulators
  arm64: dts: remove s2 regulator from smd regulators.
  arm64: dts: qcom: add correct drive strenght on cs pins
  arm64: dts: qcom: remove redundant spi cs pins from pinconf
  arm64: dts: apq8016-sbc: Add aliases to spi device.
  arm64: dts: Add L2 cache node to msm8916
  ...
2016-03-02 22:28:30 +01:00
Mark Rutland dbd4d7ca56 arm64: Rework valid_user_regs
We validate pstate using PSR_MODE32_BIT, which is part of the
user-provided pstate (and cannot be trusted). Also, we conflate
validation of AArch32 and AArch64 pstate values, making the code
difficult to reason about.

Instead, validate the pstate value based on the associated task. The
task may or may not be current (e.g. when using ptrace), so this must be
passed explicitly by callers. To avoid circular header dependencies via
sched.h, is_compat_task is pulled out of asm/ptrace.h.

To make the code possible to reason about, the AArch64 and AArch32
validation is split into separate functions. Software must respect the
RES0 policy for SPSR bits, and thus the kernel mirrors the hardware
policy (RAZ/WI) for bits as-yet unallocated. When these acquire an
architected meaning writes may be permitted (potentially with additional
validation).

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Dave Martin <dave.martin@arm.com>
Cc: James Morse <james.morse@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-02 15:49:28 +00:00
Ard Biesheuvel 6d2aa549de arm64: mm: check at build time that PAGE_OFFSET divides the VA space evenly
Commit 8439e62a15 ("arm64: mm: use bit ops rather than arithmetic in
pa/va translations") changed the boundary check against PAGE_OFFSET from
an arithmetic comparison to a bit test. This means we now silently assume
that PAGE_OFFSET is a power of 2 that divides the kernel virtual address
space into two equal halves. So make that assumption explicit.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-02 09:45:52 +00:00
Paolo Bonzini 2b097e9bc3 KVM/ARM fixes for 4.5-rc7
- Fix ioctl error handling on the timer path
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Merge tag 'kvm-arm-for-4.5-rc7' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master

KVM/ARM fixes for 4.5-rc7

- Fix ioctl error handling on the timer path
2016-03-02 10:31:30 +01:00
Thomas Gleixner fc6d73d674 arch/hotplug: Call into idle with a proper state
Let the non boot cpus call into idle with the corresponding hotplug state, so
the hotplug core can handle the further bringup. That's a first step to
convert the boot side of the hotplugged cpus to do all the synchronization
with the other side through the state machine. For now it'll only start the
hotplug thread and kick the full bringup of the cpu.

Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arch@vger.kernel.org
Cc: Rik van Riel <riel@redhat.com>
Cc: Rafael Wysocki <rafael.j.wysocki@intel.com>
Cc: "Srivatsa S. Bhat" <srivatsa@mit.edu>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Sebastian Siewior <bigeasy@linutronix.de>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Steven Rostedt <rostedt@goodmis.org>
Cc: Oleg Nesterov <oleg@redhat.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Paul McKenney <paulmck@linux.vnet.ibm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Paul Turner <pjt@google.com>
Link: http://lkml.kernel.org/r/20160226182341.614102639@linutronix.de
Signed-off-by: Thomas Gleixner <tglx@linutronix.de>
2016-03-01 20:36:57 +01:00
Marc Zyngier 22b39ca3f2 arm64: KVM: Move kvm_call_hyp back to its original localtion
In order to reduce the risk of a bad merge, let's move the new
kvm_call_hyp back to its original location in the file. This has
zero impact from a code point of view.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-03-01 13:49:51 +00:00
Alim Akhtar 6bb8371893 arm64: defconfig: Enable Samsung MFD and related configs
Exynos7 based espresso board uses S2MPS15, a multifunction device.
This patch enables S2MPS1X regulator, pmic-clk and rtc drivers utilized by
the same.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-03-01 17:55:03 +09:00
Arnd Bergmann 44563cb452 Second part of X-Gene DT changes queued for v4.6
This patch set includes:
 + X-Gene v2 Mailbox DT node
 + X-Gene v1 and X-Gene v2 SLIMpro Mailbox
 I2C driver DT nodes
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Merge tag 'xgene-dts-for-v4.6-part2' of https://github.com/AppliedMicro/xgene-next into next/dt64

Merge "Second part of X-Gene DT changes queued for v4.6" from Duc Dang:

This patch set includes:
+ X-Gene v2 Mailbox DT node
+ X-Gene v1 and X-Gene v2 SLIMpro Mailbox
I2C driver DT nodes

* tag 'xgene-dts-for-v4.6-part2' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
  arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
  arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
2016-03-01 00:40:58 +01:00
Arnd Bergmann 1c268a8911 First part of X-Gene DT changes queued for v4.6
This patch set includes:
 + A change in compatible string of X-Gene v2 SoC
 PLL DT node to reflect the v2 hardware
 + Update DT fields for X-Gene v1 and v2 standby
 GPIO controllers
 + Update declaration of power button GPIO for
 X-Gene v1 and X-Gene v2 platforms
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Merge tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next into next/dt64

Merge "First part of X-Gene DT changes queued for v4.6" from Duc Dang:

This patch set includes:
+ A change in compatible string of X-Gene v2 SoC
PLL DT node to reflect the v2 hardware
+ Update DT fields for X-Gene v1 and v2 standby
GPIO controllers
+ Update declaration of power button GPIO for
X-Gene v1 and X-Gene v2 platforms

* tag 'xgene-dts-for-v4.6-part1' of https://github.com/AppliedMicro/xgene-next:
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
  arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
  arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
  arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries
  arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware
2016-03-01 00:36:51 +01:00
Arnd Bergmann 31cf19a14c ARM64: Hip05: configure updates for 4.6
- Enable DesignWare APB GPIO controller
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Merge tag 'hip05-config-for-4.6' of git://github.com/hisilicon/linux-hisi into next/arm64

ARM64: Hip05: configure updates for 4.6

- Enable DesignWare APB GPIO controller

* tag 'hip05-config-for-4.6' of git://github.com/hisilicon/linux-hisi:
  arm64: defconfig: Enable DesignWare APB GPIO controller
2016-03-01 00:30:30 +01:00
Will Deacon fe638401a0 arm64: perf: Extend ARMV8_EVTYPE_MASK to include PMCR.LC
Commit 7175f0591e ("arm64: perf: Enable PMCR long cycle counter bit")
added initial support for a 64-bit cycle counter enabled using PMCR.LC.

Unfortunately, that patch doesn't extend ARMV8_EVTYPE_MASK, so any
attempts to set the enable bit are ignored by armv8pmu_pmcr_write.

This patch extends the mask to include the new bit.

Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-29 23:23:59 +00:00
Arnd Bergmann 047b2f6d7b ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6
- Add L2 cache topology
 - Use Cortex specific device node for pmu
 - Append all gicv3 ITS entries
 - Append gpio nodes
 - Append power button node for D02 board
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Merge tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi into next/dt64

Merge "ARM64: DT: Hisilicon Hip05 soc and D02 board updates for 4.6" from Wei Xu:

- Add L2 cache topology
- Use Cortex specific device node for pmu
- Append all gicv3 ITS entries
- Append gpio nodes
- Append power button node for D02 board

* tag 'hip05-dt-for-4.6' of git://github.com/hisilicon/linux-hisi:
  arm64: dts: hip05: Append power button node for D02 board
  arm64: dts: hip05: Append gpio nodes
  arm64: dts: hip05: Append all gicv3 ITS entries
  arm64: dts: hip05: Use Cortex specific device node for pmu
  arm64: dts: hip05: Add L2 cache topology
2016-03-01 00:22:23 +01:00
Arnd Bergmann e5db3c6321 Allwinner configuration changes for ARM64, 4.6 edition
Not a lot of changes for this kernel release, just a new Kconfig option and
 some changes to the arm64 defconfig to add Allwinner drivers
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Merge tag 'sunxi-config64-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux into next/arm64

Merge "Allwinner configuration changes for ARM64, 4.6 edition" from Maxime Ripard:

Not a lot of changes for this kernel release, just a new Kconfig option and
some changes to the arm64 defconfig to add Allwinner drivers

* tag 'sunxi-config64-for-4.6' of https://git.kernel.org/pub/scm/linux/kernel/git/mripard/linux:
  arm64: add defconfig options for Allwinner SoCs
  arm64: Introduce Allwinner SoC config option
2016-03-01 00:06:24 +01:00
Arnd Bergmann 5f84a8efc4 mvebu arm64 for 4.6 (part 2)
Add initial support for Armada 7K/8K
 Update Marvell documentation
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Merge tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu into next/arm64

Merge "mvebu arm64 for 4.6 (part 2)" from Gregory CLEMENT:

Add initial support for Armada 7K/8K
Update Marvell documentation

* tag 'mvebu-arm64-4.6-2' of git://git.infradead.org/linux-mvebu:
  arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
  Documentation: arm: add Marvell Armada 7K and 8K families
  Documentation: arm: add link to Armada 38x Functional Spec
  Documentation: arm: improve Armada 37xx description
  Documentation: arm: update Marvell product listing
2016-03-01 00:01:31 +01:00
Ivan T. Ivanov 4bd40f6ceb arm64: dts: qcom: Fix MPP's function used for LED control
The qcom-spmi-mpp driver is now using string "digital" to denote
old "normal" functionality. Update DTS file.
Also update the powersource.

Signed-off-by: Ivan T. Ivanov <ivan.ivanov@linaro.org>
2016-02-29 16:17:45 -06:00
Marc Zyngier 623eefa8d0 arm64: KVM: Switch the sys_reg search to be a binary search
Our 64bit sys_reg table is about 90 entries long (so far, and the
PMU support is likely to increase this). This means that on average,
it takes 45 comparaisons to find the right entry (and actually the
full 90 if we have to search the invariant table).

Not the most efficient thing. Specially when you think that this
table is already sorted. Switching to a binary search effectively
reduces the search to about 7 comparaisons. Slightly better!

As an added bonus, the comparison is done by comparing all the
fields at once, instead of one at a time.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:22 +00:00
Shannon Zhao bb0c70bcca arm64: KVM: Add a new vcpu device control group for PMUv3
To configure the virtual PMUv3 overflow interrupt number, we use the
vcpu kvm_device ioctl, encapsulating the KVM_ARM_VCPU_PMU_V3_IRQ
attribute within the KVM_ARM_VCPU_PMU_V3_CTRL group.

After configuring the PMUv3, call the vcpu ioctl with attribute
KVM_ARM_VCPU_PMU_V3_INIT to initialize the PMUv3.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao f577f6c2a6 arm64: KVM: Introduce per-vcpu kvm device controls
In some cases it needs to get/set attributes specific to a vcpu and so
needs something else than ONE_REG.

Let's copy the KVM_DEVICE approach, and define the respective ioctls
for the vcpu file descriptor.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao 808e738142 arm64: KVM: Add a new feature bit for PMUv3
To support guest PMUv3, use one bit of the VCPU INIT feature array.
Initialize the PMU when initialzing the vcpu with that bit and PMU
overflow interrupt set.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Acked-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao 2aa36e9840 arm64: KVM: Reset PMU state when resetting vcpu
When resetting vcpu, it needs to reset the PMU state to initial status.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao d692b8ad6e arm64: KVM: Add access handler for PMUSERENR register
This register resets as unknown in 64bit mode while it resets as zero
in 32bit mode. Here we choose to reset it as zero for consistency.

PMUSERENR_EL0 holds some bits which decide whether PMU registers can be
accessed from EL0. Add some check helpers to handle the access from EL0.

When these bits are zero, only reading PMUSERENR will trap to EL2 and
writing PMUSERENR or reading/writing other PMU registers will trap to
EL1 other than EL2 when HCR.TGE==0. To current KVM configuration
(HCR.TGE==0) there is no way to get these traps. Here we write 0xf to
physical PMUSERENR register on VM entry, so that it will trap PMU access
from EL0 to EL2. Within the register access handler we check the real
value of guest PMUSERENR register to decide whether this access is
allowed. If not allowed, return false to inject UND to guest.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao 76993739cd arm64: KVM: Add helper to handle PMCR register bits
According to ARMv8 spec, when writing 1 to PMCR.E, all counters are
enabled by PMCNTENSET, while writing 0 to PMCR.E, all counters are
disabled. When writing 1 to PMCR.P, reset all event counters, not
including PMCCNTR, to zero. When writing 1 to PMCR.C, reset PMCCNTR to
zero.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:21 +00:00
Shannon Zhao 7a0adc7064 arm64: KVM: Add access handler for PMSWINC register
Add access handler which emulates writing and reading PMSWINC
register and add support for creating software increment event.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao 76d883c4e6 arm64: KVM: Add access handler for PMOVSSET and PMOVSCLR register
Since the reset value of PMOVSSET and PMOVSCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMOVSSET or PMOVSCLR register.

When writing non-zero value to PMOVSSET, the counter and its interrupt
is enabled, kick this vcpu to sync PMU interrupt.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao 9db52c78cd arm64: KVM: Add access handler for PMINTENSET and PMINTENCLR register
Since the reset value of PMINTENSET and PMINTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMINTENSET or PMINTENCLR register.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao 9feb21ac57 arm64: KVM: Add access handler for event type register
These kind of registers include PMEVTYPERn, PMCCFILTR and PMXEVTYPER
which is mapped to PMEVTYPERn or PMCCFILTR.

The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.

When writing to these registers, create a perf_event for the selected
event type.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao 96b0eebcc6 arm64: KVM: Add access handler for PMCNTENSET and PMCNTENCLR register
Since the reset value of PMCNTENSET and PMCNTENCLR is UNKNOWN, use
reset_unknown for its reset handler. Add a handler to emulate writing
PMCNTENSET or PMCNTENCLR register.

When writing to PMCNTENSET, call perf_event_enable to enable the perf
event. When writing to PMCNTENCLR, call perf_event_disable to disable
the perf event.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao 051ff581ce arm64: KVM: Add access handler for event counter register
These kind of registers include PMEVCNTRn, PMCCNTR and PMXEVCNTR which
is mapped to PMEVCNTRn.

The access handler translates all aarch32 register offsets to aarch64
ones and uses vcpu_sys_reg() to access their values to avoid taking care
of big endian.

When reading these registers, return the sum of register value and the
value perf event counts.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:20 +00:00
Shannon Zhao a86b550530 arm64: KVM: Add access handler for PMCEID0 and PMCEID1 register
Add access handler which gets host value of PMCEID0 or PMCEID1 when
guest access these registers. Writing action to PMCEID0 or PMCEID1 is
UNDEFINED.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Shannon Zhao 3965c3ce75 arm64: KVM: Add access handler for PMSELR register
Since the reset value of PMSELR_EL0 is UNKNOWN, use reset_unknown for
its reset handler. When reading PMSELR, return the PMSELR.SEL field to
guest.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Shannon Zhao ab9468340d arm64: KVM: Add access handler for PMCR register
Add reset handler which gets host value of PMCR_EL0 and make writable
bits architecturally UNKNOWN except PMCR.E which is zero. Add an access
handler for PMCR.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Shannon Zhao 04fe472615 arm64: KVM: Define PMU data structure for each vcpu
Here we plan to support virtual PMU for guest by full software
emulation, so define some basic structs and functions preparing for
futher steps. Define struct kvm_pmc for performance monitor counter and
struct kvm_pmu for performance monitor unit for each vcpu. According to
ARMv8 spec, the PMU contains at most 32(ARMV8_PMU_MAX_COUNTERS)
counters.

Since this only supports ARM64 (or PMUv3), add a separate config symbol
for it.

Signed-off-by: Shannon Zhao <shannon.zhao@linaro.org>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Reviewed-by: Andrew Jones <drjones@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Marc Zyngier ad88213773 arm64: KVM: Add temporary kvm_perf_event.h
In order to merge the KVM/ARM PMU patches without creating a
conflict mess, let's have a temporary include file that won't
conflict with anything. Subsequent patches will clean that up.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Marc Zyngier 21a4179ce0 arm64: KVM: Move __cpu_init_stage2 after kvm_call_hyp
In order to ease the merge with the rest of the arm64 tree, move the
definition of __cpu_init_stage2() after what will be the new kvm_call_hyp.
Hopefully the resolution of the merge conflict will be obvious.

Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:19 +00:00
Marc Zyngier 6d50d54cd8 arm64: KVM: Move vgic-v2 and timer save/restore to virt/kvm/arm/hyp
We already have virt/kvm/arm/ containing timer and vgic stuff.
Add yet another subdirectory to contain the hyp-specific files
(timer and vgic again).

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier 13720a56ed arm64: KVM: Move kvm/hyp/hyp.h to include/asm/kvm_hyp.h
In order to be able to move code outside of kvm/hyp, we need to make
the global hyp.h file accessible from a standard location.

include/asm/kvm_hyp.h seems good enough.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier 1f364c8c48 arm64: VHE: Add support for running Linux in EL2 mode
With ARMv8.1 VHE, the architecture is able to (almost) transparently
run the kernel at EL2, despite being written for EL1.

This patch takes care of the "almost" part, mostly preventing the kernel
from dropping from EL2 to EL1, and setting up the HYP configuration.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier ae7e27fe68 arm64: hw_breakpoint: Allow EL2 breakpoints if running in HYP
With VHE, we place kernel {watch,break}-points at EL2 to get things
like kgdb and "perf -e mem:..." working.

This requires a bit of repainting in the low-level encore/decode,
but is otherwise pretty simple.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier d98ecdaca2 arm64: perf: Count EL2 events if the kernel is running in HYP
When the kernel is running in HYP (with VHE), it is necessary to
include EL2 events if the user requests counting kernel or
hypervisor events.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier 5f05a72aed arm64: KVM: Move most of the fault decoding to C
The fault decoding process (including computing the IPA in the case
of a permission fault) would be much better done in C code, as we
have a reasonable infrastructure to deal with the VHE/non-VHE
differences.

Let's move the whole thing to C, including the workaround for
erratum 834220, and just patch the odd ESR_EL2 access remaining
in hyp-entry.S.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier 253dcbd39a arm64: KVM: VHE: Add alternative panic handling
As the kernel fully runs in HYP when VHE is enabled, we can
directly branch to the kernel's panic() implementation, and
not perform an exception return.

Add the alternative code to deal with this.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:18 +00:00
Marc Zyngier 77cb2d9133 arm64: KVM: VHE: Add fpsimd enabling on guest access
Despite the fact that a VHE enabled kernel runs at EL2, it uses
CPACR_EL1 to trap FPSIMD access. Add the required alternative
code to re-enable guest FPSIMD access when it has trapped to
EL2.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier 5efe6de138 arm64: KVM: VHE: Use unified sysreg accessors for timer
Switch the timer code to the unified sysreg accessors.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier 68908bf789 arm64: KVM: VHE: Implement VHE activate/deactivate_traps
Running the kernel in HYP mode requires the HCR_E2H bit to be set
at all times, and the HCR_TGE bit to be set when running as a host
(and cleared when running as a guest). At the same time, the vector
 must be set to the current role of the kernel (either host or
hypervisor), and a couple of system registers differ between VHE
and non-VHE.

We implement these by using another set of alternate functions
that get dynamically patched.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier 328762247c arm64: KVM: VHE: Make __fpsimd_enabled VHE aware
As non-VHE and VHE have different ways to express the trapping of
FPSIMD registers to EL2, make __fpsimd_enabled a patchable predicate
and provide a VHE implementation.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier d1526e5efc arm64: KVM: VHE: Enable minimal sysreg save/restore
We're now in a position where we can introduce VHE's minimal
save/restore, which is limited to the handful of shared sysregs.

Add the required alternative function calls that result in a
"do nothing" call on VHE, and the normal save/restore for non-VHE.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier 094f8233c0 arm64: KVM: VHE: Use unified system register accessors
Use the recently introduced unified system register accessors for
those sysregs that behave differently depending on VHE being in
use or not.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier 9c6c356832 arm64: KVM: VHE: Split save/restore of registers shared between guest and host
A handful of system registers are still shared between host and guest,
even while using VHE (tpidr*_el[01] and actlr_el1).

Also, some of the vcpu state (sp_el0, PC and PSTATE) must be
save/restored on entry/exit, as they are used on the host as well.

In order to facilitate the introduction of a VHE-specific sysreg
save/restore, make move the access to these registers to their
own save/restore functions.

No functional change.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:17 +00:00
Marc Zyngier edef528dc4 arm64: KVM: VHE: Differenciate host/guest sysreg save/restore
With ARMv8, host and guest share the same system register file,
making the save/restore procedure completely symetrical.
With VHE, host and guest now have different requirements, as they
use different sysregs.

In order to prepare for this, add split sysreg save/restore functions
for both host and guest. No functional changes yet.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier 915ccd1dbf arm64: KVM: VHE: Introduce unified system register accessors
VHE brings its own bag of new system registers, or rather system
register accessors, as it define new ways to access both guest
and host system registers. For example, from the host:

- The host TCR_EL2 register is accessed using the TCR_EL1 accessor
- The guest TCR_EL1 register is accessed using the TCR_EL12 accessor

Obviously, this is confusing. A way to somehow reduce the complexity
of writing code for both ARMv8 and ARMv8.1 is to use a set of unified
accessors that will generate the right sysreg, depending on the mode
the CPU is running in. For example:

- read_sysreg_el1(tcr) will use TCR_EL1 on ARMv8, and TCR_EL12 on
  ARMv8.1 with VHE.
- read_sysreg_el2(tcr) will use TCR_EL2 on ARMv8, and TCR_EL1 on
  ARMv8.1 with VHE.

We end up with three sets of accessors ({read,write}_sysreg_el[012])
that can be directly used from C code. We take this opportunity to
also add the definition for the new VHE sysregs.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier cedbb8b78c arm64: KVM: VHE: Patch out kern_hyp_va
The kern_hyp_va macro is pretty meaninless with VHE, as there is
only one mapping - the kernel one.

In order to keep the code readable and efficient, use runtime
patching to replace the 'and' instruction used to compute the VA
with a 'nop'.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier b81125c791 arm64: KVM: VHE: Patch out use of HVC
With VHE, the host never issues an HVC instruction to get into the
KVM code, as we can simply branch there.

Use runtime code patching to simplify things a bit.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier d88701bea3 arm64: Add ARM64_HAS_VIRT_HOST_EXTN feature
Add a new ARM64_HAS_VIRT_HOST_EXTN features to indicate that the
CPU has the ARMv8.1 VHE capability.

This will be used to trigger kernel patching in KVM.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier 82deae0fc8 arm/arm64: Add new is_kernel_in_hyp_mode predicate
With ARMv8.1 VHE extension, it will be possible to run the kernel
at EL2 (aka HYP mode). In order for the kernel to easily find out
where it is running, add a new predicate that returns whether or
not the kernel is in HYP mode.

For completeness, the 32bit code also get such a predicate (always
returning false) so that code common to both architecture (timers,
KVM) can use it transparently.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:16 +00:00
Marc Zyngier 3a3604bc5e arm64: KVM: Switch to C-based stage2 init
There is no real need to leave the stage2 initialization as part
of the early HYP bootstrap, and we can easily postpone it to
the point where we can safely run C code.

This will help VHE, which doesn't need any of this bootstrap.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:15 +00:00
Marc Zyngier 57c841f131 arm/arm64: KVM: Handle out-of-RAM cache maintenance as a NOP
So far, our handling of cache maintenance by VA has been pretty
simple: Either the access is in the guest RAM and generates a S2
fault, which results in the page being mapped RW, or we go down
the io_mem_abort() path, and nuke the guest.

The first one is fine, but the second one is extremely weird.
Treating the CM as an I/O is wrong, and nothing in the ARM ARM
indicates that we should generate a fault for something that
cannot end-up in the cache anyway (even if the guest maps it,
it will keep on faulting at stage-2 for emulation).

So let's just skip this instruction, and let the guest get away
with it.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:15 +00:00
Marc Zyngier 42428525a9 ARM: KVM: Remove __kvm_hyp_code_start/__kvm_hyp_code_end
Now that we've unified the way we refer to the HYP text between
arm and arm64, drop __kvm_hyp_code_start/end, and just use the
__hyp_text_start/end symbols.

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:12 +00:00
Marc Zyngier 35a2491a62 arm/arm64: KVM: Add hook for C-based stage2 init
As we're about to move the stage2 init to C code, introduce some
C hooks that will later be populated with arch-specific implementations.

Reviewed-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 18:34:12 +00:00
Ard Biesheuvel 020d044f66 arm64: mm: treat memstart_addr as a signed quantity
Commit c031a4213c ("arm64: kaslr: randomize the linear region")
implements randomization of the linear region, by subtracting a random
multiple of PUD_SIZE from memstart_addr. This causes the virtual mapping
of system RAM to move upwards in the linear region, and at the same time
causes memstart_addr to assume a value which may be negative if the offset
of system RAM in the physical space is smaller than its offset relative to
PAGE_OFFSET in the virtual space.

Since memstart_addr is effectively an offset now, redefine its type as s64
so that expressions involving shifting or division preserve its sign.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-29 18:31:03 +00:00
Ard Biesheuvel a6e1f7273b arm64: mm: list kernel sections in order
In the boot log, instead of listing .init first, list .text, .rodata,
.init and .data in the same order they appear in memory

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-29 17:15:44 +00:00
Arnd Bergmann 9b1c124dd4 Second Round of Renesas ARM64 Based SoC DT Updates for v4.6
Updates for r8a7795/salvator-x
 * Enable USB2.0, and SDHI0 & 3
 * Add GIC-400 virtual interfaces
 * Add INTC-EX and L2 cache-controller nodes
 * Use fallback etheravb compatibility string
 * Use GIC_* defines where appropriate
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Merge tag 'renesas-arm64-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt64

Merge "Second Round of Renesas ARM64 Based SoC DT Updates for v4.6"
from Simon Horman:

Updates for r8a7795/salvator-x
* Enable USB2.0, and SDHI0 & 3
* Add GIC-400 virtual interfaces
* Add INTC-EX and L2 cache-controller nodes
* Use fallback etheravb compatibility string
* Use GIC_* defines where appropriate

* tag 'renesas-arm64-dt2-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
  arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
  arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodes
  arm64: dts: r8a7795: add usb2_phy device nodes
  arm64: dts: r8a7795: use fallback etheravb compatibility string
  arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3
  arm64: dts: r8a7795: Add SDHI support to dtsi
  arm64: dts: r8a7795: Add GIC-400 virtual interfaces
  arm64: dts: r8a7795: Add INTC-EX device node
  arm64: dts: r8a7795: Add CA53 L2 cache-controller node
  arm64: dts: r8a7795: Add missing properties to CA57 L2 cache node
  arm64: dts: r8a7795: use GIC_* defines
  arm64: dts: r8a7795: pmu: switch to Cortex specific device nodes
  arm64: dts: r8a7795: Add L2 cache-controller nodes
2016-02-29 16:20:44 +01:00
Arnd Bergmann e15cd209fc Renesas ARM64 Based SoC SoC Updates for v4.6
* Enable RENESAS_IRQC, and PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
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Merge tag 'renesas-arm64-soc-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/arm64

Merge "Renesas ARM64 Based SoC SoC Updates for v4.6" from Simon Horman:

* Enable RENESAS_IRQC, and PM and PM_GENERIC_DOMAINS for SoCs with PM Domains

* tag 'renesas-arm64-soc-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: renesas: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
  arm64: renesas: Enable RENESAS_IRQC
2016-02-29 16:19:00 +01:00
Arnd Bergmann 107adb57f2 Renesas ARM64 Based SoC Defconfig Updates for v4.6
* Enable Renesas R-Car Gen3 USB 2.0 phy driver
   which is used on the r8a7795/salvator-x
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Merge tag 'renesas-arm64-defconfig-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/arm64

Merge "Renesas ARM64 Based SoC Defconfig Updates for v4.6" from Simon Horman:

* Enable Renesas R-Car Gen3 USB 2.0 phy driver
  which is used on the r8a7795/salvator-x

* tag 'renesas-arm64-defconfig-for-v4.6' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
  arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
2016-02-29 16:17:30 +01:00
Michael S. Tsirkin 4cad67fca3 arm/arm64: KVM: Fix ioctl error handling
Calling return copy_to_user(...) in an ioctl will not
do the right thing if there's a pagefault:
copy_to_user returns the number of bytes not copied
in this case.

Fix up kvm to do
	return copy_to_user(...)) ?  -EFAULT : 0;

everywhere.

Cc: stable@vger.kernel.org
Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-29 09:56:40 +00:00
Daniel Cashman 5ef11c35ce mm: ASLR: use get_random_long()
Replace calls to get_random_int() followed by a cast to (unsigned long)
with calls to get_random_long().  Also address shifting bug which, in
case of x86 removed entropy mask for mmap_rnd_bits values > 31 bits.

Signed-off-by: Daniel Cashman <dcashman@android.com>
Acked-by: Kees Cook <keescook@chromium.org>
Cc: "Theodore Ts'o" <tytso@mit.edu>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Benjamin Herrenschmidt <benh@kernel.crashing.org>
Cc: Paul Mackerras <paulus@samba.org>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: David S. Miller <davem@davemloft.net>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Al Viro <viro@zeniv.linux.org.uk>
Cc: Nick Kralevich <nnk@google.com>
Cc: Jeff Vander Stoep <jeffv@google.com>
Cc: Mark Salyzyn <salyzyn@android.com>
Signed-off-by: Andrew Morton <akpm@linux-foundation.org>
Signed-off-by: Linus Torvalds <torvalds@linux-foundation.org>
2016-02-27 10:28:52 -08:00
Arnd Bergmann ebb7c983b5 Merge tag 'arm-soc/for-4.6/soc-arm64' of http://github.com/Broadcom/stblinux into next/arm64
Merge "Broadcom soc-arm64 changes for 4.6" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoC/platform changes:

- Anup, Ray and Dhanajay enable COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc
  SoCs to get the corresponding iProc-based drivers to be available and work

- Zi adds support for Broadcom's Vulcan processor by adding a reference
  board Device Tree file along with a config ARCH_VULCAN symbol

- Jayachandran C. adds the Broadcom implementor ID and part ID for the Vulcan
  processors

* tag 'arm-soc/for-4.6/soc-arm64' of http://github.com/Broadcom/stblinux:
  arm64: cputype info for Broadcom Vulcan
  arm64: Broadcom Vulcan support
  arm64: Select COMMON_CLK_IPROC, PINCTRL and GPIOLIB for iProc SoCs
2016-02-26 23:37:04 +01:00
Arnd Bergmann f9098036af Merge tag 'arm-soc/for-4.6/defconfig-arm64' of http://github.com/Broadcom/stblinux into next/arm64
Merge "Broadcom defconfig-arm64 changes for 4.6" from Florian Fainelli:

This pull request contains ARM64 defconfig changes for Broadcom SoCs:

- Jayachandran C enables the newly introduced Broadcom Vulcan SoC to the ARM64
  defconfig

* tag 'arm-soc/for-4.6/defconfig-arm64' of http://github.com/Broadcom/stblinux:
  arm64: defconfig: Add Broadcom Vulcan to defconfig
2016-02-26 23:33:12 +01:00
Arnd Bergmann 55da9c0852 Merge tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux into next/dt64
Merge "Broadcom devicetree-arm64 changes for 4.6" from Florian Fainelli:

This pull request contains Broadcom ARM64-based SoCs device tree changes:

- Anup adds additional nodes to the Broadcom Northstart 2 Device Trees: SDHCI
  (iProc-compatible), ARM SP804 timers, ARM SP805 watchdog

- Anup also adds a binding documentation for the ARM SP805 watchdog since there
  was not one in tree before

- Ray adds PCIE root complex nodes to the Northstar 2 Device Tree nodes, using
  the iProc-compatible binding

- Jayachandran C. adds binding documentation for the Broadcom Vulcan processors and
  reference platforms

* tag 'arm-soc/for-4.6/devicetree-arm64' of http://github.com/Broadcom/stblinux:
  dt-bindings: Add documentation for Broadcom Vulcan
  arm64: dts: Add PCIe0 and PCIe4 DT nodes for NS2
  arm64: dts: Add ARM SP805 watchdog DT node for NS2
  dt-bindings: watchdog: Add ARM SP805 DT bindings
  arm64: dts: Add ARM SP804 timer DT nodes for NS2
  arm64: dts: Add SDHCI DT node for NS2
2016-02-26 23:27:58 +01:00
Antoine Tenart 29de0e39aa arm64: dts: alpine: add the MSIX node in the Alpine v2 dtsi
Following the addition of the Alpine MSIX controller driver, add the
corresponding node in the Alpine v2 device tree.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26 22:58:10 +01:00
Antoine Tenart 1c3554fa94 arm64: dts: add the Alpine v2 EVP
This patch adds the initial support for the Alpine v2 EVP board from
Annapurna Labs (Amazon).

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Barak Wasserstrom <barak@annapurnalabs.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26 22:58:03 +01:00
Antoine Tenart 93df6d16af arm64: alpine: select the Alpine MSI controller driver
Select the Alpine MSI controller driver when using an Alpine platform.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Signed-off-by: Tsahee Zidenberg <tsahee@annapurnalabs.com>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26 22:56:48 +01:00
Antoine Tenart 476cfc05f3 arm64: defconfig: enable the Alpine family
Enable the Alpine SoC family in the arm64 defconfig.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26 22:56:31 +01:00
Antoine Tenart e2f0abaf45 arm64: add Alpine SoC family
This patch introduces ARCH_ALPINE to add the support of the Alpine SoC
family for the arm64 architecture.

Signed-off-by: Antoine Tenart <antoine.tenart@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Arnd Bergmann <arnd@arndb.de>
2016-02-26 22:56:22 +01:00
Arnd Bergmann 56c8b00fdb arm: Xilinx ZynqMP dt patches for v4.6
- Extract clock information from EP108
 - Sort GPIO node
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Merge tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx into next/dt64

Merge "ARM: Xilinx ZynqMP dt patches for v4.6" from Michal Simek:

- Extract clock information from EP108
- Sort GPIO node

* tag 'zynqmp-dt-for-4.6' of https://github.com/Xilinx/linux-xlnx:
  ARM64: zynqmp: Extract clock information from EP108
  ARM64: zynqmp: Keep gpio node alphabetically sorted
2016-02-26 22:51:16 +01:00
Arnd Bergmann f6c7017c60 Add nor-flash to mt8173 SoC.
Add efuse device to mt1873 SoC.
 Fix power-domain issue mt8173-evb which uses older chip revision.
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Merge tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek into next/dt64

Merge "ARM: mediatek: dts updates for v4.6" from Matthias Brugger:

Add nor-flash to mt8173 SoC.
Add efuse device to mt8173 SoC.
Fix power-domain issue mt8173-evb which uses older chip revision.

* tag 'v4.5-next-dts64' of https://github.com/mbgg/linux-mediatek:
  ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue
  dts: arm64: Add EFUSE device node
  arm64: dts: mt8173: Add nor flash node
2016-02-26 22:29:42 +01:00
Ard Biesheuvel 5be8b70af1 arm64: lse: deal with clobbered IP registers after branch via PLT
The LSE atomics implementation uses runtime patching to patch in calls
to out of line non-LSE atomics implementations on cores that lack hardware
support for LSE. To avoid paying the overhead cost of a function call even
if no call ends up being made, the bl instruction is kept invisible to the
compiler, and the out of line implementations preserve all registers, not
just the ones that they are required to preserve as per the AAPCS64.

However, commit fd045f6cd9 ("arm64: add support for module PLTs") added
support for routing branch instructions via veneers if the branch target
offset exceeds the range of the ordinary relative branch instructions.
Since this deals with jump and call instructions that are exposed to ELF
relocations, the PLT code uses x16 to hold the address of the branch target
when it performs an indirect branch-to-register, something which is
explicitly allowed by the AAPCS64 (and ordinary compiler generated code
does not expect register x16 or x17 to retain their values across a bl
instruction).

Since the lse runtime patched bl instructions don't adhere to the AAPCS64,
they don't deal with this clobbering of registers x16 and x17. So add them
to the clobber list of the asm() statements that perform the call
instructions, and drop x16 and x17 from the list of registers that are
callee saved in the out of line non-LSE implementations.

In addition, since we have given these functions two scratch registers,
they no longer need to stack/unstack temp registers.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[will: factored clobber list into #define, updated Makefile comment]
Signed-off-by: Will Deacon <will.deacon@arm.com>

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 18:35:02 +00:00
Kefeng Wang cc30e6b95c arm64: mm: dump: Use VA_START directly instead of private LOWEST_ADDR
Use VA_START macro in asm/memory.h instead of private LOWEST_ADDR
definition in dump.c.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 18:31:41 +00:00
Will Deacon f993318bfe arm64: kconfig: add submenu for 8.2 architectural features
UAO is a feature of ARMv8.2, so add a submenu like we have for 8.1.

Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 18:12:35 +00:00
Ard Biesheuvel dfd55ad85e arm64: vmemmap: use virtual projection of linear region
Commit dd006da216 ("arm64: mm: increase VA range of identity map") made
some changes to the memory mapping code to allow physical memory to reside
at an offset that exceeds the size of the virtual mapping.

However, since the size of the vmemmap area is proportional to the size of
the VA area, but it is populated relative to the physical space, we may
end up with the struct page array being mapped outside of the vmemmap
region. For instance, on my Seattle A0 box, I can see the following output
in the dmesg log.

   vmemmap : 0xffffffbdc0000000 - 0xffffffbfc0000000   (     8 GB maximum)
             0xffffffbfc0000000 - 0xffffffbfd0000000   (   256 MB actual)

We can fix this by deciding that the vmemmap region is not a projection of
the physical space, but of the virtual space above PAGE_OFFSET, i.e., the
linear region. This way, we are guaranteed that the vmemmap region is of
sufficient size, and we can even reduce the size by half.

Cc: <stable@vger.kernel.org>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-26 17:59:04 +00:00
Lorenzo Pieralisi c1e4659ba8 arm64: kernel: acpi: fix ioremap in ACPI parking protocol cpu_postboot
When secondary cpus are booted through the ACPI parking protocol, the
booted cpu should check that FW has correctly cleared its mailbox entry
point value to make sure the boot process was correctly executed.
The entry point check is carried in the cpu_ops->cpu_postboot method, that
is executed by secondary cpus when entering the kernel with irqs disabled.

The ACPI parking protocol cpu_ops maps/unmaps the mailboxes on the
primary CPU to trigger secondary boot in the cpu_ops->cpu_boot method
and on secondary processors to carry out FW checks on the booted CPU
to verify the boot protocol was successfully executed in the
cpu_ops->cpu_postboot method.

Therefore, the cpu_ops->cpu_postboot method is forced to ioremap/unmap the
mailboxes, which is wrong in that ioremap cannot be safely be carried out
with irqs disabled.

To fix this issue, this patch reshuffles the code so that the mailboxes
are still mapped after the boot processor executes the cpu_ops->cpu_boot
method for a given cpu, and the VA at which a mailbox is mapped for a given
cpu is stashed in the per-cpu data struct so that secondary cpus can
retrieve them in the cpu_ops->cpu_postboot and complete the required
FW checks.

Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Reported-by: Itaru Kitayama <itaru.kitayama@riken.jp>
Tested-by: Loc Ho <lho@apm.com>
Tested-by: Itaru Kitayama <itaru.kitayama@riken.jp>
Cc: Will Deacon <will.deacon@arm.com>
Cc: Hanjun Guo <hanjun.guo@linaro.org>
Cc: Loc Ho <lho@apm.com>
Cc: Itaru Kitayama <itaru.kitayama@riken.jp>
Cc: Sudeep Holla <sudeep.holla@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mark Salter <msalter@redhat.com>
Cc: Al Stone <ahs3@redhat.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 15:39:52 +00:00
Suzuki K Poulose bf50061844 arm64: Add support for Half precision floating point
ARMv8.2 extensions [1] include an optional feature, which supports
half precision(16bit) floating point/asimd data processing
instructions. This patch adds support for detecting and exposing
the same to the userspace via HWCAPs

[1] https://community.arm.com/groups/processors/blog/2016/01/05/armv8-a-architecture-evolution

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 15:37:01 +00:00
Mark Rutland 3eca86e75e arm64: Remove fixmap include fragility
The asm-generic fixmap.h depends on each architecture's fixmap.h to pull
in the definition of PAGE_KERNEL_RO, if this exists. In the absence of
this, FIXMAP_PAGE_RO will not be defined. In mm/early_ioremap.c the
definition of early_memremap_ro is predicated on FIXMAP_PAGE_RO being
defined.

Currently, the arm64 fixmap.h doesn't include pgtable.h for the
definition of PAGE_KERNEL_RO, and as a knock-on effect early_memremap_ro
is not always defined, leading to link-time failures when it is used.
This has been observed with defconfig on next-20160226.

Unfortunately, as pgtable.h includes fixmap.h, adding the include
introduces a circular dependency, which is just as fragile.

Instead, this patch factors out PAGE_KERNEL_RO and other prot
definitions into a new pgtable-prot header which can be included by poth
pgtable.h and fixmap.h, avoiding the  circular dependency, and ensuring
that early_memremap_ro is alwyas defined where it is used.

Signed-off-by: Mark Rutland <mark.rutland@arm.com>
Reported-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 15:22:53 +00:00
Andrew Pinski 104a0c02e8 arm64: Add workaround for Cavium erratum 27456
On ThunderX T88 pass 1.x through 2.1 parts, broadcast TLBI
instructions may cause the icache to become corrupted if it contains
data for a non-current ASID.

This patch implements the workaround (which invalidates the local
icache when switching the mm) by using code patching.

Signed-off-by: Andrew Pinski <apinski@cavium.com>
Signed-off-by: David Daney <david.daney@cavium.com>
Reviewed-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 15:14:27 +00:00
Jeremy Linton 2f39b5f91e arm64: mm: Mark .rodata as RO
Currently the .rodata section is actually still executable when DEBUG_RODATA
is enabled. This changes that so the .rodata is actually read only, no execute.
It also adds the .rodata section to the mem_init banner.

Signed-off-by: Jeremy Linton <jeremy.linton@arm.com>
Reviewed-by: Kees Cook <keescook@chromium.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
[catalin.marinas@arm.com: added vm_struct vmlinux_rodata in map_kernel()]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 15:08:04 +00:00
Thomas Petazzoni b5ebfad8df arm64: dts: marvell: re-order Device Tree nodes for Armada AP806
The DT nodes representing the XOR engines were not placed at the
proper location to comply with the requirement of ordering DT nodes by
their unit address. This commit fixes this mistake.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26 15:17:31 +01:00
Thomas Petazzoni d2b78fb6f2 arm64: dts: marvell: update Armada AP806 clock description
Following the review from the DT maintainers, the DT binding for the
clocks has changed, and we now use a DFX server node exposing a
syscon, with the clock nodes being subnodes of the DFX server
node. This commit therefore updates the AP806 Device Tree file to use
this new DT binding.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26 15:17:30 +01:00
Thomas Petazzoni ec7e5a569b arm64: dts: marvell: add Device Tree files for Armada 7K/8K
This commit adds the base Device Tree files for the Armada 7K and 8K
SoCs, as well as the Armada 8040 DB board.

The Armada 7020, 7040 (7K family) and 8020, 8040 (8K family) are
composed of:

 - An AP806 block that contains the CPU core and a few basic
   peripherals. The AP806 is available in dual core configurations
   (used in 7020 and 8020) and quad core configurations (used in 8020
   and 8040).

 - One or two CP110 blocks that contain all the high-speed interfaces
   (SATA, PCIe, Ethernet, etc.). The 7K family chips have one CP110,
   and the 8K family chips have two CP110, giving them twice the
   number of HW interfaces.

In order to represent this from a Device Tree point of view, this
commit creates the following hierarchy:

 * armada-ap806.dtsi - definitions common to dual/quad ap806
   * armada-ap806-dual.dtsi - description of the two CPUs
     * armada-7020.dtsi - description of the 7020 SoC
     * armada-8020.dtsi - description of the 8020 SoC
   * armada-ap806-quad.dtsi - description of the four CPUs
     * armada-7040.dtsi - description of the 7040 SoC
       * armada-7040-db.dts - description of the 7040 board
     * armada-8040.dtsi - description of the 8040 SoC

The CP110 blocks are not described yet, and will be part of future
patch series.

[gregory.clement@free-electrons.com: Fix commit title by adding ' dts:']
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-26 15:17:16 +01:00
Miles Chen b7dc8d16e7 arm64/mm: remove unnecessary boundary check
Remove the unnecessary boundary check since there is a huge
gap between user and kernel address that they would never overlap.
(arm64 does not have enough levels of page tables to cover 64-bit
virtual address)

See Documentation/arm64/memory.txt

Signed-off-by: Miles Chen <miles.chen@mediatek.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-26 13:39:53 +00:00
Linus Torvalds 73056bbc68 KVM/ARM fixes:
- Fix per-vcpu vgic bitmap allocation
 - Do not give copy random memory on MMIO read
 - Fix GICv3 APR register restore order
 
 KVM/x86 fixes:
 - Fix ubsan warning
 - Fix hardware breakpoints in a guest vs. preempt notifiers
 - Fix Hurd
 
 Generic:
 - use __GFP_NOWARN together with GFP_NOWAIT
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Merge tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm

Pull KVM fixes from Paolo Bonzini:
 "KVM/ARM fixes:
   - Fix per-vcpu vgic bitmap allocation
   - Do not give copy random memory on MMIO read
   - Fix GICv3 APR register restore order

  KVM/x86 fixes:
   - Fix ubsan warning
   - Fix hardware breakpoints in a guest vs. preempt notifiers
   - Fix Hurd

  Generic:
   - use __GFP_NOWARN together with GFP_NOWAIT"

* tag 'for-linus' of git://git.kernel.org/pub/scm/virt/kvm/kvm:
  KVM: x86: MMU: fix ubsan index-out-of-range warning
  arm64: KVM: vgic-v3: Restore ICH_APR0Rn_EL2 before ICH_APR1Rn_EL2
  KVM: async_pf: do not warn on page allocation failures
  KVM: x86: fix conversion of addresses to linear in 32-bit protected mode
  KVM: x86: fix missed hardware breakpoints
  arm/arm64: KVM: Feed initialized memory to MMIO accesses
  KVM: arm/arm64: vgic: Ensure bitmaps are long enough
2016-02-25 19:53:54 -08:00
Duc Dang 406f594054 arm64: dts: apm: Add DT node for X-Gene v2 SLIMpro Mailbox I2C Driver
Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v2 platforms.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:14:04 -08:00
Duc Dang e99fe22661 arm64: dts: apm: Mailbox device tree node for APM X-Gene v2 platform.
Add mailbox device tree node for APM X-Gene v2 platform.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:14:03 -08:00
Duc Dang 778b5cbc0d arm64: dts: apm: Add DT node for X-Gene v1 SLIMpro Mailbox I2C Driver
Add DT node to enable SLIMpro Mailbox I2C Driver for
X-Gene v1 platforms.

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:14:02 -08:00
Duc Dang b0e4563c2f arm64: dts: apm: mailbox device tree node for APM X-Gene platform.
Mailbox device tree node for APM X-Gene platform.

Signed-off-by: Feng Kan <fkan@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
Signed-off-by: Jassi Brar <jaswinder.singh@linaro.org>
2016-02-25 17:14:01 -08:00
Duc Dang edf21f2710 arm64: dts: apm: Update GPIO to control power-off on X-Gene v2 platforms
This patch updates gpio-keys node that supports power-off for
X-Gene v2 Merlin board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).

Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:14:00 -08:00
Duc Dang b8a4ee33d9 arm64: dts: apm: Update GPIO standby controller DT node for X-Gene v2 platforms
xgene-gpio-sb driver now supports configuring some GPIO pins
as interrupt pins. This patch adds the required fields for GPIO
standby controller DT node of X-Gene v2 platform to work with
this new driver change.

Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:13:59 -08:00
Duc Dang 310b1406a5 arm64: dts: apm: Update GPIO to control power-off on X-Gene v1 platforms
This patch updates gpio-keys node that supports power-off for
X-Gene v1 Mustang board to adapt with new changes in xgene-gpio-sb
driver (to support configuring some GPIO pins as interrupt pins).

Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 17:13:58 -08:00
Alim Akhtar 617fe7196d arm64: defconfig: Enable exynos thermal config
This patch enables Exynos thermal and related configs for the
TMU found on Exynos7 SoC. This also enables thermal emulation
mode to test trip points.

Signed-off-by: Alim Akhtar <alim.akhtar@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
2016-02-26 09:32:45 +09:00
Yoshihiro Shimoda 474efcae3b arm64: dts: salvator-x: enable USB 2.0 Host of channel 1 and 2
We should set SW15 to pin 2-3 side on the board before we use CN9
as USB host or peripheral.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:32 +09:00
Yoshihiro Shimoda e24250c008 arm64: dts: salvator-x: enable usb2_phy of channel 1 and 2
This board has a MAX3355 chip. However, we cannot use the extcon/max3355
driver because the ID pin doesn't connect to a gpio pin (in other words,
it connects to the SoC specific pin).
And, the phy-rcar-gen3-usb2 driver cannot handle such a chip for now.
So, this patch enables usb2_phy of channel 1 and 2.

Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:32 +09:00
Yoshihiro Shimoda a2bcdc2876 arm64: dts: r8a7795: add USB2.0 Host (EHCI/OHCI) device nodes
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:31 +09:00
Yoshihiro Shimoda 5923bb5227 arm64: dts: r8a7795: add usb2_phy device nodes
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:31 +09:00
Simon Horman 2b953ccd0e arm64: dts: r8a7795: use fallback etheravb compatibility string
Use recently added fallback compatibility string in r8a7795 device tree.

Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
2016-02-26 08:55:30 +09:00
Ai Kyuse 1c0e7b9a00 arm64: dts: r8a7795: salvator-x: enable SDHI0 & 3
Add the exposed SD card slots. The on-board eMMC needs to wait until we
fixed the 8bit support.

Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:29 +09:00
Ai Kyuse d9d67010e0 arm64: dts: r8a7795: Add SDHI support to dtsi
Signed-off-by: Ai Kyuse <ai.kyuse.uw@renesas.com>
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
[wsa: squashed some fixes and added mmc-caps]
Signed-off-by: Wolfram Sang <wsa+renesas@sang-engineering.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-26 08:55:18 +09:00
Srinivas Kandagatla a7b2466cea arm64: dts: qcom: fix usb digital voltage levels
This patch updates the digital voltage levels from corner values to
microvolts as we are going to use s1 regulator directly for vddcx
instead of s1_corner.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:08 -06:00
Srinivas Kandagatla b1cda82b93 arm64: dts: qcom: apq8016-sbc: enable lpass on DB410c
This patch enables the lpass on DB410C. LPASS is used as cpu dai for
both analog and digital audio.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:08 -06:00
Srinivas Kandagatla 3761a3618f arm64: dts: qcom: add lpass node
This patch adds lpass node to the SOC.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:07 -06:00
Srinivas Kandagatla 143bb9ad85 arm64: dts: qcom: add audio pinctrls
This patch adds pinctrls required for digital and analog audio via lpass.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:07 -06:00
Srinivas Kandagatla dd8cdc9e1d arm64: dts: qcom: apq8016-sbc: add usb support
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:07 -06:00
Srinivas Kandagatla 2a0bc8104e arm64: dts: qcom: add manual pullup setting to otg.
This patch adds manual pull up setting for usb otg indicating that the
vbus is vbus is not routed to USB controller/phy therefore enables
pull-up explicitly before starting controller.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
2016-02-25 16:50:07 -06:00
Quan Nguyen 47f134a2d5 arm64: dts: apm: Update X-Gene standby GPIO controller DTS entries
Update APM X-Gene standby GPIO controller DTS entries to enable it
as interrupt controller.

[dhdang: update patch subject]
Signed-off-by: Y Vo <yvo@apm.com>
Signed-off-by: Quan Nguyen <qnguyen@apm.com>
Reviewed-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 14:40:17 -08:00
Loc Ho 8943f5530d arm64: dts: apm: Update Merlin DT PCP PLL clock node for v2 hardware
Update Merlin DT PCP PLL clock node to reflect compatible
string change to reflect v2 hardware.

[dhdang: change patch subject]
Signed-off-by: Loc Ho <lho@apm.com>
Signed-off-by: Duc Dang <dhdang@apm.com>
2016-02-25 14:38:18 -08:00
Andre Przywara 22b0898e83 arm64: add defconfig options for Allwinner SoCs
With the Allwinner platform now supported, enable it in the defconfig
and add some options to give some decent out-of-the-box experience on
those SoCs.

Signed-off-by: Andre Przywara <andre.przywara@arm.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
2016-02-25 10:51:50 -08:00
Catalin Marinas cac4b8cdf5 arm64: Fix building error with 16KB pages and 36-bit VA
In such configuration, Linux uses only two pages of page tables and
__pud_populate() should not be used. However, the BUILD_BUG() triggers
since pud_sect() is still defined and the compiler cannot eliminate such
code, even though at run-time it should not be triggered. This patch
extends the #ifdef ARM64_64K_PAGES condition for pud_sect to include
PGTABLE_LEVELS < 3.

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 16:01:26 +00:00
Yong Wu 5ff6b3a6d3 dts: mt8173: Add iommu/smi nodes for mt8173
This patch add the iommu/larbs nodes for mt8173

Signed-off-by: Yong Wu <yong.wu@mediatek.com>
Reviewed-by: Daniel Kurtz <djkurtz@chromium.org>
Signed-off-by: Joerg Roedel <jroedel@suse.de>
2016-02-25 16:49:09 +01:00
Kefeng Wang c966f0521d arm64: defconfig: Enable DesignWare APB GPIO controller
The Synopsys DesignWare APB GPIO controller is used by several vender's socs,
like apm/marvell/altera/hisilicon, enable it by default.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:21:26 +08:00
Kefeng Wang 82a14b1e95 arm64: dts: hip05: Append power button node for D02 board
This patch adds poweroff button device node to support
poweroff feature on hip05 d02 board.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang 8f41d122bf arm64: dts: hip05: Append gpio nodes
There are two dw GPIO controllers in hip05 peri sub, this patch
adds the corresponding device tree nodes.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang abf9c25d55 arm64: dts: hip05: Append all gicv3 ITS entries
There are four subsystems in hip05 soc, peri/m3/pcie/dsa,
each subsystem has one its, append them under gicv3 node.

They will be used by hisilicon mbigen.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang 6897db62bb arm64: dts: hip05: Use Cortex specific device node for pmu
Instead of using the generic armv8-pmuv3 compatibility, use
the more specific Cortex A57 compatibility.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Kefeng Wang dbb58d0f79 arm64: dts: hip05: Add L2 cache topology
The Hip05 SoC has four L2 cache for all 16 CPUs, every four cpus
share one L2 cache, add them to the dtsi file so that the cache
hierarchy can be probed.

Signed-off-by: Kefeng Wang <wangkefeng.wang@huawei.com>
Signed-off-by: Wei Xu <xuwei5@hisilicon.com>
2016-02-25 21:15:58 +08:00
Michal Simek 5087bccb2f ARM64: zynqmp: Extract clock information from EP108
Extract clocks and put it specific file to help with platform
autogeneration.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25 14:01:03 +01:00
Michal Simek 72e5df437b ARM64: zynqmp: Keep gpio node alphabetically sorted
No functional change.

Signed-off-by: Michal Simek <michal.simek@xilinx.com>
2016-02-25 14:00:50 +01:00
Suzuki K Poulose 28c5dcb22f arm64: Rename cpuid_feature field extract routines
Now that we have a clear understanding of the sign of a feature,
rename the routines to reflect the sign, so that it is not misused.
The cpuid_feature_extract_field() now accepts a 'sign' parameter.

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:08 +00:00
Suzuki K Poulose ff96f7bc7b arm64: capabilities: Handle sign of the feature bit
Use the appropriate accessor for the feature bit by keeping
track of the sign of the feature

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:07 +00:00
Suzuki K Poulose 0710cfdb8d arm64: cpufeature: Fix the sign of feature bits
There is a confusion on whether the values of a feature are signed
or not in ARM. This is not clearly mentioned in the ARM ARM either.
We have dealt most of the bits as signed so far, and marked the
rest as unsigned explicitly. This fixed in ARM ARM and will be rolled
out soon.

Here is the criteria in a nutshell:

1) The fields, which are either signed or unsigned, use increasing
   numerical values to indicate an increase in functionality. Thus, if a value
   of 0x1 indicates the presence of some instructions, then the 0x2 value will
   indicate the presence of those instructions plus some additional instructions
   or functionality.

2) For ID field values where the value 0x0 defines that a feature is not present,
   the number is an unsigned value.

3) For some features where the feature was made optional or removed after the
   start of the definition of the architecture, the value 0x0 is used to
   indicate the presence of a feature, and 0xF indicates the absence of the
   feature. In these cases, the fields are, in effect, holding signed values.

So with these rules applied, we have only the following fields which are signed and
the rest are unsigned.

 a) ID_AA64PFR0_EL1: {FP, ASIMD}
 b) ID_AA64MMFR0_EL1: {TGran4K, TGran64K}
 c) ID_AA64DFR0_EL1: PMUVer (0xf - PMUv3 not implemented)
 d) ID_DFR0_EL1: PerfMon
 e) ID_MMFR0_EL1: {InnerShr, OuterShr}

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:07 +00:00
Suzuki K Poulose e53435031a arm64: cpufeature: Correct feature register tables
Correct the feature bit entries for :
  ID_DFR0
  ID_MMFR0

to fix the default safe value for some of the bits.

Signed-off-by: Suzuki K. Poulose <suzuki.poulose@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:07 +00:00
Suzuki K Poulose 13f417f3b8 arm64: Ensure the secondary CPUs have safe ASIDBits size
Adds a hook for checking whether a secondary CPU has the
features used already by the kernel during early boot, based
on the boot CPU and plugs in the check for ASID size.

The ID_AA64MMFR0_EL1:ASIDBits determines the size of the mm context
id and is used in the early boot to make decisions. The value is
picked up from the Boot CPU and cannot be delayed until other CPUs
are up. If a secondary CPU has a smaller size than that of the Boot
CPU, things will break horribly and the usual SANITY check is not good
enough to prevent the system from crashing. So, crash the system with
enough information.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:06 +00:00
Suzuki K Poulose 038dc9c66a arm64: Add helper for extracting ASIDBits
Add a helper to extract ASIDBits on the current cpu

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:06 +00:00
Suzuki K Poulose fd9c2790cb arm64: Enable CPU capability verification unconditionally
We verify the capabilities of the secondary CPUs only when
hotplug is enabled. The boot time activated CPUs do not
go through the verification by checking whether the system
wide capabilities were initialised or not.

This patch removes the capability check dependency on CONFIG_HOTPLUG_CPU,
to make sure that all the secondary CPUs go through the check.
The boot time activated CPUs will still skip the system wide
capability check. The plan is to hook in a check for CPU features
used by the kernel at early boot up, based on the Boot CPU values.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:33:06 +00:00
Suzuki K Poulose bb9052744f arm64: Handle early CPU boot failures
A secondary CPU could fail to come online due to insufficient
capabilities and could simply die or loop in the kernel.
e.g, a CPU with no support for the selected kernel PAGE_SIZE
loops in kernel with MMU turned off.
or a hotplugged CPU which doesn't have one of the advertised
system capability will die during the activation.

There is no way to synchronise the status of the failing CPU
back to the master. This patch solves the issue by adding a
field to the secondary_data which can be updated by the failing
CPU. If the secondary CPU fails even before turning the MMU on,
it updates the status in a special variable reserved in the head.txt
section to make sure that the update can be cache invalidated safely
without possible sharing of cache write back granule.

Here are the possible states :

 -1. CPU_MMU_OFF - Initial value set by the master CPU, this value
indicates that the CPU could not turn the MMU on, hence the status
could not be reliably updated in the secondary_data. Instead, the
CPU has updated the status @ __early_cpu_boot_status.

 0. CPU_BOOT_SUCCESS - CPU has booted successfully.

 1. CPU_KILL_ME - CPU has invoked cpu_ops->die, indicating the
master CPU to synchronise by issuing a cpu_ops->cpu_kill.

 2. CPU_STUCK_IN_KERNEL - CPU couldn't invoke die(), instead is
looping in the kernel. This information could be used by say,
kexec to check if it is really safe to do a kexec reboot.

 3. CPU_PANIC_KERNEL - CPU detected some serious issues which
requires kernel to crash immediately. The secondary CPU cannot
call panic() until it has initialised the GIC. This flag can
be used to instruct the master to do so.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
[catalin.marinas@arm.com: conflict resolution]
[catalin.marinas@arm.com: converted "status" from int to long]
[catalin.marinas@arm.com: updated update_early_cpu_boot_status to use str_l]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-25 10:32:23 +00:00
Paolo Bonzini 0fb00d326f KVM/ARM fixes for 4.5-rc6
- Fix per-vcpu vgic bitmap allocation
 - Do not give copy random memory on MMIO read
 - Fix GICv3 APR register restore order
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Merge tag 'kvm-arm-for-4.5-rc6' of git://git.kernel.org/pub/scm/linux/kernel/git/kvmarm/kvmarm into kvm-master

KVM/ARM fixes for 4.5-rc6

- Fix per-vcpu vgic bitmap allocation
- Do not give copy random memory on MMIO read
- Fix GICv3 APR register restore order
2016-02-25 09:53:55 +01:00
Olof Johansson 072201624a mvebu dt64 for 4.6 (part 1)
Device tree part of the Armada 3700 support:
 - binding for the Armada 3700 SoCs
 - device tree files for the SoCs and a board
 - tidy up the Marvell related files
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Merge tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu into next/dt64

mvebu dt64 for 4.6 (part 1)

Device tree part of the Armada 3700 support:
- binding for the Armada 3700 SoCs
- device tree files for the SoCs and a board
- tidy up the Marvell related files

* tag 'mvebu-dt64-4.6-1' of git://git.infradead.org/linux-mvebu:
  arm64: dts: add the Marvell Armada 3700 family and a development board
  devicetree: bindings: add DT binding for the Marvell Armada 3700 SoC family
  Documentation: dt: Tidy up the Marvell related files
  Documentation: dt-bindings: Add a new compatible for the Armada 3700

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 16:49:05 -08:00
Olof Johansson c74f162e84 mvebu arm64 for 4.6 (part 1)
Non dt part of the Armada 3700 support:
 - Kconfig update
 - defconfig update
 - documentation update (including MAINTAINERS:)
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Merge tag 'mvebu-arm64-4.6-1' of git://git.infradead.org/linux-mvebu into next/arm64

mvebu arm64 for 4.6 (part 1)

Non dt part of the Armada 3700 support:
- Kconfig update
- defconfig update
- documentation update (including MAINTAINERS:)

* tag 'mvebu-arm64-4.6-1' of git://git.infradead.org/linux-mvebu:
  arm64: defconfig: enable Armada 3700 related config
  Documentation: arm: update supported Marvell EBU processors
  MAINTAINERS: Extend dts entry for ARM64 mvebu files
  arm64: add mvebu architecture entry
  irqchip/armada-370-xp: Do not enable it by default when ARCH_MVEBU is selected
  ARM: mvebu: Use the ARMADA_370_XP_IRQ option
  irqchip/armada-370-xp: Allow allocation of multiple MSIs
  irqchip/armada-370-xp: Use shorter names for irq_chip
  irqchip/armada-370-xp: Use PCI_MSI_DOORBELL_START where appropriate
  irqchip/armada-370-xp: Use the generic MSI infrastructure
  irqchip/armada-370-xp: Add Kconfig option for the driver

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 16:46:14 -08:00
Minghuan Lian f21a3c7d57 dts/ls2080a: Update PCIe compatible
The patch adds LS2085a to PCIe compatible to fix the compatibility
issue when using firmware with LS2085a compatible property.

Signed-off-by: Minghuan Lian <minghuan.lian@nxp.com>
Signed-off-by: Mingkai Hu <mingkai.hu@nxp.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 16:40:41 -08:00
Suravee Suthikulpanit 18f94513ea arm64: dts: amd: Fix-up for ccn504 and kcs nodes
This is a fix-up patch based on the review comment from
Arnd regarding:
    * fix ccn504 address in the node name
    * remove kcs interrupt-name

Signed-off-by: Brijesh Singh <brijesh.singh@amd.com>
Signed-off-by: Suravee Suthikulpanit <suravee.suthikulpanit@amd.com>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 14:02:19 -08:00
Olof Johansson 4375acc3e2 Define the tuning-related mmc clocks and move from
gpio-key,wakeup to the more generic wakeup-source property.
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Merge tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt64

Define the tuning-related mmc clocks and move from
gpio-key,wakeup to the more generic wakeup-source property.

* tag 'v4.6-rockchip-dts64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: dts: rockchip: replace gpio-key,wakeup with wakeup-source property
  arm64: dts: rockchip: add rk3368 tuning clk for emmc and sdmmc

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 13:51:45 -08:00
Olof Johansson 8f4f2721dd Enable the rockchip-specific timers on arm64 rockchip platforms.
The driver got reworked to not use arm32-specific dsb calls in
 4.5-rc1, so now we can safely enable it.
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Merge tag 'v4.6-rockchip-soc64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/arm64

Enable the rockchip-specific timers on arm64 rockchip platforms.
The driver got reworked to not use arm32-specific dsb calls in
4.5-rc1, so now we can safely enable it.

* tag 'v4.6-rockchip-soc64-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip:
  arm64: Enable the timer on Rockchip architecture

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 13:51:08 -08:00
Olof Johansson 7fa12181b0 Few updates for ARM VExpress/Juno platforms
1. GICv3 support on Foundation models
 
 2. Support for Juno R2 board
 
 3. Support for ARM HDLCD on all Juno platforms
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Merge tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux into next/dt

Few updates for ARM VExpress/Juno platforms

1. GICv3 support on Foundation models

2. Support for Juno R2 board

3. Support for ARM HDLCD on all Juno platforms

* tag 'vexpress-for-v4.6/dt-updates' of git://git.kernel.org/pub/scm/linux/kernel/git/sudeep.holla/linux:
  arm64: dts: Add HDLCD support on Juno platforms
  Documentation: drm: Add DT bindings for ARM HDLCD
  arm64: dts: Add support for Juno r2 board
  arm64: dts: move juno pcie-controller to base file
  arm64: dts: add .dts for GICv3 Foundation model
  arm64: dts: split Foundation model dts to put the GIC separately
  arm64: dts: Foundation model: increase GICC region to allow EOImode=1
  arm64: dts: prepare foundation-v8.dts to cope with GICv3

Signed-off-by: Olof Johansson <olof@lixom.net>
2016-02-24 13:40:18 -08:00
Marc Zyngier fd451b90e7 arm64: KVM: vgic-v3: Restore ICH_APR0Rn_EL2 before ICH_APR1Rn_EL2
The GICv3 architecture spec says:

Writing to the active priority registers in any order other than
the following order will result in UNPREDICTABLE behavior:
- ICH_AP0R<n>_EL2.
- ICH_AP1R<n>_EL2.

So let's not pointlessly go against the rule...

Acked-by: Christoffer Dall <christoffer.dall@linaro.org>
Signed-off-by: Marc Zyngier <marc.zyngier@arm.com>
2016-02-24 17:25:58 +00:00
Suzuki K Poulose fce6361fe9 arm64: Move cpu_die_early to smp.c
This patch moves cpu_die_early to smp.c, where it fits better.
No functional changes, except for adding the necessary checks
for CONFIG_HOTPLUG_CPU.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 17:17:45 +00:00
Suzuki K Poulose ee02a15919 arm64: Introduce cpu_die_early
Or in other words, make fail_incapable_cpu() reusable.

We use fail_incapable_cpu() to kill a secondary CPU early during the
bringup, which doesn't have the system advertised capabilities.
This patch makes the routine more generic, to kill a secondary
booting CPU, getting rid of the dependency on capability struct.
This can be used by checks which are not necessarily attached to
a capability struct (e.g, cpu ASIDBits).

In that process, renames the function to cpu_die_early() to better
match its functionality. This will be moved to arch/arm64/kernel/smp.c
later.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 17:17:44 +00:00
Suzuki K Poulose c4bc34d202 arm64: Add a helper for parking CPUs in a loop
Adds a routine which can be used to park CPUs (spinning in kernel)
when they can't be killed.

Cc: Mark Rutland <mark.rutland@arm.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Suzuki K Poulose <suzuki.poulose@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 17:17:44 +00:00
Ard Biesheuvel 2b5fe07a78 arm64: efi: invoke EFI_RNG_PROTOCOL to supply KASLR randomness
Since arm64 does not use a decompressor that supplies an execution
environment where it is feasible to some extent to provide a source of
randomness, the arm64 KASLR kernel depends on the bootloader to supply
some random bits in the /chosen/kaslr-seed DT property upon kernel entry.

On UEFI systems, we can use the EFI_RNG_PROTOCOL, if supplied, to obtain
some random bits. At the same time, use it to randomize the offset of the
kernel Image in physical memory.

Reviewed-by: Matt Fleming <matt@codeblueprint.co.uk>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:29 +00:00
Ard Biesheuvel c031a4213c arm64: kaslr: randomize the linear region
When KASLR is enabled (CONFIG_RANDOMIZE_BASE=y), and entropy has been
provided by the bootloader, randomize the placement of RAM inside the
linear region if sufficient space is available. For instance, on a 4KB
granule/3 levels kernel, the linear region is 256 GB in size, and we can
choose any 1 GB aligned offset that is far enough from the top of the
address space to fit the distance between the start of the lowest memblock
and the top of the highest memblock.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:27 +00:00
Ard Biesheuvel f80fb3a3d5 arm64: add support for kernel ASLR
This adds support for KASLR is implemented, based on entropy provided by
the bootloader in the /chosen/kaslr-seed DT property. Depending on the size
of the address space (VA_BITS) and the page size, the entropy in the
virtual displacement is up to 13 bits (16k/2 levels) and up to 25 bits (all
4 levels), with the sidenote that displacements that result in the kernel
image straddling a 1GB/32MB/512MB alignment boundary (for 4KB/16KB/64KB
granule kernels, respectively) are not allowed, and will be rounded up to
an acceptable value.

If CONFIG_RANDOMIZE_MODULE_REGION_FULL is enabled, the module region is
randomized independently from the core kernel. This makes it less likely
that the location of core kernel data structures can be determined by an
adversary, but causes all function calls from modules into the core kernel
to be resolved via entries in the module PLTs.

If CONFIG_RANDOMIZE_MODULE_REGION_FULL is not enabled, the module region is
randomized by choosing a page aligned 128 MB region inside the interval
[_etext - 128 MB, _stext + 128 MB). This gives between 10 and 14 bits of
entropy (depending on page size), independently of the kernel randomization,
but still guarantees that modules are within the range of relative branch
and jump instructions (with the caveat that, since the module region is
shared with other uses of the vmalloc area, modules may need to be loaded
further away if the module region is exhausted)

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:27 +00:00
Ard Biesheuvel 1e48ef7fcc arm64: add support for building vmlinux as a relocatable PIE binary
This implements CONFIG_RELOCATABLE, which links the final vmlinux
image with a dynamic relocation section, allowing the early boot code
to perform a relocation to a different virtual address at runtime.

This is a prerequisite for KASLR (CONFIG_RANDOMIZE_BASE).

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:27 +00:00
Ard Biesheuvel 6c94f27ac8 arm64: switch to relative exception tables
Instead of using absolute addresses for both the exception location
and the fixup, use offsets relative to the exception table entry values.
Not only does this cut the size of the exception table in half, it is
also a prerequisite for KASLR, since absolute exception table entries
are subject to dynamic relocation, which is incompatible with the sorting
of the exception table that occurs at build time.

This patch also introduces the _ASM_EXTABLE preprocessor macro (which
exists on x86 as well) and its _asm_extable assembly counterpart, as
shorthands to emit exception table entries.

Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:26 +00:00
Ard Biesheuvel 4a2e034e5c arm64: make asm/elf.h available to asm files
This reshuffles some code in asm/elf.h and puts a #ifndef __ASSEMBLY__
around its C definitions so that the CPP defines can be used in asm
source files as well.

Acked-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:25 +00:00
Ard Biesheuvel 2bf31a4a05 arm64: avoid dynamic relocations in early boot code
Before implementing KASLR for arm64 by building a self-relocating PIE
executable, we have to ensure that values we use before the relocation
routine is executed are not subject to dynamic relocation themselves.
This applies not only to virtual addresses, but also to values that are
supplied by the linker at build time and relocated using R_AARCH64_ABS64
relocations.

So instead, use assemble time constants, or force the use of static
relocations by folding the constants into the instructions.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:25 +00:00
Ard Biesheuvel 6ad1fe5d90 arm64: avoid R_AARCH64_ABS64 relocations for Image header fields
Unfortunately, the current way of using the linker to emit build time
constants into the Image header will no longer work once we switch to
the use of PIE executables. The reason is that such constants are emitted
into the binary using R_AARCH64_ABS64 relocations, which are resolved at
runtime, not at build time, and the places targeted by those relocations
will contain zeroes before that.

So refactor the endian swapping linker script constant generation code so
that it emits the upper and lower 32-bit words separately.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:25 +00:00
Ard Biesheuvel fd045f6cd9 arm64: add support for module PLTs
This adds support for emitting PLTs at module load time for relative
branches that are out of range. This is a prerequisite for KASLR, which
may place the kernel and the modules anywhere in the vmalloc area,
making it more likely that branch target offsets exceed the maximum
range of +/- 128 MB.

In this version, I removed the distinction between relocations against
.init executable sections and ordinary executable sections. The reason
is that it is hardly worth the trouble, given that .init.text usually
does not contain that many far branches, and this version now only
reserves PLT entry space for jump and call relocations against undefined
symbols (since symbols defined in the same module can be assumed to be
within +/- 128 MB)

For example, the mac80211.ko module (which is fairly sizable at ~400 KB)
built with -mcmodel=large gives the following relocation counts:

                    relocs    branches   unique     !local
  .text              3925       3347       518        219
  .init.text           11          8         7          1
  .exit.text            4          4         4          1
  .text.unlikely       81         67        36         17

('unique' means branches to unique type/symbol/addend combos, of which
!local is the subset referring to undefined symbols)

IOW, we are only emitting a single PLT entry for the .init sections, and
we are better off just adding it to the core PLT section instead.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-24 14:57:24 +00:00
Georgi Djakov e2841db7a2 arm64: dts: qcom: msm8916: Add RPMCC DT node
Add the RPM Clock Controller DT node and include the necessary header
file for clocks.

Signed-off-by: Georgi Djakov <georgi.djakov@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:06 -06:00
Stephen Boyd bd6429e810 ARM64: dts: qcom: Remove size elements from pmic reg properties
The #size-cells for the pmics are 0, but we specify a size in the
reg property so that MPP and GPIO modules can figure out how many
pins there are. Now that we've done that by counting irqs, we can
remove the size elements in the reg properties and be DT
compliant.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Acked-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:06 -06:00
Rajendra Nayak a70d74492b arm64: dts: msm8996: Add #power-domain-cells property
Add #power-domain-cells property for both the gcc and mmcc
clock controller nodes as they both supports power domains (gdsc's)

Signed-off-by: Rajendra Nayak <rnayak@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:05 -06:00
Srinivas Kandagatla b0542d4a41 arm64: dts: apq8016-sbc: Add real regulators and pinctrl for sdhc
This patch adds real regulators and pinctrl nodes for sdhc_1.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:05 -06:00
Srinivas Kandagatla 0283687c5e arm64: dts: apq8016-sbc: move sdhci node under soc node
To be consistent with other nodes move sdhci node under the soc node,
rather than using lable references.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:05 -06:00
Srinivas Kandagatla 828dd5d66f arm64: dts: apq8016-sbc: make 1.8v available on LS expansion
96boards mezzanine boards on LS expansion require 1.8v as per 96boards
specifications, so enable the corresponding regulators and make them
always-on.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:04 -06:00
Srinivas Kandagatla 4c7d53d16d arm64: dts: apq8016-sbc: add regulators support
This patch adds required regulators for apq8016-sbc aka db410c board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:04 -06:00
Srinivas Kandagatla 0ba7da26c2 arm64: dts: qcom: add lable for smd rpm regulators
This patch adds label to smd rpm regulators so that the board level file
can use the label directly to populate the regulators, rather than
having deep nesting.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:03 -06:00
Srinivas Kandagatla 7b08f61ef2 arm64: dts: remove s2 regulator from smd regulators.
s2 is spmi controller regulator on msm8916 according to downstream 3.10
kernel, so remove it from the dt to avoid confusion an use of it.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:03 -06:00
Srinivas Kandagatla 93a3514182 arm64: dts: qcom: add correct drive strenght on cs pins
2mA drive strenght is not enough to drive chipselect low on hardware
configurations with level shifters, 16mA should give good range to
allow such configurations to work.

This issue was noticed while testing spi on db410c with sensor board.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:03 -06:00
Srinivas Kandagatla df984b8b5a arm64: dts: qcom: remove redundant spi cs pins from pinconf
This patch removes redundant pins from spi pinconf as these are already
specified in pinconf_cs.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:02 -06:00
Srinivas Kandagatla 09cbd8ed15 arm64: dts: apq8016-sbc: Add aliases to spi device.
This patch adds aliases to spi device so that it can get proper bus
number rather than a random number.

Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:02 -06:00
Stephen Boyd 0a9bcf4e09 arm64: dts: Add L2 cache node to msm8916
The msm8916 SoC has an L2 cache for all 4 CPUs. Add it to the
dtsi file so that the cache hierarchy can be probed.

Cc: <devicetree@vger.kernel.org>
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:02 -06:00
Stephen Boyd 886c73babe arm64: dts: Rename qcom,gcc node to clock-controller
Use the standard name for clock controller nodes instead of a
qcom specific name.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:14:01 -06:00
Stephen Boyd 0804308fdd arm64: dts: qcom: Add pm8994 gpios and MPPs
Add the gpio and MPP devices to the pm8994 pmic dts.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-24 00:13:54 -06:00
Yoshihiro Shimoda a9c42f0238 arm64: defconfig: Add Renesas R-Car Gen3 USB 2.0 phy driver support
Signed-off-by: Yoshihiro Shimoda <yoshihiro.shimoda.uh@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-24 09:44:34 +09:00
Stephen Boyd 38757eb3ca arm64: dts: qcom: Add pm8994, pmi8994, pm8004 PMIC skeletons
Add the skeleton nodes for the PMICs found on msm8996-mtp
devices.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-23 15:14:24 -06:00
Stephen Boyd 4558e9b319 arm64: dts: Add msm8996 SoC and MTP board support
Add initial device tree support for the Qualcomm MSM8996 SoC and
MTP8996 evaluation board.

Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
2016-02-23 15:14:15 -06:00
Ard Biesheuvel f98deee9a9 arm64: move brk immediate argument definitions to separate header
Instead of reversing the header dependency between asm/bug.h and
asm/debug-monitors.h, split off the brk instruction immediate value
defines into a new header asm/brk-imm.h, and include it from both.

This solves the circular dependency issue that prevents BUG() from
being used in some header files, and keeps the definitions together.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-23 17:43:25 +00:00
Ard Biesheuvel 8439e62a15 arm64: mm: use bit ops rather than arithmetic in pa/va translations
Since PAGE_OFFSET is chosen such that it cuts the kernel VA space right
in half, and since the size of the kernel VA space itself is always a
power of 2, we can treat PAGE_OFFSET as a bitmask and replace the
additions/subtractions with 'or' and 'and-not' operations.

For the comparison against PAGE_OFFSET, a mov/cmp/branch sequence ends
up getting replaced with a single tbz instruction. For the additions and
subtractions, we save a mov instruction since the mask is folded into the
instruction's immediate field.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-23 17:43:25 +00:00
Ard Biesheuvel a92405f082 arm64: mm: only perform memstart_addr sanity check if DEBUG_VM
Checking whether memstart_addr has been assigned every time it is
referenced adds a branch instruction that may hurt performance if
the reference in question occurs on a hot path. So only perform the
check if CONFIG_DEBUG_VM=y.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
[catalin.marinas@arm.com: replaced #ifdef with VM_BUG_ON]
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-23 17:42:11 +00:00
David S. Miller b633353115 Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net
Conflicts:
	drivers/net/phy/bcm7xxx.c
	drivers/net/phy/marvell.c
	drivers/net/vxlan.c

All three conflicts were cases of simple overlapping changes.

Signed-off-by: David S. Miller <davem@davemloft.net>
2016-02-23 00:09:14 -05:00
Krzysztof Kozlowski c87b3e970c arm64: EXYNOS: Consolidate ARCH_EXYNOS7 symbol into ARCH_EXYNOS
The ARMv8 Exynos family SoCs in Linux kernel are currently:
 - Exynos5433 (controlled by ARCH_EXYNOS),
 - Exynos7 (controlled by ARCH_EXYNOS7).

It duplicates Kconfig symbols unnecessarily, so consolidate them into
one ARCH_EXYNOS. Future SoCs could fall also under the ARCH_EXYNOS
symbol.

The commit should not bring any visible functional change.

Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Chanwoo Choi <cw00.choi@samsung.com>
Reviewed-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Tested-by: Alim Akhtar <alim.akhtar@samsung.com>
Reviewed-by: Tomasz Figa <tomasz.figa@gmail.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Reviewed-by: Andi Shyti <andi.shyti@samsung.com>
2016-02-23 08:49:46 +09:00
Kees Cook e267d97b83 asm-generic: Consolidate mark_rodata_ro()
Instead of defining mark_rodata_ro() in each architecture, consolidate it.

Signed-off-by: Kees Cook <keescook@chromium.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Andy Gross <agross@codeaurora.org>
Cc: Andy Lutomirski <luto@amacapital.net>
Cc: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Ashok Kumar <ashoks@broadcom.com>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Borislav Petkov <bp@suse.de>
Cc: Brian Gerst <brgerst@gmail.com>
Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Dan Williams <dan.j.williams@intel.com>
Cc: David Brown <david.brown@linaro.org>
Cc: David Hildenbrand <dahi@linux.vnet.ibm.com>
Cc: Denys Vlasenko <dvlasenk@redhat.com>
Cc: Emese Revfy <re.emese@gmail.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Helge Deller <deller@gmx.de>
Cc: James E.J. Bottomley <jejb@parisc-linux.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Luis R. Rodriguez <mcgrof@suse.com>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: Mathias Krause <minipli@googlemail.com>
Cc: Michael Ellerman <mpe@ellerman.id.au>
Cc: Nicolas Pitre <nicolas.pitre@linaro.org>
Cc: PaX Team <pageexec@freemail.hu>
Cc: Paul Gortmaker <paul.gortmaker@windriver.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Ross Zwisler <ross.zwisler@linux.intel.com>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Rusty Russell <rusty@rustcorp.com.au>
Cc: Stephen Boyd <sboyd@codeaurora.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: Toshi Kani <toshi.kani@hp.com>
Cc: kernel-hardening@lists.openwall.com
Cc: linux-arch <linux-arch@vger.kernel.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Cc: linux-parisc@vger.kernel.org
Link: http://lkml.kernel.org/r/1455748879-21872-2-git-send-email-keescook@chromium.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-02-22 08:51:37 +01:00
Ard Biesheuvel 1ce99bf453 arm64/vmlinux.lds.S: Handle .init.rodata.xxx and .init.bss sections
The EFI stub is typically built into the decompressor (x86, ARM) so none
of its symbols are annotated as __init. However, on arm64, the stub is
linked into the kernel proper, and the code is __init annotated at the
section level by prepending all names of SHF_ALLOC sections with '.init'.

This results in section names like .init.rodata.str1.8 (for string literals)
and .init.bss (which is tiny), both of which can be moved into the .init.data
output section.

Tested-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Matt Fleming <matt@codeblueprint.co.uk>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-efi@vger.kernel.org
Link: http://lkml.kernel.org/r/1455712566-16727-6-git-send-email-matt@codeblueprint.co.uk
Signed-off-by: Ingo Molnar <mingo@kernel.org>
2016-02-22 08:26:26 +01:00
Jayachandran C 9eb8a2cdf6 arm64: cputype info for Broadcom Vulcan
Add Broadcom Vulcan implementor ID and part ID in cputype.h. This is
to document the values.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Acked-by: Will Deacon <will.deacon@arm.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-20 10:42:38 -08:00
Zi Shen Lim 5bfb388987 arm64: Broadcom Vulcan support
Add a configuration option and a device tree for Broadcom's Vulcan
ARM64 processor. vulcan.dtsi has the on-chip blocks like the PCIe
controller, GICv3 with ITS, PMU, system timer and the pl011 UART.
vulcan-eval.dts has definitions for a basic evaluation board.

Vulcan's processor cores support the ARMv8.1 instruction set and
will use "brcm,vulcan" as the compatible property. The firmware
has PSCI 0.2 support for cpu wakeup.

Signed-off-by: Zi Shen Lim <zlim@broadcom.com>
[ updated and split dts - jchandra@broadcom.com ]
Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-20 10:42:29 -08:00
Jayachandran C 4cf430ee0c arm64: defconfig: Add Broadcom Vulcan to defconfig
Enable Broadcom Vulcan support in arm64 default configuration. This will
build the device tree needed to boot on a Broadcom Vulcan board.

Signed-off-by: Jayachandran C <jchandra@broadcom.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
2016-02-20 10:42:08 -08:00
Linus Torvalds 23300f6575 arm64 fixes:
- Allow EFI stub to use strnlen(), which is required by recent libfdt
 
 - Avoid smp_processor_id() in preempt context during unwinding
 
 - Avoid false Kasan warnings during unwinding
 
 - Ensure early devices are picked up by the IOMMU DMA ops
 
 - Avoid rebuilding the kernel for the 'install' target
 
 - Run fixup handlers for alignment faults on userspace access
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Merge tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux

Pull arm64 fixes from Will Deacon:
 "Here are some more arm64 fixes for 4.5.  This has mostly come from
  Yang Shi, who saw some issues under -rt that also affect mainline.
  The rest of it is pretty small, but still worth having.

  We've got an old issue outstanding with valid_user_regs which will
  likely wait until 4.6 (since it would really benefit from some time in
  -next) and another issue with kasan and idle which should be fixed
  next week.

  Apart from that, pretty quiet here (and still no sign of the THP issue
  reported on s390...)

  Summary:

   - Allow EFI stub to use strnlen(), which is required by recent libfdt

   - Avoid smp_processor_id() in preempt context during unwinding

   - Avoid false Kasan warnings during unwinding

   - Ensure early devices are picked up by the IOMMU DMA ops

   - Avoid rebuilding the kernel for the 'install' target

   - Run fixup handlers for alignment faults on userspace access"

* tag 'arm64-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/arm64/linux:
  arm64: mm: allow the kernel to handle alignment faults on user accesses
  arm64: kbuild: make "make install" not depend on vmlinux
  arm64: dma-mapping: fix handling of devices registered before arch_initcall
  arm64/efi: Make strnlen() available to the EFI namespace
  arm/arm64: crypto: assure that ECB modes don't require an IV
  arm64: make irq_stack_ptr more robust
  arm64: debug: re-enable irqs before sending breakpoint SIGTRAP
  arm64: disable kasan when accessing frame->fp in unwind_frame
2016-02-19 08:40:05 -08:00
Catalin Marinas 70c8abc287 arm64: User die() instead of panic() in do_page_fault()
The former gives better error reporting on unhandled permission faults
(introduced by the UAO patches).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-19 14:28:58 +00:00
Thomas Petazzoni b3920b2b23 arm64: update ARCH_MVEBU for Marvell Armada 7K/8K support
This commit updates the ARCH_MVEBU Kconfig option introduced for
Armada 3700 to also be used for the Armada 7K and 8K platforms, by:

 - Selecting the appropriate clock and irqchip drivers
 - Updating the help text to mention Armada 7K and 8K

Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
2016-02-19 14:08:10 +01:00
EunTaik Lee 52d7523d84 arm64: mm: allow the kernel to handle alignment faults on user accesses
Although we don't expect to take alignment faults on access to normal
memory, misbehaving (i.e. buggy) user code can pass MMIO pointers into
system calls, leading to things like get_user accessing device memory.

Rather than OOPS the kernel, allow any exception fixups to run and
return something like -EFAULT back to userspace. This makes the
behaviour more consistent with userspace, even though applications with
access to device mappings can easily cause other issues if they try
hard enough.

Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Eun Taik Lee <eun.taik.lee@samsung.com>
[will: dropped __kprobes annotation and rewrote commit mesage]
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-19 12:20:37 +00:00
Masahiro Yamada 8684fa3e7a arm64: kbuild: make "make install" not depend on vmlinux
For the same reason as commit 19514fc665 ("arm, kbuild: make "make
install" not depend on vmlinux"), the install targets should never
trigger the rebuild of the kernel.

Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-19 10:33:35 +00:00
Eddie Huang 3ea064b1e5 ARM64: dts: Mediatek: mt8173-evb: fix access MMC fail issue
MT8173 E1 chip has one bug that if turn off USB power domain, vcore
power will also be off, thus cause modules using vcore power domain
fail, like MMC. The E1 chip only found on MT8173-evb board and this
board only has E1 chip, so implement this as a board specific
workaround.

Pwrapper use vcore power, so add pwrapper using USB power domain to
keep USB power domain not to zero and disabled.

Signed-off-by: Eddie Huang <eddie.huang@mediatek.com>
Signed-off-by: Matthias Brugger <matthias.bgg@gmail.com>
2016-02-19 11:05:09 +01:00
Dirk Behme 4c811edf65 arm64: dts: r8a7795: Add GIC-400 virtual interfaces
Besides the distributor and the CPU interface the GIC-400 additionally
supports the virtual interface control blocks and the virtual CPU interfaces.

Add the physical base addresses and size for these.

See

http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0471b/index.html
-> 3.2. GIC-400 register map

and Linux kernel's

Documentation/devicetree/bindings/interrupt-controller/arm,gic.txt

for more details.

For the at GICH Virtual interface control blocks at 0xf1040000 cover the
whole 128kB (0x20000) range. This is done based on the advice from Marc
Zyngier http://www.spinics.net/lists/arm-kernel/msg483139.html

Signed-off-by: Dirk Behme <dirk.behme@de.bosch.com>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-19 14:55:33 +09:00
Geert Uytterhoeven 2ee98234b8 arm64: renesas: Enable PM and PM_GENERIC_DOMAINS for SoCs with PM Domains
All supported Renesas ARM64 SoCs have clock and power domains. To ensure
proper operation of on-SoC modules, module clocks must be ungated, and
power domains must be powered up when needed.

Currently the user can choose to build a kernel with power management
enabled or disabled:
  - If CONFIG_PM=y, power domains and/or module clocks are handled
    dynamically by Runtime PM and the generic power domain.
  - If CONFIG_PM=n, power domains are assumed to be powered up by reset
    state or by the boot loader, and module clocks are handled by the
    legacy clock domain on driver (un)bind.
    The latter is implemented using a platform bus notifier, which
    applies not only to all on-SoC devices, but to all platform devices
    present in the system.

To remove the dependency on implicit assumptions, and to get rid of the
peculiarities of the legacy clock domain, enable CONFIG_PM and
CONFIG_PM_GENERIC_DOMAINS unconditionally.

Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-19 14:55:18 +09:00
Magnus Damm f7e020512e arm64: renesas: Enable RENESAS_IRQC
Select RENESAS_IRQC for Arm64 SoCs from Renesas to enable
build of drivers/irqchip/irq-renesas-irqc.c.

Signed-off-by: Magnus Damm <damm+renesas@opensource.se>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
2016-02-19 14:55:05 +09:00
Jan Glauber 94085fe570 arm64: dts: Add Cavium ThunderX specific PMU
Add a compatible string for the Cavium ThunderX PMU.

Signed-off-by: Jan Glauber <jglauber@cavium.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
2016-02-18 18:43:32 +00:00
Ard Biesheuvel a7f8de168a arm64: allow kernel Image to be loaded anywhere in physical memory
This relaxes the kernel Image placement requirements, so that it
may be placed at any 2 MB aligned offset in physical memory.

This is accomplished by ignoring PHYS_OFFSET when installing
memblocks, and accounting for the apparent virtual offset of
the kernel Image. As a result, virtual address references
below PAGE_OFFSET are correctly mapped onto physical references
into the kernel Image regardless of where it sits in memory.

Special care needs to be taken for dealing with memory limits passed
via mem=, since the generic implementation clips memory top down, which
may clip the kernel image itself if it is loaded high up in memory. To
deal with this case, we simply add back the memory covering the kernel
image, which may result in more memory to be retained than was passed
as a mem= parameter.

Since mem= should not be considered a production feature, a panic notifier
handler is installed that dumps the memory limit at panic time if one was
set.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:53 +00:00
Ard Biesheuvel a89dea5853 arm64: defer __va translation of initrd_start and initrd_end
Before deferring the assignment of memstart_addr in a subsequent patch, to
the moment where all memory has been discovered and possibly clipped based
on the size of the linear region and the presence of a mem= command line
parameter, we need to ensure that memstart_addr is not used to perform __va
translations before it is assigned.

One such use is in the generic early DT discovery of the initrd location,
which is recorded as a virtual address in the globals initrd_start and
initrd_end. So wire up the generic support to declare the initrd addresses,
and implement it without __va() translations, and perform the translation
after memstart_addr has been assigned.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:49 +00:00
Ard Biesheuvel f9040773b7 arm64: move kernel image to base of vmalloc area
This moves the module area to right before the vmalloc area, and moves
the kernel image to the base of the vmalloc area. This is an intermediate
step towards implementing KASLR, which allows the kernel image to be
located anywhere in the vmalloc area.

Since other subsystems such as hibernate may still need to refer to the
kernel text or data segments via their linears addresses, both are mapped
in the linear region as well. The linear alias of the text region is
mapped read-only/non-executable to prevent inadvertent modification or
execution.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:44 +00:00
Ard Biesheuvel a0bf9776cd arm64: kvm: deal with kernel symbols outside of linear mapping
KVM on arm64 uses a fixed offset between the linear mapping at EL1 and
the HYP mapping at EL2. Before we can move the kernel virtual mapping
out of the linear mapping, we have to make sure that references to kernel
symbols that are accessed via the HYP mapping are translated to their
linear equivalent.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:40 +00:00
Ard Biesheuvel 157962f5a8 arm64: decouple early fixmap init from linear mapping
Since the early fixmap page tables are populated using pages that are
part of the static footprint of the kernel, they are covered by the
initial kernel mapping, and we can refer to them without using __va/__pa
translations, which are tied to the linear mapping.

Since the fixmap page tables are disjoint from the kernel mapping up
to the top level pgd entry, we can refer to bm_pte[] directly, and there
is no need to walk the page tables and perform __pa()/__va() translations
at each step.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:34 +00:00
Ard Biesheuvel 6533945a32 arm64: pgtable: implement static [pte|pmd|pud]_offset variants
The page table accessors pte_offset(), pud_offset() and pmd_offset()
rely on __va translations, so they can only be used after the linear
mapping has been installed. For the early fixmap and kasan init routines,
whose page tables are allocated statically in the kernel image, these
functions will return bogus values. So implement pte_offset_kimg(),
pmd_offset_kimg() and pud_offset_kimg(), which can be used instead
before any page tables have been allocated dynamically.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:31 +00:00
Ard Biesheuvel ab893fb9f1 arm64: introduce KIMAGE_VADDR as the virtual base of the kernel region
This introduces the preprocessor symbol KIMAGE_VADDR which will serve as
the symbolic virtual base of the kernel region, i.e., the kernel's virtual
offset will be KIMAGE_VADDR + TEXT_OFFSET. For now, we define it as being
equal to PAGE_OFFSET, but in the future, it will be moved below it once
we move the kernel virtual mapping out of the linear mapping.

Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:27 +00:00
Ard Biesheuvel 324420bf91 arm64: add support for ioremap() block mappings
This wires up the existing generic huge-vmap feature, which allows
ioremap() to use PMD or PUD sized block mappings. It also adds support
to the unmap path for dealing with block mappings, which will allow us
to unmap the __init region using unmap_kernel_range() in a subsequent
patch.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:16 +00:00
Ard Biesheuvel 03336b1df9 arm64: prevent potential circular header dependencies in asm/bug.h
Currently, using BUG_ON() in header files is cumbersome, due to the fact
that asm/bug.h transitively includes a lot of other header files, resulting
in the actual BUG_ON() invocation appearing before its definition in the
preprocessor input. So let's reverse the #include dependency between
asm/bug.h and asm/debug-monitors.h, by moving the definition of BUG_BRK_IMM
from the latter to the former. Also fix up one user of asm/debug-monitors.h
which relied on a transitive include.

Signed-off-by: Ard Biesheuvel <ard.biesheuvel@linaro.org>
Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 18:16:11 +00:00
Catalin Marinas e950631e84 arm64: Remove the get_thread_info() function
This function was introduced by previous commits implementing UAO.
However, it can be replaced with task_thread_info() in
uao_thread_switch() or get_fs() in do_page_fault() (the latter being
called only on the current context, so no need for using the saved
pt_regs).

Signed-off-by: Catalin Marinas <catalin.marinas@arm.com>
2016-02-18 17:27:05 +00:00