"PHONY += FORCE" is already cared by scripts/Makefile.build,
which these files are included from.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
Since commit 2aedcd098a ('kbuild: suppress annoying "... is up to
date." message'), $(call if_changed,...) is evaluated to "@:"
when there is nothing to do.
We no longer need to add "@:" after $(call if_changed,...) to
suppress "... is up to date." message.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Michal Marek <mmarek@suse.com>
One part of the efs memory region is used specifically for sharing file system
buffers between the apps and modem cpus (aka rmtfs), so better reflect this
split.
Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the blsp_dma node to the device tree and the required
properties for using DMA with serial
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the crypto nodes to the ipq4019 device tree, it also adds the
BAM node used by crypto as well which the driver currently requires to
operate properly
The crypto driver itself depends on some other patches to qcom_bam_dma
to function properly:
https://lkml.org/lkml/2015/12/1/113
CC: Stanimir Varbanov <svarbanov@mm-sol.com>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds some operating points for cpu frequeny scaling
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This will allow boards to enable the I2C bus
CC: Sricharan R <srichara@qti.qualcomm.com>
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This will allow boards to enable the SPI bus
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This will allow these types of boards to be rebooted.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This will allow boards to enable watchdog support
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
This adds the required device tree nodes to bring up the
secondary cores on the ipq4019 SoC.
Signed-off-by: Matthew McClintock <mmcclint@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Initial board support dts files for DK01 board.
Signed-off-by: Senthilkumar N L <snlakshm@codeaurora.org>
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Add initial dts files and SoC support for IPQ4019
Signed-off-by: Varadarajan Narayanan <varada@codeaurora.org>
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Adding reset-gpio-active-high boolean DT binding property, which we need to
make PCIe working on Apalis SoMs and not break old DTBs. While at it, I've
fixed comment and GPIO polarity.
On Apalis SoMs the GPIO1_IO28 used to PCIe reset is not connected directly
to PERST# PCIe signal, but it's ORed with RESETBMCU coming off the PMIC,
and thus is inverted, active-high.
Signed-off-by: Petr Štetiar <ynezz@true.cz>
Signed-off-by: Bjorn Helgaas <bhelgaas@google.com>
This patch adds the CPU node of the BCM2835 into the DT.
Signed-off-by: Stefan Wahren <stefan.wahren@i2se.com>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Stephen Warren <swarren@wwwdotorg.org>
Reviewed-by: Eric Anholt <eric@anholt.net>
The ARM TWD interrupt is a private peripheral interrupt (PPI), and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED.
For R-Car H1 devices the PPI type cannot be set, and so when we attempt
to set the type for the ARM TWD interrupt it fails. This has gone
unnoticed because it fails silently, and because we cannot re-configure
the type it has had no impact. Nevertheless fix the type for the TWD
interrupt so that it matches the hardware configuration.
Based on patches by Jon Hunter for Tegra20/30 and OMAP4.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The ARM TWD interrupt is a private peripheral interrupt (PPI), and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED.
For SH-Mobile AG5 devices the PPI type cannot be set, and so when we
attempt to set the type for the ARM TWD interrupt it fails. This has
gone unnoticed because it fails silently, and because we cannot
re-configure the type it has had no impact. Nevertheless fix the type
for the TWD interrupt so that it matches the hardware configuration.
Based on patches by Jon Hunter for Tegra20/30 and OMAP4.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Add IIC nodes to r8a7794 device tree.
Based on similar work for the r8a7793 by Laurent Pinchart.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add IIC clocks to r8a7794 device tree.
Based on similar work for the r8a7790 by Wolfram Sang.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
The R-Car CAN controllers can derive the CAN bus clock not only from their
peripheral clock input (clkp1) but also from the other internal clock
(clkp2) and external clock fed on CAN_CLK pin. Describe those clocks in
the device tree along with the USB_EXTAL clock from which clkp2 is
derived.
Based on work by Sergei Shtylyov for the r8a7791 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Add CAN nodes to r8a7794 device tree.
Based on work by Sergei Shtylyov for the r8a7791 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Add CAN nodes to r8a7794 device tree.
Based on work by Sergei Shtylyov for the r8a7791 SoC.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Acked-by: Ramesh Shanmugasundaram <ramesh.shanmugasundaram@bp.renesas.com>
Based on Rev. 2.00 of the R-Car Gen2 datasheet.
Signed-off-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This reverts commit 19417bd9c5 ("ARM: dts: porter: Enable SCIF_CLK
frequency and pins") as according to
http://elinux.org/File:R-CarM2-KOELSCH_PORTER-B_PORTER_C_Comparison.pdf
the external oscillator for SCIF_CLK is not mounted on the porter boards.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
clk_get on a disabled clock node will return EPROBE_DEFER, which can
cause drivers to be deferred forever if such clocks are referenced in
their clocks property.
Update the various disabled external clock nodes to default to a
frequency of 0, but don't disable them to prevent this.
Signed-off-by: Sjoerd Simons <sjoerd.simons@collabora.co.uk>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Obviously, these are PHONY targets.
Signed-off-by: Masahiro Yamada <yamada.masahiro@socionext.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add interrupt-names properties to dt and apply the correct
mapping between irq and dma channels.
Signed-off-by: Martin Sperl <kernel@martin.sperl.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
Acked-by: Eric Anholt <eric@anholt.net>
Signed-off-by: Vinod Koul <vinod.koul@intel.com>
The DRAM gates control whether the image / display devices on the SoC have
access to the DRAM clock or not.
Enable it.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
It turns out that the A13 / R8 also have a tve encoder block, and a gate
for it.
Add it to the DT.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Enable the pll3 and pll7 clocks in the DT that are used to drive the
display-related clocks.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Acked-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch changes SROM nodes compatible from generic to model specific
to match with binding documentation. Also updating property
"samsung,srom-page-mode" as it is not defined as bool instead of int
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
The official UDOO board kit has 7 and 15.6 inch touchscreen LCD panels
as options.
This patch adds support for 7 inch panel only, but the 15.6 inch one
should be easy to add using the same regulator, backlight device and
LVDS channel.
Since this panel is an option for UDOO board it is disabled by default
and can be enabled (for example) by the following U-Boot commands:
fdt set backlight status okay
fdt set panelchan status okay
fdt set panel7 status okay
fdt set touchscreenp7 status okay
The LVDS channels is also disabled by default to avoid warning from its
driver.
Signed-off-by: Maciej S. Szmigiero <mail@maciej.szmigiero.name>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the Keypad Port (KPP) devicetree nodes for IMX31 and IMX35 SOC.
Signed-off-by: Alexander Kurz <akurz@blala.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Probably most of NXP LPC32xx boards have 13MHz main oscillator and
therefore for HCLK PLL and ARM core clock rate default hardware
setting is 16 * 13MHz = 208MHz, however a user may vary HCLK PLL/ARM
core rate from 156MHz to about 266MHz for 13MHz clock source.
The change explicitly defines HCLK PLL output rate to default 208MHz
to overwrite any settings done by a bootloader, if needed it can be
redefined in a board DTS file.
Acked-by: Sylvain Lemieux <slemieux.tyco@gmail.com>
Signed-off-by: Vladimir Zapolskiy <vz@mleia.com>
The edp-phy control is a part of the General Register Files and
with a recent patch in 4.6 the phy driver can now also handle this
correctly, so move the dts node under the GRF as well.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Similar to the pmu, the general register files contain a lot of different
setting bits grouped into general registers, but also some somewhat special
entities like the controls for some phy-blocks or the io-voltage control.
To be able to move these blocks under the grf node where they actually
belong, make it a simple-mfd.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Add the Security Controller (SCC) module to the dtsi.
Signed-off-by: Steffen Trumtrar <s.trumtrar@pengutronix.de>
Signed-off-by: Herbert Xu <herbert@gondor.apana.org.au>
DRA72-EVM now has an upgrade to Rev C with SR2.0 silicon. As part of
this change, a few updates were factored in that were software
incompatible with previous board in few areas:
- We now use DP83867 ethernet phy instead of older DP838865 which fails
in certain use cases.
- Two Ethernet ports now instead of the single one in rev B.
- polarities changed for certain pcf gpios
- Due to SoC phy current requirements, VDDA supplies are split between
ldo3 and ldo2 (ldo2 was previously unused). NOTE: DSS (VDDA_VIDEO) is
still supplied by ldo5, HDMI is now supplied by LDO2 instead of using
LDO3.
NOTE: It does not make much sense to spin off a new board compatible
flag since there is no real benefit for the same.
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ChiliSOM has TPS65217's PWR_EN pin connected to AM335x PMIC_POWER_EN
pin. Processor's PMIC_POWER_EN is controlled by it's internal RTC, hence
RTC subsystem is responsible for proper board poweroff sequence.
This change enables complete poweroff sequence for ChiliBoard, switching
PMIC's state from ACTIVE to SLEEP.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
ChiliSOM has 2 Ethernet subsystems with different types of possibly used
PHY interfaces (i.e. MII, RMII, GMII, RGMII). Current code configured
pinmux for RMII on 1st Ethernet subsystem and enabled Ethernet MAC with
1 slave for all boards which use ChiliSOM.
This change moves pinmux configuration of 1st Ethernet subsystem to
ChiliBoard description, as this is board-specific.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
uart0 configuration code has been in SOM. However, it is possible to
use all (or none) of 6 uart's of AM335x processor present on ChiliSOM.
This fix moves declaration of uart0 from ChiliSOM to ChiliBoard, because
use of uart is strictly board-specific.
Signed-off-by: Marcin Niestroj <m.niestroj@grinn-global.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds the DMA engine to the Nomadik and assigns the UART
DMA channels. Both slave DMA for UARTs and the memcpy engine
works fine, tested on the Nomadik NHK15.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The LIS3LV02DL accelerometer on the Nomadik NHK15 can generate
IRQs by the DRDY line. Map this in the DTS file and set up the
pin as input to the SoC.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This platform is based on a Marvell 88E6282 SoC and 88E6171 switch.
[gregory.clement@free-electrons.com: fix block comment style]
Signed-off-by: Bert Vermeulen <bert@biot.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add dts file to support Buffalo/Revogear Kurobox-Pro, which is marvell
orion5x based 3.5" HDD NAS.
It's a quite old product and already discontinued. So there's no
official website for it. But it was an early product which used marvell
orion5x 88F5182 chipset, it's popular in the community.
Some unofficial site:
- http://buffalo.nas-central.org/wiki/Category:KuroboxPro
- http://nice.kaze.com/KUROPRO_ProductSpecifications.pdf
This device tree is based on the board file:
arch/arm/mach-orion5x/kurobox_pro-setup.c
However, the probing order of NAND and JEDEC-Flash are different from
the original board file, this results in incompatible minor number
for a few /dev/mtdX and /dev/mtdblockX devices.
So I still want to keep the board file for the time being.
Signed-off-by: Roger Shimizu <rogershimizu@gmail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The regulator has a reg property so include it in the unit name.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
gpio-i2c does not have a reg property, just a list of gpios.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
PCIe has a range property, so the unit name should contain an address.
Make use of the label to enable individual PCIe busses. Also, fixup
the synology dtsi file which added a label pcie2 rather than using the
existing pcie1 label.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
PHYs have an address on the mdio bus. So the unit name should contain
an address. This is complicated in that some .dtsi files contain the
node, but the reg is set in the .dts file. In this case, use the
abstract address X.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The dsa node does not have a reg property, so remove the address from
the unit name.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
leds don't have a reg property, so remove the address from the unit name.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
The DT compiler is now warning about unit names with addresses but not
reg property. Fix all the gpio-key buttons which causes warnings.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
da850 has two I2C controllers, but the node for i2c1 was missing.
Add node for i2c1 controller and i2c1 pinmux pins.
Signed-off-by: Petr Kulhavy <petr@barix.com>
[nsekhar@ti.com: fix indentation]
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
TI has been using the physical address in DT after the @ in device nodes.
The device tree convention is to use the same address that is used for
the reg property. This updates all davinci DT files to use the proper
convention.
Signed-off-by: David Lechner <david@lechnology.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
The gpio node is missing the mandatory property #gpio-cells, which is
causing runtime errors when using GPIOs e.g. with gpio-leds or gpio-keys:
"could not get #gpio-cells for /soc/gpio@1e26000"
This fixes the problem and adds the missing parameter.
The value is 2 according to the gpio-davinci.txt binding.
Signed-off-by: Petr Kulhavy <petr@barix.com>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
as well as general display+hdmi support on rk3036. With the Analogix
DP support, Veyron Chromeboks can now finally use their internal
display.
Other than this big improvement we have thermal support on the rk3228,
a long time missing binding document for the General Register Files
block, better operating points for Veyron devices and a bunch of fixes
with parts stemming from warnings that new dtc version can generate.
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Merge tag 'v4.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip into next/dt
A lot display-controller nodes for DSI and the Analogix DP on rk3288
as well as general display+hdmi support on rk3036. With the Analogix
DP support, Veyron Chromeboks can now finally use their internal
display.
Other than this big improvement we have thermal support on the rk3228,
a long time missing binding document for the General Register Files
block, better operating points for Veyron devices and a bunch of fixes
with parts stemming from warnings that new dtc version can generate.
* tag 'v4.7-rockchip-dts32-1' of git://git.kernel.org/pub/scm/linux/kernel/git/mmind/linux-rockchip: (27 commits)
ARM: dts: rockchip: move rk3036 memory definition to board files
ARM: dts: rockchip: enable the eDP on rk3288 veyron devices
ARM: dts: rockchip: simple panel and backlight supplies on veyron boards
ARM: dts: rockchip: override edp hpd handling on veyron-pinky and speedy
ARM: dts: rockchip: add rk3288-veyron-minnie backlight and panel settings
ARM: dts: rockchip: add rk3288-veyron-jaq backlight and panel overrides
ARM: dts: rockchip: add core rk3288-veyron backlight and panel nodes
ARM: dts: rockchip: add startup delay to rk3288-veyron panel-regulators
ARM: dts: rockchip: move edp-hpd pin definition into common location
ARM: dts: rockchip: add rk3288 displayport controller node
ARM: dts: rockchip: add rk3288 edp-phy node
ARM: dts: rockchip: add missing unitname to cpu_leakage efuse
ARM: dts: rockchip: drop unneeded properties from mipi node
ARM: dts: rockchip: clean up gpio-keys nodes
ARM: dts: rockchip: fix missing usbphy unit-names
ARM: dts: rockchip: fix rk3288 power-domain unit names
ARM: dts: rockchip: update rk3288-veyron cpu operating points
ARM: dts: rockchip: remove broken-cd from emmc and sdio
ARM: dts: rockchip: enable the tsadc for rk3228 evb
ARM: dts: rockchip: add the thermal main info found on rk3228
...
Signed-off-by: Olof Johansson <olof@lixom.net>
- Update SD/MMC node for Arria10
- Update Arria10 with clock and interrupt fields for DMA
- Remove 'phy-addr' from stmmac node
- Remove ethernet node from Cyclone5 DTSI
- Add LEDs/KEYs/SWs support on Sockit
- Add L2 and OCRAM EDAC dts entries
- Add reset control for USB
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Merge tag 'socfpga_dts_for_v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux into next/dt
SoCFPGA DTS updates for v4.7
- Update SD/MMC node for Arria10
- Update Arria10 with clock and interrupt fields for DMA
- Remove 'phy-addr' from stmmac node
- Remove ethernet node from Cyclone5 DTSI
- Add LEDs/KEYs/SWs support on Sockit
- Add L2 and OCRAM EDAC dts entries
- Add reset control for USB
* tag 'socfpga_dts_for_v4.7' of git://git.kernel.org/pub/scm/linux/kernel/git/dinguyen/linux:
ARM: dts: socfpga: add reset control for USB
ARM: dts: socfpga: Add Altera Arria10 OCRAM EDAC devicetree entry
ARM: dts: socfpga: Add Altera Arria10 L2 Cache EDAC devicetree entry
ARM: dts: socfpga: Add support for HPS KEYs/SWs on SoCKit
ARM: dts: socfpga: Add support for HPS LEDs on SoCKit
ARM: dts: socfpga: Drop gmac0 from CV dtsi
ARM: dts: socfpga: Drop phy-addr OF property from CV dtsi
ARM: dts: socfpga: Add missing clock and interrupt fields for Arria10 DMA
ARM: dts: socfpga: add the clk-phase property for sd/mmc clock
ARM: dts: socfpga: add cap-sd-highspeed for SD/MMC node
Signed-off-by: Olof Johansson <olof@lixom.net>
- CREG clock controller
- Real Time Clock (RTC)
- Analog peripherals (ADC/DAC)
- Warning fixes for the new dtc compiler
With the CREG clock controller in place it is now possible
to enable the internal RTC on LPC18xx/43xx platforms. The
analog peripherals (ADC/DAC) has also been added here and
enabled on both the EA4357 dev kit and Hitex eval board.
In addition to the new entries there are a fixes for the
DT warnings generated by the new dtc.
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Merge tag 'lpc18xx_dts_for_4.7' of https://github.com/manabian/linux-lpc into next/dt
Device Tree additions for LPC18xx platform
- CREG clock controller
- Real Time Clock (RTC)
- Analog peripherals (ADC/DAC)
- Warning fixes for the new dtc compiler
With the CREG clock controller in place it is now possible
to enable the internal RTC on LPC18xx/43xx platforms. The
analog peripherals (ADC/DAC) has also been added here and
enabled on both the EA4357 dev kit and Hitex eval board.
In addition to the new entries there are a fixes for the
DT warnings generated by the new dtc.
* tag 'lpc18xx_dts_for_4.7' of https://github.com/manabian/linux-lpc:
dt-bindings: phy-lpc18xx-usb-otg: remove unit address from binding
ARM: dts: lpc4350-hitex-eval: fix unit name warnings from dtc
ARM: dts: lpc4357-ea4357: fix unit name warnings from dtc
ARM: dts: lpc18xx: remove unit addresses from creg childs
ARM: dts: armv7-m: add unit name to interrupt-controller
ARM: dts: lpc4350-hitex-eval: add adc1
ARM: dts: lpc4357-ea4357: add dac
ARM: dts: lpc4357-ea4357: add adc0
ARM: dts: lpc18xx: add dac node
ARM: dts: lpc18xx: add adc nodes
ARM: dts: lpc18xx: add rtc node
ARM: dts: lpc18xx: add creg-clk node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add CLCD panel nodes to PB1176 and PB11MPCore
- Add a DT binding blurb for the Versatile IB2 syscon
- Add DTS files for the (QEMU supported) RealView EB
boards in all variants.
- Add DTS files for the (QEMU supported) RealView PBA8
and PBX-A9 board variants.
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Merge tag 'versatile-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator into next/dt
Versatile DTS changes, baseline for the v4.7 series:
- Add CLCD panel nodes to PB1176 and PB11MPCore
- Add a DT binding blurb for the Versatile IB2 syscon
- Add DTS files for the (QEMU supported) RealView EB
boards in all variants.
- Add DTS files for the (QEMU supported) RealView PBA8
and PBX-A9 board variants.
* tag 'versatile-dts-1' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-integrator:
ARM: dts: realview: DT support for the PBA8 and PBX-A9
ARM: dts: realview: support all the RealView EB board variants
ARM: dts: realview: PB1176: define a standard VGA panel
ARM: dts: realview: PB11MPCore: define a standard VGA panel
Documentation/DT: add blurb for IB2 syscon to Versatile
Signed-off-by: Olof Johansson <olof@lixom.net>
USB1 controller is hardwired to be used as Host only port so
we don't need to check ID pin state and can get rid of extcon_usb1.
This also reduces USB1 controller's and so eSATA power's dependency
with EXTCON. This fixes eSATA port with multi_v7_defconfig.
Cc: Franklin S Cooper Jr. <fcooper@ti.com>
Cc: Vagrant Cascadian <vagrant@debian.org>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Tested-by: Franklin S Cooper Jr. <fcooper@ti.com>
[tony@atomide.com: updated to describe what it fixes]
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch updates the GPMC's DT DMA property to reflect the updated eDMA
bindings.
Fixes: cce1ee0001 ("ARM: DTS: am437x: Use the new DT bindings for the eDMA3")
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch updates the GPMC's DT DMA property to reflect the updated eDMA
bindings.
Fixes: b5e5090660 ("ARM: DTS: am33xx: Use the new DT bindings for the eDMA3")
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Acked-by: Roger Quadros <rogerq@ti.com>
Acked-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
clkout1 clock node and its generation tree was missing. Add this based
on the data on TRM and PRCM functional spec.
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Tested-by: Benoit Parrot <bparrot@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
There are few devices that have USB power controlled using GPIO. Linux
USB host driver (bcma-hcd) already supports this by reading vcc-gpio
from DT. Set it properly for all known devices.
Signed-off-by: Rafał Miłecki <zajec5@gmail.com>
Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
This commit adds definition for cpu_on, cpu_off and cpu_suspend commands.
These definitions must match the corresponding PSCI definitions in
boot monitor.
Having those command and corresponding PSCI support in boot monitor allows
run time CPU hot plugin.
Signed-off-by: Vitaly Andrianov <vitalya@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
Add aliases for SPI nodes, this is required to probe the SPI devices in
U-Boot.
Signed-off-by: Vignesh R <vigneshr@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
As reported in [1], rename the k2* dts files to keystone-* files
this will force consistency throughout.
Script for the same (and hand modified for Makefile and MAINTAINERS
files):
for i in arch/arm/boot/dts/k2*
do
b=`basename $i`;
git mv $i arch/arm/boot/dts/keystone-$b;
sed -i -e "s/$b/keystone-$b/g" arch/arm/boot/dts/*[si]
done
NOTE: bootloaders that depend on older dtb names will need to be
updated as well.
[1] http://marc.info/?l=linux-arm-kernel&m=145637407804754&w=2
Reported-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Santosh Shilimkar <ssantosh@kernel.org>
The DCU IP has distinct clock inputs for register access and the
pixel clocks, at least in some implementations. LS1021a seems to
use the same clock, therefore specify the same clock for "dcu"
and "pix".
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Both DSPI have signals SPIn_PCS[0:5] so in summary 6 chip-selects, not 5.
Fix that.
Signed-off-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add gpio nodes for ls1021a platform dts file. The gpio
IP block of the ls1021a can be supported by the code
drivers/gpio/gpio-mpc8xxx.c.
The compatible "fsl,qoriq-gpio" is used by gpio driver:
drivers/gpio/gpio-mpc8xxx.c to implement general gpio
functionalities.
The chip-specific compatible "fsl,ls1021a-gpio" may be
used to fix potential gpio IP block errata or other
chip-specific gpio issues.
Signed-off-by: Liu Gang <Gang.Liu@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The vqmmc supply is not connected to bio supply on the BA16 module.
Hence remove vqmmc-supply property in usdhc3 node.
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add SCFG MSI dts node and add msi-parent property to PCIe dts node
that points to the corresponding MSI node.
Signed-off-by: Minghuan Lian <Minghuan.Lian@nxp.com>
Tested-by: Alexander Stein <alexander.stein@systec-electronic.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to Documentation/devicetree/bindings/net/fsl-fec.txt the polarity
of "phy-reset-gpios" is assumed to be active-low unless a separate property
"phy-reset-active-high" is available. So replace the inconsistent polarity
description to make the correct active-low reset behavior more obvious.
Signed-off-by: Soeren Moch <smoch@web.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This commit adds support for Rev. B of a Zodiac Inflight Innovations
development board, mainly intended for DSA and ARINC 429 development
work.
Signed-off-by: Cory Tusar <cory.tusar@pid1solutions.com>
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add missing reg properties to AIPS bus and Cortex-A5's PMU unit.
This change avoids the following warnings:
Warning (unit_address_vs_reg): Node /soc/aips-bus@40000000 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000 has a unit
name, but no reg property
Warning (unit_address_vs_reg): Node /soc/aips-bus@40080000/pmu@40089000
has a unit name, but no reg property
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The NAND flash memory populated on Colibri VF61 allows faster NAND
timings than the flash memory on VF50. Additionally, due to divider
limitations, VF61 did clock the flash even slower than VF50. Assign
the NFC clock in the module specific device trees vf500-colibri.dtsi
and vf610-colibri.dtsi respectively.
This increases raw read speed on Colibri VF61 by about 20%.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The Vybrid based Colibri modules provide a on-module PHY which is
connected to the second FEC instance FEC1. Since the on-module
Ethernet port is considered as primary ethernet interface, alias
fec1 as ethernet0. This also makes sure that the first MAC address
provided by the boot loader gets assigned to the FEC instance used
for the on-module PHY.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Introduce imx6sx-sdb-sai.dts so that it is possible to use the
SAI interface.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Property 'dma-source' is not used anywhere, nor it is documented, so
let's just get rid of it.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
According to sdma_peripheral_type in include/linux/platform_data/dma-imx.h
IMX_DMATYPE_SAI corresponds to index 24, so fix it accordingly.
Suggested-by: Zidan Wang <zidan.wang@nxp.com>
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
pwm2 is provided on the BA16 Q7 module, but is not used on any
of the current configurations. However, future platforms may
utilize this device, so we are simply disabling the node rather
than removing it completely.
Signed-off-by: Justin Waters <justin.waters@timeys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
It is preferred to use the panel compatible string rather than passing the
LCD timings in the device tree.
So pass the "hannstar,hsd100pxn1" compatible string to describe
the LVDS panel on this board.
Signed-off-by: Fabio Estevam <fabio.estevam@nxp.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
This baseboard can be used with all TX6 SoMs, but only a certain set
of combinations can be ordered by default. Add support for these
combinations in mainline, so that users can easily adopt their own
combination of SoM and baseboard themselves.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add support for the following i.MX6 based modules from Ka-Ro
electronics GmbH:
TX6S-8034:
Processor Freescale i.MX 6 Solo, 800MHz
RAM 256MiB DDR3 SDRAM
ROM 128MiB NAND Flash
Power supply Single 3.1V to 5.5V
Size 31mm SO-DIMM
Temp. Range industrial grade (-40°C/-25°C to 105°C Tj)
TX6S-8035:
Processor Freescale i.MX 6 Solo, 800MHz
RAM 512MiB DDR3 SDRAM
ROM 4GiB eMMC
Power supply Single 3.1V to 5.5V
Size 31mm SO-DIMM
Temp. Range industrial grade (-40°C/-25°C to 105°C Tj)
TX6U-8033:
Processor Freescale i.MX 6 Dual Lite, 800MHz
RAM 1GiB DDR3 SDRAM
ROM 4GiB eMMC
Power supply Single 3.1V to 5.5V
Size 31mm SO-DIMM
Temp. Range industrial grade (-40°C/-25°C to 105°C Tj)
TX6Q-1036:
Processor Freescale i.MX 6Quad, 1GHz
RAM 1GB DDR3 SDRAM 64-bit
ROM 8GiB eMMC
Power supply Single 3.1V to 5.5V
Size 31mm SO-DIMM
Temp. Range Extended Consumer Grade (-20°C to 105°C Tj)
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add missing pinctrl for the RTS/CTS lines to uart1 and set the
fsl,uart-has-rtscts property on all UARTs to enable support for HW
handshake.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Move the pinctrl setting for the board LED from the hoggrp node
to a separate node referenced by the LED driver, so that the pin is
free to be used for different purpose when the LED driver is disabled.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
DT maintainers don't like the 'simple-bus' container around the
regulator nodes. So remove it.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Based on i.MX6 Quad Plus with 4GB of RAM.
https://boundarydevices.com/product/nitrogen6max/
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add mdio node and an appropriate PHY configuration to enable use of
the PHY interrupt for link status changes.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Remove the function node around the pinctrl nodes that was obsoleted
by commit 5fcdf6a7ed ("pinctrl: imx: Allow parsing DT without
function nodes"), we can save this container node.
Also move the iomux node to the bottom of the file to improve
readability of the file.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The spidev driver doesn't like to be instantiated via a naked 'spidev'
compatible, though it is very convenient to invoke it this way without
a dedicated SPI device for basic functional testing.
Disable the spi node by default to silence the WARN_ON() from the
spidev driver, but leave the configuration intact otherwise.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add an empty line between properties and subnode in the clocks node.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
GPLv2-only devicetrees make reuse difficult for software components
licensed under a different license.
The consensus is that a GPL/X11 dual-license should allow all necessary
uses, so relicense the imx6*-tx6* files to this combination.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
With SION set the level on such a pin is reported to the UART. So for
example when the CS5 pin is configured for GPIO mode and the level
changes this triggers an RTS interrupt on uart5.
Adding some severity to this issue: The imx uart driver currently
doesn't handle correctly irqs for changes on RI and DCD which are
enabled automatically when the respective UART is driven in DTE mode
(that is, has the fsl,dte-mode property set in the device tree). This
results in a stuck machine because the irq isn't cleared and so stalls
the CPU.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Apart from a few additions this also contains two fixes where the daisy
chain input selection register was missing. Moreover dropped _MUX from
some pins for consistency.
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Utilize the new PCIe Tx configuration to properly support the correct
values.
Signed-off-by: Justin Waters <justin.waters@timesys.com>
Signed-off-by: Akshay Bhat <akshay.bhat@timesys.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
The TXUL-0010/-0011 modules are Computers On Module manufactured by
Ka-Ro electronics GmbH with the following characteristics:
Processor Freescale i.MX 6UltraLite MCIMX6G2, 528 MHz
RAM 256MB 16-bit DDR3 SDRAM
ROM 128MB NAND Flash (TXUL-0010) / 4GB eMMC (TXUL-0011)
Power supply Single 3.3 to 5V
Size 26mm SO-DIMM
Temp. Range -40°C to 85°C
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Enable dcu node which is used by the DCU DRM driver. Assign the 5.7"
EDT panel with VGA resolution which Toradex sells often with the
evaluation board.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the dcu and tcon nodes to enable the Display Controller Unit
and Timing Controller in Vybrid's SoC level device-tree file.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Based on i.MX7 Dual with 1GB of RAM.
https://boundarydevices.com/product/nitrogen7/
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the device nodes for the i.MX7 FlexCAN buses.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Add the device node for the i.MX7 eLCDIF interface.
Signed-off-by: Gary Bisson <gary.bisson@boundarydevices.com>
Signed-off-by: Shawn Guo <shawnguo@kernel.org>
Fix following DTC warnings in SMDKv210 board:
Warning (unit_address_vs_reg): Node /soc/fimd@f8000000/display-timings/timing@0 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Exynos5440 boards:
Warning (unit_address_vs_reg): Node /pinctrl has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /rtc has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Exynos5420 SMDK5420:
Warning (unit_address_vs_reg): Node /dp-controller@145B0000/display-timings/timing@0 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Exynos5420 Peach Pit:
Warning (unit_address_vs_reg): Node /dp-controller@145B0000/ports/port@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c@12CD0000/lvds-bridge@48/ports/port@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c@12CD0000/lvds-bridge@48/ports/port@1 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in all Exynos542x/5800 boards:
Warning (unit_address_vs_reg): Node /video-phy@10040728 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /video-phy@10040714 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /usb@12000000 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /usb@12000000/dwc3 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /usb@12400000 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /usb@12400000/dwc3 has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in all Exynos5250 boards:
Warning (unit_address_vs_reg): Node /dp-controller@145B0000/display-timings/timing@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /usb@12000000 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /usb@12000000/dwc3 has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /hdmi has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /mixer has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /video-phy@10040720 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /fixed-regulator@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /fixed-regulator@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /fixed-regulator@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c@12C70000/trackpad has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /i2c@12CD0000/lvds-bridge@20/ports/port@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c@12CD0000/lvds-bridge@20/ports/port@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c-arbitrator/i2c@0/embedded-controller has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /i2c-arbitrator/i2c@0/power-regulator has a reg or ranges property, but no unit name
Warning (unit_address_vs_reg): Node /i2c@12CA0000/embedded-controller has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Exynos4x12 boards:
Warning (unit_address_vs_reg): Node /camera/fimc-is@12000000/pmu has a reg or ranges property, but no unit name
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Trats2 board:
Warning (unit_address_vs_reg): Node /i2c-gpio-1/max77693@66/regulators/ESAFEOUT1@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c-gpio-1/max77693@66/regulators/ESAFEOUT2@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /i2c-gpio-1/max77693@66/regulators/CHARGER@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /thermistor-ap@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /thermistor-battery@1 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in all Exynos4 boards:
Warning (unit_address_vs_reg): Node /soc/video-phy@10020710 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in Exynos3250 boards:
Warning (unit_address_vs_reg): Node /soc/video-phy@10020710 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Fix following DTC warnings in cros-adc-thermistors:
Warning (unit_address_vs_reg): Node /adc@12D10000/ncp15wb473@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /adc@12D10000/ncp15wb473@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /adc@12D10000/ncp15wb473@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /adc@12D10000/ncp15wb473@6 has a unit name, but no reg property
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add vmmc and vqmmc supplies from MF circuit sheets for eMMC and SD on
odroid XU3 and XU4 to avoid warnings:
dwmmc_exynos 12200000.mmc: Looking up vmmc-supply property in node /mmc@12200000 failed
Also remove their always_on properties so the regulators could be
disabled when not used.
Signed-off-by: Markus Reichl <m.reichl@fivetechno.de>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Merge necessary new clocks from Sylwester (used by new board) and add support
for Exynos3250-based Artik5 board.
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Merge tag 'samsung-dt-exynos3250-artik5-4.7' into next/dt
Topic branch for Device Tree changes for Exynos 3250 for v4.7:
Merge necessary new clocks from Sylwester (used by new board) and add support
for Exynos3250-based Artik5 board.
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 13212 KiB/ to 15753 KiB/s
and write speed was unchanged at 4404 KiB/s.
Measured using mtd_speedtest.ko on omap3-beagle-c4.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 7869 KiB/ to 8875 KiB/s
and write speed was unchanged at 5100 KiB/s.
Measured using mtd_speedtest.ko on am335x-evm.
Cc: Teresa Remmet <t.remmet@phytec.de>
Cc: Ilya Ledvich <ilya@compulab.co.il>
Cc: Yegor Yefremov <yegorslists@googlemail.com>
Cc: Rostislav Lisovy <lisovy@gmail.com>
Cc: Enric Balletbo i Serra <eballetbo@iseebcn.com>
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
For NAND we don't use GPMC wait pin monitoring but
get the NAND Ready/Busy# status using GPIOlib.
GPMC driver provides the WAIT0 pin status over GPIOlib.
Read speed increases from 16516 KiB/ to 18813 KiB/s
and write speed was unchanged at 9941 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
On these boards NAND ready pin status is avilable over
GPMC_WAIT0 pin.
Read speed increases from 13768 KiB/ to 17246 KiB/s.
Write speed was unchanged at 7123 KiB/s.
Measured using mtd_speedtest.ko.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides GPI support for the GPMC_WAIT pins.
Mark it gpio controller capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
GPMC driver provides interrupts and gpio for the GPMC_WAIT pins.
Mark it as gpio and interrupt capable.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds support for turning off the main power supply via the TWL6030 on the
Kindle Fire (first generation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds support for the Kindle Fire (first generation) power button LEDs, that
are wired to the TWL6030 PWM outputs.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This adds support for USB OTG on the Kindle Fire (first generation).
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Amazon Kindle Fire (first generation) codename kc1 is a tablet that was
released by Amazon back in 2011. It is using an OMAP4430 SoC GP version.
This adds devicetree support for the device, with only a few basic features
supported, such as debug uart, i2c and internal emmc.
Signed-off-by: Paul Kocialkowski <contact@paulk.fr>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Before "tty: Add software emulated RS485 support for 8250" patch Baltos devices
relied on MCTRL_GPIO framework to handle both modem signals and RS485 mode.
With emulated RS485 support for 8250 we can now use these pins as dedicated
RTS/CTS signals taking advantage of hardware flow control etc. when operating
in RS232 mode.
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The AM572x-IDK board is a board based on TI's AM5728 SOC
which has a dual core 1.5GHz A15 processor. This board is a
development platform for the Industrial market with:
- 2GB of DDR3L
- Dual 1Gbps Ethernet
- HDMI,
- PRU-ICSS
- uSD
- 16GB eMMC
- CAN
- RS-485
- PCIe
- USB3.0
- Video Input Port
- Industrial IO port and expansion connector
The link to the data sheet and TRM can be found here:
http://www.ti.com/product/AM5728
This patch creates a common dtsi file that will provide a common board
dtsi file to define the nodes that are common to AM57xx (including the
upcoming AM5718) IDK boards.
Initial support is only for basic peripherals
Signed-off-by: Schuyler Patton <spatton@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
TI's Industrial Communication Engine EVM is a low cost hardware mainly
developed for industrial communication type applications using serial
or Ethernet based interfaces. This platform features TI's AM3359 with
800MHz single core Cortex-A8 processor, 256MB DDR3, 64MB SPI flash,
8MB NOR Flash, mmc, usb, can, dual Ethernet ports.
For more information, look at HW user guide[1], Data manual[2].
Just add basic support for the moment.
[1] http://processors.wiki.ti.com/index.php/AM335x_Industrial_Communication_Engine_EVM_Rev2_1_HW_User_Guide
[2] http://www.ti.com/lit/ds/symlink/am3359.pdf
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Reviewed-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
When possible generic node names should be used. So change the node name
from ehrpwm to pwm.
Signed-off-by: Franklin S Cooper Jr <fcooper@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The binding definition for the PCF857x GPIO expanders doesn't mention
a "ti,pcf8575" compatible string. This is apparently because TI is
only a second source - there is no functional difference between
PCF8575 chips manufactured by TI and NXP, and the same board might be
populated with either depending on availability.
This is not a problem in practice because the I2C core uses
of_modalias_node() before matching drivers and this strips the
manufacturer name.
Signed-off-by: Ben Hutchings <ben.hutchings@codethink.co.uk>
Acked-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Signed-off-by: Filip Matijević <filip.matijevic.pz@gmail.com>
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Acked-by: Pavel Machek <pavel@ucw.cz>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Like the Nokia N900, the N950 has leds to show
the state of sys_clkreq and sys_off_mode pins.
A detailed description for the LEDs and
OMAP's sleep states can be found in Tony's
commit for the Nokia N900:
c1be2032f6
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add keypad matrix information based on data from
Nokia N950 Kernel.
Signed-off-by: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add regulator configuration as found in the
board files of Nokia's kernel.
Signed-off-By: Sebastian Reichel <sre@kernel.org>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The switch configuration for NAND is actually the other way round.
Also mention ON/OFF states as that is more natural to understand
(without the help of schematics) when compared to HIGH/LOW.
Signed-off-by: Roger Quadros <rogerq@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Few regulators information were missing from DT. Add those
missing regulators.
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
- fix USB adress register for Linksys Armada 388 based boards
- fix build warning in mvebu-mbus
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Merge tag 'mvebu-fixes-4.6-1' of git://git.infradead.org/linux-mvebu into fixes
mvebu fixes for 4.6 (part 1)
- fix USB adress register for Linksys Armada 388 based boards
- fix build warning in mvebu-mbus
* tag 'mvebu-fixes-4.6-1' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Correct unit address for linksys
bus: mvebu-mbus: use %pa to print phys_addr_t
Signed-off-by: Olof Johansson <olof@lixom.net>
SoCs with few board fixes and a fix for a long time hwmod bug:
- Fix cpsw_emac0 link type for baltos-ir5221
- Fix interrupt type for TWD
- Fix edma memcpy channel allocation for am43x
- Fix am43x-epos sycntimer32k by using the correct assigned clock
- Fix interconnect barrier for dra7
- Fix a long time hwmod bug for updating sysconfig register properly
- Fix flakey booting on dm814x where USB reset needs a delay
And there is one minor change that is not strictly a fix, but is
good to have for proper hardware detection:
- Detect dra7 silicon revision 2.0 properly
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Merge tag 'omap-for-v4.6/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
Fixes for omaps against v4.6-rc1. Mostly minor fixes for the newer
SoCs with few board fixes and a fix for a long time hwmod bug:
- Fix cpsw_emac0 link type for baltos-ir5221
- Fix interrupt type for TWD
- Fix edma memcpy channel allocation for am43x
- Fix am43x-epos sycntimer32k by using the correct assigned clock
- Fix interconnect barrier for dra7
- Fix a long time hwmod bug for updating sysconfig register properly
- Fix flakey booting on dm814x where USB reset needs a delay
And there is one minor change that is not strictly a fix, but is
good to have for proper hardware detection:
- Detect dra7 silicon revision 2.0 properly
* tag 'omap-for-v4.6/fixes-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: dts: am335x-baltos-ir5221: fix cpsw_emac0 link type
ARM: OMAP: Correct interrupt type for ARM TWD
ARM: DRA722: Add ID detect for Silicon Rev 2.0
ARM: dts: am43xx: fix edma memcpy channel allocation
ARM: dts: AM43x-epos: Fix clk parent for synctimer
ARM: OMAP2: Fix up interconnect barrier initialization for DRA7
ARM: OMAP2+: hwmod: Fix updating of sysconfig register
ARM: OMAP2+: Use srst_udelay for USB on dm814x
Signed-off-by: Olof Johansson <olof@lixom.net>
The ARM TWD interrupt is a private peripheral interrupt (PPI) and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED. For Tegra20/30 devices the PPI type cannot be
set and so when we attempt to set the type for the ARM TWD interrupt it
fails. This has gone unnoticed because it fails silently and because we
cannot re-configure the type it has had no impact. Nevertheless fix the
type for the TWD interrupt so that it matches the hardware configuration.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
For Tegra boards, the device-tree alias serial0 is used for the console
and so add the stdout-path information so that the console no longer
needs to be passed via the kernel boot parameters.
This has been tested on boards, tegra20-trimslice, tegra30-beaver,
tegra114-dalmore and tegra124-jetson-tk1.
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Acked-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Though the keyboard and other driver will continue to support the legacy
"gpio-key,wakeup", "nvidia,wakeup-source" boolean property to enable the
wakeup source, "wakeup-source" is the new standard binding.
This patch replaces all the legacy wakeup properties with the unified
"wakeup-source" property in order to avoid any further copy-paste
duplication.
Cc: Stephen Warren <swarren@wwwdotorg.org>
Cc: Thierry Reding <thierry.reding@gmail.com>
Cc: Alexandre Courbot <gnurou@gmail.com>
Cc: linux-tegra@vger.kernel.org
Signed-off-by: Sudeep Holla <sudeep.holla@arm.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Watchdog support was added to the timer block with Tegra30. Tegra20 did
not have this yet. However, the Tegra114 and Tegra124 DTSI files had an
entry in the compatible string list for "nvidia,tegra20-timer", but not
for "nvidia,tegra30-timer", which is why watchdog support isn't enabled
on them.
Fix this by adding an entry for "nvidia,tegra30-timer" to the compatible
string list of the timer block on Tegra114 and Tegra124.
This allows the watchdog to work on Jetson TK1.
Signed-off-by: Maarten Lankhorst <dev@mblankhorst.nl>
Signed-off-by: Thierry Reding <treding@nvidia.com>
This patch enables the APB DMA high speed UARTs of the Jetson TK1. So
far, they were only enabled in NVidia's official BSP.
Those additional UARTs are exposed on the expansion connector J3A2:
UART1:
Pin 41: BR_UART1_TXD
Pin 44: BR_UART1_RXD
UART2:
Pin 65: UART2_RXD
Pin 68: UART2_TXD
Pin 71: UART2_CTS_L
Pin 74: UART2_RTS_L
Signed-off-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
The comment about the 8250 vs. APB DMA-enabled UART devices that was
added for Tegra20 and Tegra30 in commit b6551bb933 ("ARM: tegra: dts:
add aliases and DMA requestor for serial controller") introduced a typo
that has since spread to various other DTS include files. Fix all
occurrences of this typo.
Signed-off-by: Ralf Ramsauer <ralf@ramses-pyramidenbau.de>
Acked-by: Stephen Warren <swarren@nvidia.com>
[treding@nvidia.com: amend subject, add commit message]
Signed-off-by: Thierry Reding <treding@nvidia.com>
Add the DT node for Timer12 present on DRA7 family of
SoCs. Timer12 is present in PD_WKUPAON power domain, and
has the same capabilities as the other timers, except for
the fact that it serves as a secure timer on HS devices
and is clocked only from the secure 32K clock.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The Timers 13 through 16 have been added previously in
disabled state. These timers are common timers that are
present on all DRA7 family of SoCs, so enable these
devices by default like the rest of the DMTimers.
Signed-off-by: Suman Anna <s-anna@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add nodes to represent all McASP ports in the dra7 family.
For system consistency use the eDMA for audio operations. sDMA would be
fine for 4/5/6/7/8 since their DAT port is not through L3 interconnect.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
rename the mcasp8_ahclk_mux to mcasp8_ahclkx_mux.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
[tony@atomide.com: updated for the unit offsets]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The assigned-clock* needs to be in the root of the device's node. If it is
in the sub-node the CCF will ignore it.
Since the clkout2 is used by the codec as MCLK, move the clock parent
selection to that node.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Since we switched to use eDMA we can now safely enable the FIFO in McASP.
This will reduce the chance of McASP level under/overflow.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
McASP3 does not support constant addressing mode on the DAT
port, so increment transfers must be used instead. This
restriction is also applicable for McASP1 and McASP2.
This DMA addressing constraint poses a major problem for sDMA
where constant addressing mode is used on the peripheral side.
Unfortunately, using increment transfers in sDMA comes with
important side effects.
The addressing mode used in eDMA is INC, so the silicon limitation
described above has no impact and the McASP3 DAT port can be
safely added by switching to eDMA instead of sDMA.
Signed-off-by: Misael Lopez Cruz <misael.lopez@ti.com>
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
DRA7 family has eDMA available along with the sDMA and in some cases it is
better suited for servicing peripherals.
Add the needed nodes for eDMA to be usable:
edma-tpcc, edma-tptc0/1 and the edma-xbar.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Move the sDMA xbar nodes under the L4 interconnect node.
Signed-off-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Add the device tree entries needed to support the Altera On-Chip
RAM EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add the device tree entries needed to support the Altera L2
cache EDAC on the Arria10 chip.
Signed-off-by: Thor Thayer <tthayer@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add support for the keys and flip-switches on the SoCFPGA SoCkit board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Add support for the blue LEDs on the SoCFPGA SoCkit board.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The socfpga_cyclone5.dtsi is included by all DTS files which describe boards
using the Cyclone V SoC. The Cyclone V SoC has two ethernet controllers and
different boards use none, one or both of them.
The /soc/ethernet@ff702000/{} node in socfpga_cyclone5.dtsi unconditionaly
enabled gmac0 interface, which is clearly wrong for those boards which use
gmac1 interface instead.
This patch removes the entire /soc/ethernet@ff702000/{} node from the
socfpga_cyclone5.dtsi file. This is correct, since all of the board which
include this file also have correct gmac0 or gmac1 node present in them.
Minor correction had to be done to EBV SoCrates, which didn't define PHY
mode explicitly, but inherited it from the socfpga_cyclone5.dtsi .
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The phy-addr property of stmmac is deprecated and the stmmac driver
does not use it either. On the contrary, the driver will warn if
this property is defined. Remove it.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Dinh Nguyen <dinguyen@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The PL330 DMA driver will not load on Arria10 without devicetree entries
for clocks and clock_names. This patch adds those entries. It also adds
the ninth interrupt, which is required for error detection.
Signed-off-by: Graham Moore <grmoore@opensource.altera.com>
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP5 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for DRA7 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for DM81x clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for AM43xx clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for AM33xx clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP4 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP2 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
Upcoming change to DT compiler is going to complain about nodes
which have a reg property, but have not defined the address in their
name. This patch fixes following type of warnings for OMAP3 clock nodes:
Warning (unit_address_vs_reg): Node /ocp/cm@48004000/clocks/dpll3_m2_ck
has a reg or ranges property, but no unit name
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warnings:
"bandgap has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warning:
"sound@0 has a unit name, but no reg property"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warnings:
"pmu has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warnings:
"i2c@0 has a unit name, but no reg property"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This patch fixes the following DTC warnings:
"pbias_regulator has a reg or ranges property, but no unit name"
Signed-off-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The CIU clock for the SD/MMC should be the sdmmc_clk and not the
sdmmc_free_clk. Also, add the correct phase shift the sdmmc_clk.
Signed-off-by: Dinh Nguyen <dinguyen@opensource.altera.com>
The Orange Pi One SBC, is a stripped down version of the popular
Orange Pi PC. The one is a H3 based SBC, with 512M of RAM,
micro-sd slot, 1 host usb, 1 otg usb, hdmi and 100Mbit ethernet.
Signed-off-by: Hans de Goede <hdegoede@redhat.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This is w.r.t J6/J6eco: 32clk is pseudo (erratum i856) - clock source.
Errata i856 for the AM572x (DRA7xx) points out that the 32.768KHz external
crystal is not enabled at power up. Instead the CPU falls back to using
an emulation for the 32KHz clock which is SYSCLK1/610. SYSCLK1 is usually
20MHz on boards so far (which gives an emulated frequency of 32.786KHz)
Modelling the same in device tree.
Acked-by: Tero Kristo <t-kristo@ti.com>
Signed-off-by: Keerthy <j-keerthy@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The amount of available memory is clearly a board-specific value, so
the core per-soc dtsi should not define a default of any sort.
Therefore move the memory-nodes to the two board files.
Also fix the amount of memory on Kylin (512MB instead of 1GB).
While in most cases the bootloader will override this with the
actual amount of memory, there is no need to keep known wrong values
in the board-dts.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
After hooking up panel and backlight informations, enable the
edp on veyron chromebooks now.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Jerry and Speedy don't need any special handling wrt the backlight or
panel, so only need their backlight and panel-regulators hooked up.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Pinky boards don't have the hotplug pin connected. So remove the
hotplug pinctrl setting and enable the force-hpd option, to allow
them to find the display too.
While on speedy boards, the hotplug pin is connected, judging by comments
in a chromeos change it seems the "panels HPD voltage is too low to be
detected", so it also needs the forced hotplug, as we of course also know
that a display is connected.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
The pwm for Minnie's backlight needs to be above 1%, so adapt the start
of non-zero brightness accordingly. Minnie is also using a different
panel, so re-set the compatible property.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
The panel which jaq uses requires the pwm duty cycle larger than 3%,
when the backlight status from power off to power on, otherwise the
backlight will flush, so we modify the second brightness-level to 8,
and when the backlight from power off to power on the pwm duty cycle
will larger than 3%.
Signed-off-by: Caesar Wang <wxt@rock-chips.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Many Veyron chromebooks share the same panel type, so define the core
settings for all of them and allow the few runaways to override it later.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
The panels need a bit of time to actually turn on. If this isn't
observed, this results in problems when trying talk to the panels
and thus produces detection errors. 100ms seem to be a safe value
for the time being.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
The edp hotplug pin is fixed on the soc side, anybody wanting to use it
will need the same definition anyway, so move it to a common location.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Add the rk3288 edp node and its hooks into the display-subsystem.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
Add the core device node of the edp-phy on rk3288 socs.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Douglas Anderson <dianders@chromium.org>
The cpu_leakage efuse on rk3288 did get it right including the
unitname but on both rk3066a and rk3188 it was missing, fix that.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
The mipi controller node does contain an unused reg property as well as
unnecessary #address-cells and #size-cells properties for subnodes
not using addresses, so remove those to also make dtc happy.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
Drop superfluous #address-cells and #size-cells, rename
key-nodes to individual names and also use the key constants
intead of numbers.
Reported-by: Julien Chauveau <chauveau.julien@gmail.com>
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
The usbphy subnodes do have a reg property but no unitname, add them.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
The power-domain sub-nodes do have reg properties, but so far are
missing the expected unit names. So add the missing ones.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Acked-by: Rob Herring <robh@kernel.org>
In Cygnus SOC touch screen controller registers are shared with ADC and
flex timer. Using readl/writel could lead to race condition. So touch
screen driver is enhanced to support register access using syscon framework
API's to take care of mutually exclusive access.
Signed-off-by: Raveendra Padasalagi <raveendra.padasalagi@broadcom.com>
Reviewed-by: Ray Jui <ray.jui@broadcom.com>
Reviewed-by: Scott Branden <scott.branden@broadcom.com>
Acked-by: Rob Herring <robh@kernel.org>
Acked-by: Florian Fainelli <f.fainelli@gmail.com>
Signed-off-by: Dmitry Torokhov <dmitry.torokhov@gmail.com>
This pull request want to land the analogix_dp driver into drm/bridge directory,
which reused the Exynos DP code, and add Rockchip DP support. And those
patches have been:
* 'drm-next-analogix-dp-v2' of github.com:yakir-Yang/linux:
drm: bridge: analogix/dp: Fix the possible dead lock in bridge disable time
drm: bridge: analogix/dp: add panel prepare/unprepare in suspend/resume time
drm: bridge: analogix/dp: add edid modes parse in get_modes method
drm: bridge: analogix/dp: move hpd detect to connector detect function
drm: bridge: analogix/dp: try force hpd after plug in lookup failed
drm: bridge: analogix/dp: add max link rate and lane count limit for RK3288
drm: bridge: analogix/dp: add some rk3288 special registers setting
dt-bindings: add document for rockchip variant of analogix_dp
drm: rockchip: dp: add rockchip platform dp driver
ARM: dts: exynos/dp: remove some properties that deprecated by analogix_dp driver
dt-bindings: add document for analogix display port driver
drm: bridge: analogix/dp: dynamic parse sync_pol & interlace & dynamic_range
drm: bridge: analogix/dp: remove duplicate configuration of link rate and link count
drm: bridge: analogix/dp: fix some obvious code style
drm: bridge: analogix/dp: rename register constants
drm/exynos: dp: rename implementation specific driver part
drm: bridge: analogix/dp: split exynos dp driver to bridge directory
After exynos_dp have been split the common IP code into analogix_dp driver,
the analogix_dp driver have deprecated some Samsung platform properties which
could be dynamically parsed from EDID/MODE/DPCD message, so this is an update
for Exynos DTS file for dp-controller.
Beside the backward compatibility is fully preserved, so there are no
bisectability break that make this change in a separate patch.
Reviewed-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Javier Martinez Canillas <javier@osg.samsung.com>
Signed-off-by: Yakir Yang <ykk@rock-chips.com>
Fix the following warnings from dtc by either adding or removing
the unit name from the node.
Warning (unit_address_vs_reg): Node /soc/flash-controller@40003000/flash@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@4 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@5 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@6 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /pca_buttons/button@7 has a unit name, but no reg property
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Fix the following warnings from dtc by either adding or removing
the unit name from the node.
Warning (unit_address_vs_reg): Node /soc/flash-controller@40003000/flash@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /gpio_joystick/button@0 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /gpio_joystick/button@1 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /gpio_joystick/button@2 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /gpio_joystick/button@3 has a unit name, but no reg property
Warning (unit_address_vs_reg): Node /gpio_joystick/button@4 has a unit name, but no reg property
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
DT nodes without reg properties should not have a unit address. This
fixes the following warnings from dtc.
Warning (unit_address_vs_reg): Node /soc/syscon@40043000/phy@004 has a
unit name, but no reg property
Warning (unit_address_vs_reg): Node /soc/syscon@40043000/dma-mux@11c has
a unit name, but no reg property
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add unit name to nvic to remove the following warning:
Warning (unit_address_vs_reg): Node /nv-interrupt-controller has a reg or ranges property, but no unit name
Also correct the node name to 'interrupt-controller'
while changing the line.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Acked-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Acked-by: Stefan Agner <stefan@agner.ch>
This adds a devicetree for the ARM RealView PBA8 platform,
also known as HBI-0178, "RealView Platform Baseboard for
Cortex-A8" and PBX-A9 "RealView Platform Baseboard
Explore for Cortex-A9"
Tested in QEMU with -M realview-pb-a8, as well as with
-M realview-pbx-a9 -smp cpus=2
Cc: Arnd Bergmann <arnd@arndb.de>
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Tested-by: Robin Murphy <robin.murphy@arm.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The ARM RealView Evaluation Baseboards are basically these:
- The original ARMv5 EB board with an ARM926EJ-S, ARM1136 or
ARM1176 core tile here described in arm-realview-eb.dts
no matter which of these core tiles is being used. This
can be emulated by QEMU "realview-eb" machine, which by
default will have the ARM926EJ-S core tile.
- The same board with one of three MPCore Core tiles:
ARM11MPCore, not to be confused with the similar ARM
PB11MPCore ARM11MPCore test system. This exist in
two revisions:
- Revision A modeled in arm-realview-eb-11mp.dts
- Revision B modeled arm-realview-eb-11mp-revb.dts
Revision B can be emulated by the QEMU
"realview-eb-mpcore" machine, but to match the hardware
also the argument -smp cpus=4 must be passed so that
it has four CPU cores, like the hardware.
There is also evidently from the code in the kernel a
Cortex-A9 core tile for the EB, and this is modeled in
arm-realview-eb-a9mp.dts based on the kernel boardfile.
I have not found a user guide for this EB core tile on
the ARM website and it seems uncommon. It is however
included for completeness.
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Cc: Marc Zyngier <marc.zyngier@arm.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This defines the CLCD block in the PB1176 and adds a standard
640x480 VGA panel to the device tree.
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Let's supply a standard VGA panel by default on the PB11MPCore,
this will work with most monitors. If more screen real estate is
desired, users can update the DPI definition.
Cc: Pawel Moll <pawel.moll@arm.com>
Cc: Rob Herring <robh@kernel.org>
Cc: Russell King <linux@arm.linux.org.uk>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
The flash on the Integrator was already defined by the device
tree, but VPP control and flash protection was in the
boardfiles. Simply add the compatible string
"arm,versatile-flash" and the special add-on code for flash
programming voltage and protection kicks in in the MTD
layer.
Remove the board file code and augment the device tree in
one go for seamless transition.
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This moves the boardfile definition of the flash memory in the
Versatile board into the device tree. The flash was already
defined with the property "arm,versatile-flash" which was
not handled by the kernel: instead define it as compatible
also with "cfi-flash" so it detects properly, and delete the
corresponding boardfile code so we get a smooth transition.
The old compatible string "arm,versatile-flash" is reused to
indicate to the MTD physmap subsystem that this flash requires
special VPP handling. (See separate patch.)
Cc: Grant Likely <grant.likely@linaro.org>
Cc: Rob Herring <robh@kernel.org>
Cc: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Revert this commit to fix regressions on non-dragonboard MSM8974 boards.
This will be put back in after the correct fixes to the bam driver are
accepted that allow remote processor control of the main control registers.
This reverts commit 0a5d0f85bb.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
Revert this commit to fix regressions on non-dragonboard MSM8974 boards.
This will be put back in after the correct fixes to the bam driver are
accepted that allow remote processor control of the main control registers.
This reverts commit 62bc817922.
Signed-off-by: Andy Gross <andy.gross@linaro.org>
The generic operating points specified in rk3288.dtsi are specified by
Rockchip as conservative and for all cases.
In contrast the Veyron ChromeOS devices are supposed to use a special
chip variant often called rk3288-c and use different operating points
in their kernel also including a higher max frequency.
So override the operating points for veyron devices.
Signed-off-by: Heiko Stuebner <heiko@sntech.de>
Reviewed-by: Douglas Anderson <dianders@chromium.org>
This patch adds new ports-implemented mask, which is required to get
achi working on the mainline. Without this patch value read from
PORTS_IMPL register which is zero would not enable any ports for
software to use.
Fixes: 566d1827df ("libata: disable forced PORTS_IMPL for >= AHCI 1.3")
Cc: stable@vger.kernel.org # v4.5+
Signed-off-by: Srinivas Kandagatla <srinivas.kandagatla@linaro.org>
Reviewed-by: Andy Gross <andy.gross@linaro.org>
Signed-off-by: Tejun Heo <tj@kernel.org>
This patch adds MSHC (Mobile Storage Host Controller) DT node for
Exynos3250 SoC. MSHC is an interface between the system and the SD card.
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds the Device Tree source for Samsung ARTIK5 module[1]
based on Exynos3250 SoC. The ARTIK5 module includes the following
devices:
- Application Processor (Samsung Exynos3250)
- WiFi/BT Combo chip (Broadcom4354)
- PMIC (Samsung S2MPS14)
- eMMC (4GB)
- DRAM LPDDR3 (512MB)
- Connectors pin (60 Pins x 3 set)
Also, this patch adds the ARTIK5 evaluation board[2] dts file which includes
the ARTIK5 module[1] and have the devices such as sound codec, sd card port,
ethernet port, uart port and so on.
[1] https://www.artik.io/hardware/artik-5
[2] http://www.digikey.com/product-search/en?FV=ffecca14
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Jaehoon Chung <jh80.chung@samsung.com>
Signed-off-by: Andi Shyti <andi.shyti@samsung.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds the MSHC2 (Mobile Storage Host Controller) Device Tree node for
Exynos3250 SoC.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch add the UART2 Device Tree node for Exynos3250 SoC.
Signed-off-by: Pankaj Dubey <pankaj.dubey@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds initial pin configuration of MMC2 device on exynos3250-monk
board because the MMC2 gpio pin (gpk2[0-6]) are NC (not connected) state.
Suggested-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds initial pin configuration using pinctrl subsystem
to reduce leakage power-consumption of gpio pins in normal state.
All pins included in this patch are NC (not connected) pin.
Signed-off-by: Chanwoo Choi <cw00.choi@samsung.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
In Baltos iR5221 cpsw_emac0 is connected directly to the switch IC and
hence needs to be configured as "fixed-link".
Signed-off-by: Yegor Yefremov <yegorslists@googlemail.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The ARM TWD interrupt is a private peripheral interrupt (PPI) and per
the ARM GIC documentation, whether the type for PPIs can be set is
IMPLEMENTATION DEFINED. For OMAP4 devices the PPI type cannot be set and
so when we attempt to set the type for the ARM TWD interrupt it fails.
This has done unnoticed because it fails silently and because we cannot
re-configure the type it has had no impact. Nevertheless fix the type
for the TWD interrupt so that it matches the hardware configuration.
Reported-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Jon Hunter <jonathanh@nvidia.com>
Tested-by: Grygorii Strashko <grygorii.strashko@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
EDMA was allocating DMA channels 32 and 33 for memcpy usage, out of which
channel 33 is actually used by DES crypto engine. This bad allocation of
the channel causes a crash in the DES crypto engine, as the channel
gets configured for memcpy usage instead of hardware <-> memory DMA.
Fixed by allocating DMA channels 58 and 59 for memcpy usage (I2C0 RX/TX),
which are not used by anybody.
Fixes: cce1ee0001 ("ARM: DTS: am437x: Use the new DT bindings for
the eDMA3")
Cc: stable@vger.kernel.org # v4.4+
Signed-off-by: Tero Kristo <t-kristo@ti.com>
Suggested-by: Peter Ujfalusi <peter.ujfalusi@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
commit 55ee7017ee ("arm: omap2: board-generic: use omap4_local_timer_init
for AM437x") makes synctimer32k as the clocksource on AM43xx. By default
the synctimer32k is clocked by 32K RTC OSC on AM43xx. But this 32K RTC OSC
is not available on epos boards which makes it fail to boot.
Synctimer32k can also be clocked by a peripheral PLL, so making this as
clock parent for synctimer3k on epos boards.
Fixes: 55ee7017ee ("arm: omap2: board-generic: use omap4_local_timer_init for AM437x")
Cc: stable@vger.kernel.org # v4.4+
Reported-by: Nishanth Menon <nm@ti.com>
Signed-off-by: Lokesh Vutla <lokeshvutla@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
The USB2 port for Armada 38x is defined to be at 58000, not at
50000.
Cc: <stable@vger.kernel.org>
Fixes: 2d0a7addbd ("ARM: Kirkwood: Add support for many Synology NAS devices")
Signed-off-by: Patrick Uiterwijk <patrick@puiterwijk.org>
Acked-by: Imre Kaloz <kaloz@openwrt.org>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Commit be3d7d023b ("ARM: kirkwood: Add DTS file for NSA320")
created the new file kirkwood-nsa320.dts but did not
add it to the Makefile.
Fixes: be3d7d023b ("ARM: kirkwood: Add DTS file for NSA320")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Commit 2d0a7addbd ("ARM: Kirkwood: Add support for many Synology
NAS devices") created the new file kirkwood-ds112.dts but did not
add it to the Makefile.
Fixes: 2d0a7addbd ("ARM: Kirkwood: Add support for many Synology NAS devices")
Signed-off-by: Heinrich Schuchardt <xypron.glpk@gmx.de>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Some of the GPIO configs were wrong in the submitted DTS files,
this patch fixes all affected boards.
Signed-off-by: Imre Kaloz <kaloz@openwrt.org>
Cc: <stable@vger.kernel.org> # v4.1 +
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Enable adc1 on LPC4350 Hitex Evalution board. This board has a
10k potensiometer (R26) connected to ADC1 channel 2.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Enable adc0 on EA4357 dev kit. This kit has a 22k
potentiometer (R94) connected on ADC0 channel 3.
Signed-off-by: Joachim Eastwood <manabian@gmail.com>
Add an entry for the hardware monitoring MCU
[gregory.clement@free-electrons.com: rename the title to use the
"standard" format]
Signed-off-by: Adam Baker <linux@baker-net.org.uk>
Signed-off-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Add node for chipid device in order to have access to the CIDR and EXID
values.
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
This SFR node is looked up by the I2S controller driver to tune the
SFR_I2SCLKSEL register.
Signed-off-by: Cyrille Pitchen <cyrille.pitchen@atmel.com>
Signed-off-by: Ludovic Desroches <ludovic.desroches@atmel.com>
Acked-by: Alexandre Belloni <alexandre.belloni@free-electrons.com>
Acked-by: Rob Herring <robh@kernel.org>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Use the <dt-bindings/interrupt-controller/arm-gic.h> header for
generating the flags for the first cell of the interrupt
definitions.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Use the <dt-bindings/gpio/gpio.h> header instead of using
hardcoded values for the GPIO flags. Eradicate the totally
bogus "0x4" flag used and set that to GPIO_ACTIVE_HIGH as is
proper, switch the inverted card detect on the Snowball to
flag using GPIO_ACTIVE_LOW instead of using the MMC-specific
inversion flag.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Add a dts node entry and enable the HDMI CEC device present in the Exynos4
family of SoCs.
Signed-off-by: Marek Szyprowski <m.szyprowski@samsung.com>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
[k.kozlowski: Put the node in alphabetical order]
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
This patch adds HDMI CEC node specific to the Exynos4210/4x12 SoC series.
Signed-off-by: Kamil Debski <kamil@wypas.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Add pinctrl nodes for the HDMI CEC device to the Exynos4210 and
Exynos4x12 SoCs. These are required by the HDMI CEC device.
Signed-off-by: Kamil Debski <kamil@wypas.org>
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Enable the Security SubSystem (SSS) on Exynos4412-based Odroid boards
to provide hardware acceleration for AES operations.
Suggested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Tested-by: Tobias Jakobi <tjakobi@math.uni-bielefeld.de>
Enable the Security SubSystem (SSS) on Trats2 (Exynos4412) board to
provide hardware acceleration for AES operations.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
Add Security SubSystem (SSS) node to Exynos4 which provides hardware
acceleration of AES operations.
Signed-off-by: Krzysztof Kozlowski <k.kozlowski@samsung.com>
Reviewed-by: Javier Martinez Canillas <javier@osg.samsung.com>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
The clock-output-names property is left in place for the zb_clk which is
thus treated as a special case as the MSTP clock driver (clk-mstp.c)
explicitly looks for a clock with node name zb_clk for the r8a73a4 and
sh73a0 SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
The clock-output-names property is left in place for the zb_clk which is
thus treated as a special case as the MSTP clock driver (clk-mstp.c)
explicitly looks for a clock with node name zb_clk for the r8a73a4 and
sh73a0 SoCs.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node. Accordingly, remove the unnecessary
clock-output-names properties and as necessary update the node names.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
* Fixed rate and fixed factor clocks do not require an
clock-output-names property.
* Since 07705583e9 ("clk: shmobile: div6: Make clock-output-names
optional") Renesas div6 clocks do not require a clock-output-names
property.
In the above cases there is only one clock output and its name is taken
from that of the clock node.
Accordingly, remove the unnecessary clock-output-names properties and
as necessary the nodes.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the kzm9d device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the kzm9g device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the silk device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the alt device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the gose device tree to use the generic
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the porter device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the koelsch device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Since 16ccaf5bb5 ("pinctrl: sh-pfc: Accept standard function, pins and
groups properties") renesas pfc drivers accept generic "function", "pins"
and "groups" properties.
This patch updates the marzen device tree to use the generic properties.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Acked-by: Geert Uytterhoeven <geert+renesas@glider.be>
Bjorn Andersson