This patch enables MSM8974 build support.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds basic board support for APQ8074 Dragonboard
which belongs to the Snapdragon 800 family.
For now, just support a basic machine with device tree.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
[olof: Split off SoC and board support in separate patches]
Signed-off-by: Olof Johansson <olof@lixom.net>
* Add Device Tree Support
* Remove platform data mapbase and irqs fields
* Remove platform data scbrr_algo_id field
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuYavAAoJENfPZGlqN0++iBQP/iRLdbZzrBtIqfPOAx7kOKC5
14kMul6tggT556xW++JhpUR/s5HdGZoUwq2XhWbzMm9rhE9FFsIOsjSROU9qwItG
4indJRS7p/2/c0vVD988QcgOK9yD++t4hMM42lZ4FsTZL7RT7t5di/Dx2OP8OyU8
LwTLYNRM8icePh+KVtEXyFKjCu22/tuj8FyPJoSruJPsPkd3w8Wt9o7ZLqp58DkG
91EYVWzbKC9JOfXhW/nybDpLpaaNC/MaeIfh2K9HFhAUnhOYDJp1dU7xIz7Wj8/j
PS9RXuNr+Vyj0ov5Y5VqgFwXz1bPFBHsMXvnh7HBwNoaxK6Nvs9ZMREfVLvsAZCS
jiWIYJLozAQX+Xmj7oYBb1kUkEE/WE8ec5GufNp43Eg6mSWsEx/YVFvSfPO/PYvG
3be9jUglpZFmh9i2f2ZtB0AG2q45HieK8i9glufg+wkKnahhOYgynV4dxTvfIEts
qQCZSoAL8KbmrMZpsW0Q9D3SvEFxcuhEtVk8h6X2lg+XcjJ9dwbH8BsBCI8W6Y+m
tOc0yeK8DQhpNastoo1xATQO1MpSTqnSWwP7j6oAS4W44iuJmGLEYLiDCLuamOto
CzGBDCluic3vMMnr3BmJLd/8P+T7IxUZ/0W8aPX786sVBMjsNJPRlyal5sA4/EJl
7Swi8gxCsasfSQLbHsab
=IZCI
-----END PGP SIGNATURE-----
Merge tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/drivers
From Simon Horman:
Third Round of Renesas SH SCI Updates for v3.14
* Add Device Tree Support
* Remove platform data mapbase and irqs fields
* Remove platform data scbrr_algo_id field
* tag 'renesas-sh-sci3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
serial: sh-sci: Add OF support
serial: sh-sci: Add device tree bindings documentation
serial: sh-sci: Remove platform data mapbase and irqs fields
serial: sh-sci: Remove platform data scbrr_algo_id field
Signed-off-by: Olof Johansson <olof@lixom.net>
* Global
- Don't set plat_sci_port scbrr_algo_id field
- Declare SCIF register base and IRQ as resources
- Don't define SCIF platform data in an array
- Use macros to declare SCIF devices
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks
* r8a7778 (R-Car M1)
- Add sound SCU clock support
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuYCjAAoJENfPZGlqN0++5uEQAICvtZMbC5Q04G22ePlzTTk1
/AHZTLRifgo8nNvGi0vky5tt3fuLBmNTixNFF1qCT7gTy9J+CzNz0OmSbg7sWY3h
km8IrTVWfY7lCMQ7UxbHW/3KjEOLG371B2edVunTb9JYHrrCte0q+4I4A7xmV1HA
mwoF+tziXXK5xCo6P0iAL7bAV04AE/r1fUD/zuH8CSm8xS8FJ2z7ZD1EIxcMNMbb
Xl7J2NkP1ntlazrElupuYxY+zDImI1mc0FIBtkV+ft4C2REKCs1q9fGC0xq+hN10
EkO0WYqezphcwSHXiHqApcjBwKHZoI6W+VmISl197FsY5zbtqLwpD+8mHeqd+WuG
qqK67m6BrcXTmM5pdsxy7QF81FdETX1e14zVkRaNBxw08kkFYbndFJz4ffNPIWUq
9N3q7Do8vZCnksM9XxQ95mpLIvfM8itlf4FDGr0O0ACEu+uQfUczXykSJVx5sGqu
0SV8ESCb3LRpRCGbwEIUgMDHM36aESqaIOWbmK6QHoTYWlg9Ka88dB2s2We71yuS
+PRZ7CpIsWMe7zb30TuiBPokYloHneiIVRf4RJWeGsyCgkN0DfkxorHK9UB7Adzy
jmkaqp5ebQ8CQplIVgldCcJngi2PmbUWeJcKlSNfg8aVpl8BRW8/Xv9RFuL8x/Cc
3jmFoXD12pJavs8T9dgi
=7k3L
-----END PGP SIGNATURE-----
Merge tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/soc
From Simon Horman:
Third Round of Renesas ARM Based SoC Updates for v3.14
* Global
- Don't set plat_sci_port scbrr_algo_id field
- Declare SCIF register base and IRQ as resources
- Don't define SCIF platform data in an array
- Use macros to declare SCIF devices
* r7s72100 SoC (RZ/A1H)
- Add i2c clocks
* r8a7778 (R-Car M1)
- Add sound SCU clock support
* tag 'renesas-soc3-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (43 commits)
arm: shmobile: r7s72100: add i2c clocks
ARM: shmobile: r8a7791: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7740: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a73a4: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7778: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r7s72100: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: sh73a0: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7790: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7791: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7778: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Don't set plat_sci_port scbrr_algo_id field
ARM: shmobile: r8a7779: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7740: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a73a4: Declare SCIF register base and IRQ as resources
ARM: shmobile: r7s72100: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh73a0: Declare SCIF register base and IRQ as resources
ARM: shmobile: sh7372: Declare SCIF register base and IRQ as resources
ARM: shmobile: r8a7790: Don't define SCIF platform data in an array
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the mmio architected timer node.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This doesn't need to be a def_bool y. Instead we can have every
DT supported platform select ARCH_MSM_DT and we achieve the same
thing with less chance of conflicts.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add the restart node so we can reboot the device.
Signed-off-by: Stephen Boyd <sboyd@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the Snapdragon 800 MSM8974 SoC, used on the Dragonboard
and others. Board support added in separate patch.
Signed-off-by: Rohit Vaswani <rvaswani@codeaurora.org>
Acked-by: Kumar Gala <galak@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
[olof: split off SoC support in separate patch]
Signed-off-by: Olof Johansson <olof@lixom.net>
Fix the following warning when !CONFIG_MMC:
arch/arm/mach-msm/board-trout.c: In function 'trout_init':
arch/arm/mach-msm/board-trout.c:67:6: warning: unused variable 'rc' [-Wunused-variable]
int rc;
^
Also, while we're here, rework explicit printk(KERN_CRIT..) to use
pr_crit.
Signed-off-by: Josh Cartwright <joshc@codeaurora.org>
Signed-off-by: David Brown <davidb@codeaurora.org>
Signed-off-by: Olof Johansson <olof@lixom.net>
This commit adds the two external clock outputs available on A20 to
its device tree. A dummy fixed factor clock is also added to serve as
the first input of the clock outputs, which according to AW's A20 user
manual, is the 24MHz oscillator divided by 750.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Device tree naming conventions state that node names should match
the nodes function. Change external low speed oscillator node name
to match.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This patch adds the clock output pin options on the A20.
The 2 pins can output a configurable clock to be used by
external modules. This is used on the CubieTruck, to supply
a 32768 Hz low power clock to the onboard Wifi+BT module.
Signed-off-by: Chen-Yu Tsai <wens@csie.org>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
On Allwinner sun7i (A20) SoCs, the SMP operations are implemented in
u-boot, and exposed to the kernel through PSCI.
We thus need to enable PSCI support for Allwinner SoCs so that the
kernel uses it to bring up the additionnal cores.
Signed-off-by: Signed-off-by: Zalan Blenessy <zalan.blenessy@gmail.com>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
The current code selects ARCH_HAS_RESET_CONTROLLER, that enables the
RESET_CONTROLLER option by default, but doesn't select it, so a configuration
might unselect it, leading to compilation error.
Explictly select RESET_CONTROLLER so that we can't have this breakage anymore.
Reported-by: Emilio López <emilio@elopez.com.ar>
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
plat/regs-ata.h is used only by Samsung PATA driver.
Move this file to the drivers folder to remove platform
dependency required for multiplatform support.
Signed-off-by: Sachin Kamat <sachin.kamat@linaro.org>
Reviewed-by: Jingoo Han <jg1.han@samsung.com>
Signed-off-by: Tejun Heo <tj@kernel.org>
Improve the comment of SW workaround for CCM lpm issue using
hardware errata description to avoid confusion.
ERR007265: CCM: When improper low-power sequence is used, the SoC
enters low power mode before the ARM core executes WFI.
Software workaround:
1) Software should trigger IRQ #32 (IOMUX) to be always pending
by setting IOMUX_GPR1_GINT.
2) Software should then unmask IRQ #32 in GPC before setting CCM
Low-Power mode.
3) Software should mask IRQ #32 right after CCM Low-Power mode is
set (set bits 0-1 of CCM_CLPCR).
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
For ccm clock gate, both 2b'11 and 2b'01 should be treated
as clock enabled, see below description in CCM, whenver CPU
trys to check clock gate's status, system will be in run mode.
2b'00: clock is off during all modes;
2b'01: clock is on in run mode, but off in wait and stop mode;
2b'10: Not applicable;
2b'11: clock is on during all modes, except stop mode.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Common clk framework will disable unused clks in late init only if
they are enabled by default and no one is using it, so we need to
add is_enabled callback for clk framework to get clks' status.
PFD clocks are enabled by hardware reset, so we need to add
interface for common clk framework to disable those unused ones for
saving power.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
PFUZE100 regulator is commonly found on mx6 based designs.
Add support for it.
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Let MX35 and MX50 device tree support be built by default.
Generated by doing:
- Selected CONFIG_MACH_IMX35_DT and CONFIG_SOC_IMX50 via 'make menuconfig'
- make savedefconfig
- cp defconfig arch/arm/configs/imx_v6_v7_defconfig
Signed-off-by: Fabio Estevam <fabio.estevam@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Update the IMX v6/v7 defconfig for the SolidRun HummingBoard:
- Add AT803X ethernet phy
- Add consumer IR devices
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
We are missing spba clock in imx6sl's clock tree, thus add it.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
SPDIF can derive a TX clock for playback from one of its clock sources --
spdif root clock to match its supporting sample rates. So this patch set
the spdif root clock's parent to pll3_pfd3_454m since the pll3_pfd3_454m
can approximately meet its sample rate requirement.
Signed-off-by: Nicolin Chen <Guangyu.Chen@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
0-DAY kernel build testing backend reports the following.
scripts/checkpatch.pl 0001-ARM-imx-add-support-code-for-IMX50-based-machines.patch
# many are suggestions rather than must-fix
ERROR: Use of const init definition must use __initconst
#80: arch/arm/mach-imx/mach-imx50.c:26:
+static const char *imx50_dt_board_compat[] __initdata = {
While at it, fix the error globally for IMX platform.
Reported-by: Fengguang Wu <fengguang.wu@intel.com>
Acked-by: Greg Ungerer <gerg@uclinux.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ldb_di0_gate is registerd with the clk index of IMX5_CLK_LDB_DI1_GATE,
thus the DI0 interface will be turned off inadvertently during boot.
Signed-off-by: Lothar Waßmann <LW@KARO-electronics.de>
Reviewed-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
This patch sets the parent of CAN peripheral clock (a.k.a. CPI clock) to the
lp_apm clock, which has a rate of 24 MHz.
In the CAN world a base clock with multiple of 8 MHz is suited best for all CIA
recommented bit rates. Without this patch the CAN peripheral clock on i.MX53
has a rate of 66.666 MHz which produces quite large bit rate errors.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
MFN bit 9 on i.MX27 has a different meaning than in other SOCs. This
is a just sign bit. This patch makes different calculation for i.MX27.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Sascha Hauer <s.hauer@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
According to the i.MX50 Rev. 1 and i.MX53 Rev. 2.1 datasheet the lp_apm_sel is
bit 10 in the CCM_CCSR register not bit 9. On the i.MX51 it's bit 9.
This patch fixes this issue.
Signed-off-by: Marc Kleine-Budde <mkl@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Add SATA PHY clock which are derived from the USB PHY1 clock. Note that this
patch derives the SATA PHY clock from USB PHY1 clock gate so that the SATA
driver can ungate both the SATA PHY clock and USB PHY1 clock for the SATA to
work correctly.
Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Richard Zhu <r65037@freescale.com>
Cc: Tejun Heo <tj@kernel.org>
Cc: Linux-IDE <linux-ide@vger.kernel.org>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Instead of selecting PINCTRL on individual SoC, let's select it at IMX
sub-architecure level.
While at it, it also adds the missing PINCTRL_IMX50 selection for
SOC_IMX50.
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
ARM clock is sourcing from pll1_sw, and pll1_sw can be either from
pll1_sys or step, so we should enable arm clock during clock
initialization instead of pll1_sys, otherwise, arm clock's usecount
would be incorrect and PLL1 will never be disabled even it is not
used.
Signed-off-by: Anson Huang <b20788@freescale.com>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Use clock defines in order to make devicetrees more
human readable.
Signed-off-by: Lucas Stach <l.stach@pengutronix.de>
Signed-off-by: Shawn Guo <shawn.guo@linaro.org>
Due to incorrect clock specified in MDMA0 node, using MDMA0 controller
could cause system failures, due to wrong clock being controlled. This
patch fixes this by specifying correct clock.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Acked-by: Mike Turquette <mturquette@linaro.org>
[t.figa: Corrected commit message and description.]
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
The chosen nodes are nowadays pretty useless, since they will be overriden by
the bootloader anyway.
We can thus safely remove them.
Signed-off-by: Maxime Ripard <maxime.ripard@free-electrons.com>
Allwinner sunXi SoCs DT changes for clocks
This contains the DT parts of the "[PATCH v3 00/13] clk: sunxi: add PLL5
and PLL6 support" series. It adds DT nodes for PLL4/5/6 and mod0 clocks
on most sunxi platforms.
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Fixup I2C device on defconfig
- Add gpio regulator support on defconfig
* r8a7791 (R-Car M2) based Koelsch board
- Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
- Enable CONFIG_PACKET in defconfig
- Enable Ether in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Enable backlight control in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuP0OAAoJENfPZGlqN0++MhsP/iV7i5qhbzKV6oPVFlBjpgMk
cp/6KikJ/9e5Nz8nGd1Q3n22/Vkw+U2JYQ0wkofJerO4AEm/Ikwf1FSRlDG4l1OR
q4/a8/ajIkZaExiztXQgwN73AyAE0vo8TWq+7qRlz6pmar8F3q32Lp1PwS7qK5zJ
NfK/JkiYJ0wH1X9Z3l3oHvKKZtoveTBYUyP/wYyfipbmesumpytWESQHWvANm0LQ
WL5haaT2F0auDLkMxnb9yIx+334oVDeRIyD/iDb3pu5OvA2Q1Xa5xWrnRYXSkOpq
UfylrS2N5LEs2teHfHiU2Rce7PDtml5TDv+uORrqMd/l76+huJYmxZcMK88NepGb
Si5Zl2GTdueAwdS1B0qdDQvkz7RYeETVwBagtQ16P6bWPbExivtqJa4zhdlm43jM
tGvU6MVv5nrqgPLUOoFRJuwutU3mIQ8+36i+MMKnePjoEvG2iCgb/X/F5x2M3Cag
xs6hsLlAkNOC/yr2A5DABzb3FPjhKvEjy0yNJFmJ0pyiHcUKuxO4HPEh74Dp0TTm
q3UHLkjXBQf5IZo0U7qUuFL+rjz6u3EbvOgddfPnPCMKJIdEWe6OtYK2N2X+BFTJ
g1tGWA2PeyO7XrNzEJ2Z5x10VTGjWywgAHRVmdBXJd0kIOARYdXRqB0Vy+M7LwKL
5mjeK9mRR3u1Lbouuzs3
=M9DB
-----END PGP SIGNATURE-----
Merge tag 'renesas-defconfig2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
From Simon Horman:
Second Round of Renesas ARM Based SoC Defconfig Updates for v3.14
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Fixup I2C device on defconfig
- Add gpio regulator support on defconfig
* r8a7791 (R-Car M2) based Koelsch board
- Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
- Enable CONFIG_PACKET in defconfig
- Enable Ether in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Enable backlight control in defconfig
* r8a7740 (R-Mobile A1) based Armadillo board
- Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
* tag 'renesas-defconfig2-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: koelsch: Do not disable CONFIG_{INOTIFY_USER,UNIX} in defconfig
ARM: shmobile: koelsch: Enable CONFIG_PACKET in defconfig
ARM: shmobile: armadillo800eva: Enable backlight control in defconfig
ARM: shmobile: Koelsch: enable Ether in defconfig
ARM: shmobile: genmai: Rename ARCH_SHMOBILE to ARCH_SHMOBILE_LEGACY
ARM: shmobile: lager: fixup I2C device on defconfig
ARM: shmobile: lager: add gpio regulator support on defconfig
Signed-off-by: Olof Johansson <olof@lixom.net>
* Global
- Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Add Multiplatform support
- Add Reference DT
* r8a7791 (R-Car M2) based Koelsch board
- Add pinctrl_register_mappings() for Koelsch
- Hook up SW30-SW36 on Koelsch
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Add Multiplatform support
- Set .debounce_interval for GPIO keys
- Add SW2 to GPIO keys
- Add Led 6, 7 and 8 support
- Add reference DT
- Enable PFC/GPIO
* r8a7790 (R-Car H2) based Lager board
- Add gpio/fixed regulator for SDHI
- Add SPI FLASH support on QSPI
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Set .debounce_interval for GPIO keys
* r8a7778 (R-Car M1) based Bock-W board
- bockw: remove unused RSND_SSI_CLK_FROM_ADG
- Set .debounce_interval for GPIO keys
- Correct FPGA ioremap area
- Use regulator for MMCIF
* r8a7740 (R-Mobile A1) based Armadillo board
- Correct FSI address size
* sh7374 (SH-Mobile AP4) based Mackerel board
- Use pinconf API to configure pin pull-down
- clk_round_rate() can return a zero to indicate an error
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSt5cHAAoJENfPZGlqN0++xIoP/jBunLyY+xAZ+06gukAdKEw4
hLoUH55GsvpaL5cuDT+LSXWafIol4A/wvME5sZJsKoCHRnDqQYKvyE7hDLIlvLRI
KvcmFvdUcN6plbD/wz/SPzur/Lq3+DcX4ep8pmI7OUXupYWomibwylv/5UgY++PN
Uymmre4CiHK7/wzWOyS79ujcGzdwk4o1ari5P2lC4fUlVM7jZ7DQswglo+jGxscw
CXHtEfqto4NEh2+05sAGdmRHwb3xwOndPYwHaFWy+X6uce/BZXsgDipWihHI5ZKr
FT+TemFlYwXc2In2F/E4T7aXqNDXSjEcX/x2/VHS5W2EoWbSk+Mz6zlFZduAv4oG
c35AQjHMktlo6voZm0L4WgH0JYT4dyu6DJG3mo7adRyYKvjv/OC48wt4jhYa0LGZ
XLcYBoaK1zqpG2M6ZIv138a9krGtkfSCy/Pt7YQ4WpA8CQyJlYqaoW9Yrpkhw13b
OcO22myGbjMnxTwpqS9rwDPnNR2PjG9ExDHmO3x4k+zsLqyJHxzv6ikKJWl0eiUF
JUv/mzxiaYsOBiMTYYuueNYegzhzGiW8jzp+j6E3WXTPxwCP2It8/31aBfyuaKcG
B807//VKcHulPONe3emBK7I2KzsJ6UOUs7iHuqrdwoglQKqMC0iyy2/ZFXbu7JJU
cMlHObCNFOGPZxKGsYXG
=5zhn
-----END PGP SIGNATURE-----
Merge tag 'renesas-boards-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/boards
From Simon Horman:
Renesas ARM based SoC board updates for v3.14
* Global
- Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
* r7s72100 SoC (RZ/A1H) based Genmai Board
- Add Multiplatform support
- Add Reference DT
* r8a7791 (R-Car M2) based Koelsch board
- Add pinctrl_register_mappings() for Koelsch
- Hook up SW30-SW36 on Koelsch
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Add Multiplatform support
- Set .debounce_interval for GPIO keys
- Add SW2 to GPIO keys
- Add Led 6, 7 and 8 support
- Add reference DT
- Enable PFC/GPIO
* r8a7790 (R-Car H2) based Lager board
- Add gpio/fixed regulator for SDHI
- Add SPI FLASH support on QSPI
- Mark GPIO keys as wake-up sources
- Use ->init_late()
- Set .debounce_interval for GPIO keys
* r8a7778 (R-Car M1) based Bock-W board
- bockw: remove unused RSND_SSI_CLK_FROM_ADG
- Set .debounce_interval for GPIO keys
- Correct FPGA ioremap area
- Use regulator for MMCIF
* r8a7740 (R-Mobile A1) based Armadillo board
- Correct FSI address size
* sh7374 (SH-Mobile AP4) based Mackerel board
- Use pinconf API to configure pin pull-down
- clk_round_rate() can return a zero to indicate an error
* tag 'renesas-boards-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (75 commits)
ARM: shmobile: lager: add gpio/fixed regulator for SDHI
ARM: shmobile: bockw: remove unused RSND_SSI_CLK_FROM_ADG
ARM: shmobile: armadillo: fixup FSI address size
ARM: Kconfig: Mention Renesas ARM SoCs instead of SH-Mobile
ARM: shmobile: mackerel: Use pinconf API to configure pin pull-down
ARM: shmobile: Lager:add SPI FLASH support on QSPI
ARM: shmobile: mackerel: clk_round_rate() can return a zero to indicate an error
ARM: shmobile: Add pinctrl_register_mappings() for Koelsch
ARM: shmobile: Use ->init_late() on Lager
ARM: shmobile: Hook up SW30-SW36 on Koelsch
ARM: shmobile: koelsch: mark GPIO keys as wake-up sources
ARM: shmobile: Use ->init_late() on Koelsch
ARM: shmobile: lager: mark GPIO keys as wake-up sources
ARM: shmobile: r7s72100 Genmai Multiplatform
ARM: shmobile: r7s72100 Genmai DT reference C bits
ARM: shmobile: r7s72100 Genmai DT reference DTS bits
ARM: shmobile: Initial r8a7791 and Koelsch multiplatform support
ARM: shmobile: koelsch: set .debounce_interval
ARM: shmobile: lager: set .debounce_interval
ARM: shmobile: bockw: add pin pull-up setting for SDHI
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This patch adds low level debug uart support to Broadcom mobile based
SOCs.
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Tested-by: Markus Mayer <markus.mayer@linaro.org>
Acked-by: Olof Johansson <olof@lixom.net>
Tested-by: Matt Porter <mporter@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There are two SCHED_HRTICK config entries in Kconfig.
This looks like a merge mistake. Fix it.
Signed-off-by: Axel Lin <axel.lin@ingics.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Modern ARM CPUs can perform efficient unaligned memory accesses in
hardware and this feature is relied up on by code such as the dcache
word-at-a-time name hashing.
This patch selects HAVE_EFFICIENT_UNALIGNED_ACCESS for these cores and
reworks the kconfig select logic for DCACHE_WORD_ACCESS to use the new
symbol.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With commit 11ec50caed ("word-at-a-time: provide generic big-endian
zero_bytemask implementation"), the asm-generic word-at-a-time code now
provides a zero_bytemask implementation, allowing us to make use of
DCACHE_WORD_ACCESS on big-endian CPUs, providing our
load_unaligned_zeropad function is endianness-clean.
This patch reworks the load_unaligned_zeropad fixup code to work for
both big- and little-endian CPUs, then removes the !CPU_BIG_ENDIAN check
when selecting DCACHE_WORD_ACCESS.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The ASID allocator has to deal with some pretty horrible behaviours by
the CPU, so expand on some of the comments in there so I remember why
we can never allocate ASID zero to a userspace task.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Since we only clear entries in the ASID bitmap on a rollover event, the
bitmap tends to consist of a block of consecutive set bits followed by
a block of consecutive clear bits. The exception to this rule is for
ASIDs which have been carried over from a previous generation, but
these are bound by the number of CPUs.
This patch optimises our bitmap searching strategy, so that we search
from the last successful allocation, rather than search from index 1
each time we allocate a new ASID.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
With the new ASID allocation algorithm, active ASIDs at the time of a
rollover event will be marked as reserved, so active mm_structs can
continue to operate with the same ASID as before. This in turn means
that we don't need to worry about allocating a new ASID to an mm that
is currently active (installed in TTBR0).
Since updating the pgd and ASID is atomic on LPAE systems (by virtue of
the two being fields in the same hardware register), we can dispose of
the reserved TTBR0 and rely on whatever tables we currently have live.
Reviewed-by: Catalin Marinas <catalin.marinas@arm.com>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The definition of virt_addr_valid is that virt_addr_valid should
return true if and only if virt_to_page returns a valid pointer.
The current definition of virt_addr_valid only checks against the
virtual address range. There's no guarantee that just because a
virtual address falls bewteen PAGE_OFFSET and high_memory the
associated physical memory has a valid backing struct page. Follow
the example of other architectures and convert to pfn_valid to
verify that the virtual address is actually valid. The check for
an address between PAGE_OFFSET and high_memory is still necessary
as vmalloc/highmem addresses are not valid with virt_to_page.
Cc: Will Deacon <will.deacon@arm.com>
Cc: Nicolas Pitre <nico@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Laura Abbott <lauraa@codeaurora.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
When given a compound high page, __flush_dcache_page will only flush
the first page of the compound page repeatedly rather than the entire
set of constituent pages.
This error was introduced by:
0b19f93 ARM: mm: Add support for flushing HugeTLB pages.
This patch corrects the logic such that all constituent pages are now
flushed.
Cc: stable@vger.kernel.org # 3.10+
Signed-off-by: Steve Capper <steve.capper@linaro.org>
Acked-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The IDE code used to specify the IDE IRQs for chipsets operating in
legacy mode. This appears to no longer work, and this information must
be provided by the arch. Do so. This partially fixes CY82C693 (and
probably others) on Footbridge platforms.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The clockevents code was being told that the footbridge clock event
device ticks at 16x the rate which it actually does. This leads to
timekeeping problems since it allows the clocksource to wrap before
the kernel notices. Fix this by using the correct clock.
Fixes: 4e8d76373c ("ARM: footbridge: convert to clockevents/clocksource")
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: <stable@vger.kernel.org>
Cleanup the LEDs code to use ioremap()/writeb() to access the register.
This allows us to move the definitions out of a header file directly
into the ebsa285 support code.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Make pgd allocation retry on failure; we really need this to succeed
otherwise fork() can trigger OOMs.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Add a one-shot mode for the DC21285 timer. This allows us to use the
NO_HZ modes on this platform.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
This adds support for the Marvell Tauros3 cache controller which
is compatible with pl310 cache controller but broadcasts L1 cache
operations to L2 cache. While updating the binding documentation,
clean up the list of possible compatibles. Also reorder driver
compatibles to allow non-ARM derivated to be compatible to ARM
cache controller compatibles.
Signed-off-by: Sebastian Hesselbarth <sebastian.hesselbarth@gmail.com>
Reviewed-by: Mark Rutland <mark.rutland@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Enable the compiler intrinsic for byte swapping on arch ARM. This
allows the compiler to detect and be able to optimize out byte
swappings, and has a very modest benefit on vmlinux size (Linaro gcc
4.8):
text data bss dec hex filename
2840310 123932 61960 3026202 2e2d1a vmlinux-lart #orig
2840152 123932 61960 3026044 2e2c7c vmlinux-lart #builtin-bswap
6473120 314840 5616016 12403976 bd4508 vmlinux-mxs #orig
6472586 314848 5616016 12403450 bd42fa vmlinux-mxs #builtin-bswap
7419872 318372 379556 8117800 7bde28 vmlinux-imx_v6_v7 #orig
7419170 318364 379556 8117090 7bdb62 vmlinux-imx_v6_v7 #builtin-bswap
Signed-off-by: Kim Phillips <kim.phillips@freescale.com>
Reviewed-by: Nicolas Pitre <nico@linaro.org>
Acked-by: David Woodhouse <David.Woodhouse@intel.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
sync_cache_w already includes a dsb, so we can just use sev() directly
then following a cache-sync.
Acked-by: Dave Martin <Dave.Martin@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
These symbols are only referenced in this source file so can be made
static, and the efficiency table is constant data so can be declared as
such. This avoids polluting the global namespace and fixes warnings
from sparse.
The function arch_scale_freq_power() is still not prototyped or static,
this is a separate issue as this is overriding a weak symbol from the
scheduler which neglects to provide a prototype.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
There is a miscompilation of csum_tcpudp_magic() due to the way we pass
the asm() operands in. Fortunately, this doesn't affect the IP code,
but can affect anyone who passes ntohs(udp->len) as the length argument,
or protocols with more than 8 bits.
The problem stems from passing 16-bit operands into an asm() - GCC makes
no guarantees about what may be in the high 16-bits of such a register
passed into assembly which is in the "HI" machine mode.
Address this by changing the way we handle the 16-bit arguments - since
accumulating the protocol and length can never overflow, we can delegate
this to the compiler to perform, and then accumulate it into the
checksum inside the asm(), taking account of the endian-ness via an
appropriate 32-bit rotation.
While we are here, also realise that there's a chance to optimise this
a little: several callers from IP code pass a constant zero as the
initial sum. This is wasteful - if we detect this condition, we can
optimise away one instruction.
Tested-by: Maxime Bizon <mbizon@freebox.fr>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Set-associative caches on all v7 implementations map the index bits
to physical addresses LSBs and tag bits to MSBs. As the last level
of cache on current and upcoming ARM systems grows in size,
this means that under normal DRAM controller configurations, the
current v7 cache flush routine using set/way operations triggers a
DRAM memory controller precharge/activate for every cache line
writeback since the cache routine cleans lines by first fixing the
index and then looping through ways (index bits are mapped to lower
physical addresses on all v7 cache implementations; this means that,
with last level cache sizes in the order of MBytes, lines belonging
to the same set but different ways map to different DRAM pages).
Given the random content of cache tags, swapping the order between
indexes and ways loops do not prevent DRAM pages precharge and
activate cycles but at least, on average, improves the chances that
either multiple lines hit the same page or multiple lines belong to
different DRAM banks, improving throughput significantly.
This patch swaps the inner loops in the v7 cache flushing routine
to carry out the clean operations first on all sets belonging to
a given way (looping through sets) and then decrementing the way.
Benchmarks showed that by swapping the ordering in which sets and
ways are decremented in the v7 cache flushing routine, that uses
set/way operations, time required to flush caches is reduced
significantly, owing to improved writebacks throughput to the DRAM
controller.
Benchmarks results vary and depend heavily on the last level of
cache tag RAM content when cache is cleaned and invalidated, ranging
from 2x throughput when all tag RAM entries contain dirty lines
mapping to sequential pages of RAM to 1x (ie no improvement) when
all tag RAM accesses trigger a DRAM precharge/activate cycle, as the
current code implies on most DRAM controller configurations.
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Acked-by: Nicolas Pitre <nico@linaro.org>
Acked-by: Santosh Shilimkar <santosh.shilimkar@ti.com>
Reviewed-by: Dave Martin <Dave.Martin@arm.com>
Signed-off-by: Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We have a handy macro to replace open coded __cpuc_flush_dcache_area(()
and outer_clean_range() sequences. Let's use it. No functional change.
Signed-off-by: Nicolas Pitre <nico@linaro.org>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Clean up the setup ARM printks a bit. Add printk level to a few
that were missing (CPU: <...> ones, in particular), and switch from
printk(KERN_* ..) to pr_*().
Finally, un-wrap some long lines since it makes it harder to grep the
sources from where an error came from and tweak some cases of indentation.
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
Driver core clears the driver data to NULL after device_release
or on probe failure, so just remove it from here.
Driver core change:
"device-core: Ensure drvdata = NULL when no driver is bound"
(sha1: 0998d06310)
Signed-off-by: Michal Simek <michal.simek@xilinx.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
The only v7-M platform only has some unused stubs in its
mach/entry-macro.S file. So don't include it which allows efm32 to drop
the file.
Acked-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Uwe Kleine-König <u.kleine-koenig@pengutronix.de>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
We don't need the offset for the first function name in each backtrace
entry; this needlessly consumes screen space. This is virtually always
the first or second instruction in the called function.
Also, recognise stmfd instructions which include r10 as a valid stack
saving instruction, and when dumping the registers, dump six registers
per line rather than five, and fix the wrapping.
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
ioremap_cache is more aligned with other architectures. There are only
2 users of this in the kernel: pxa2xx-flash and Xen.
This fixes Xen build failures on arm64 caused by commit c04e8e2fe5 (arm64:
allow ioremap_cache() to use existing RAM mappings)
drivers/tty/hvc/hvc_xen.c:233:2: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration]
drivers/xen/grant-table.c:1174:3: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration]
drivers/xen/xenbus/xenbus_probe.c:778:4: error: implicit declaration of function 'ioremap_cached' [-Werror=implicit-function-declaration]
Signed-off-by: Rob Herring <rob.herring@calxeda.com>
Cc: Stefano Stabellini <stefano.stabellini@eu.citrix.com>
Acked-by: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will.deacon@arm.com>
Signed-off-by: Russell King <rmk+kernel@arm.linux.org.uk>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSt1TYAAoJEHm+PkMAQRiGvWgH/iWg8TmEWz4KUKuHthuUi0uh
9+2YDN+4k577Xa0obaG24giQeqkCdxMr3oJrS3FO9jeAmaNRHEGhxUPneisb7RtN
9jIVsz5bPa9/DcK9nqtaUQdvA0O5AWTE6AAPmwleTVy+8CygBo987T2uGELnQCSR
FrKCrMePc7Pj0uthMVXrpJ17Ffm/j7jkfRtPhrxHJyngh3jEux+tPbpynH/aKuO2
47unsSQimoFk7n2SPFvNu3E/vZE2xVbu5SH9MCl5yyiCifFjpi3B71LV/FW51lvm
cK8Jzn2BmYDygRFjnZfq4zJHqYJCBHzpjCLWmR37Dm/JS91aGq3+Cg0stDP8UTs=
=+Hcn
-----END PGP SIGNATURE-----
Merge tag 'v3.13-rc5' into next/boards
Need a newer base version to get a regulator fix for Samsung platforms that
they enable building in a defconfig.
Linux 3.13-rc5
the sparse IRQ conversion, fix DRA7 console output for earlyprintk,
and fix the LDP LCD backlight when DSS is built into the kernel and
not as a loadable module.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSvcG1AAoJEBvUPslcq6VzU+gP/0AvO/aJVJNt2rpjH13RSmyo
3omMN06pxyqYUgtr4rXY2av8okSmJXWGjtUYVRKry0uMfXjIFFf7PNUX6K3j82cC
kiYUsZ42WFUbQ5F5KptVYXXHk6FFgxHCh1lmtbL7ZwDttTdoqCNZ+s6ufeGFDNl8
93tTaBhuwbPOmTUXZdCnhcfiZ8jZS3ZOz/sVx98c31aQ1jtZU74HomJMGC4t5pFY
NPAkEMD3EJHdNTJfNc+wvpA/oEfCDqJSc83RmWGIcbFwihz++0dApKstZstVco4m
5pj2fKVUI4cpe0wxbdZJnQmzSOWLPCuDBoWNQ1MYrh6i6ykcMYibOXJyvNmLtd9Y
JtqAYao2+hfLlYlWiBCuFqkfdttYDl5aTkzimAzQGXU1l0VnnMa4VD+nUdpW8F/+
Nb8MckhukKnfHEjnCRwb3wgXJzOYlAg5iekUqo0y1bZWpBC8rUzgW2qDkAYXT+Ul
eRi4AEgrmPNkSvLFWSm1aWJSt2yP+Xd9fA+P7EUHmBMXYa7mQyxaI/Xpr/qO0Oqd
Ewm9BOoKzLKvn6IeOLQ4JgUERocbB0hH38efP6h/qf4LlFcygF5pAPfXNK3/WHlt
2gaVHCi4x4deFwZA/u2x0bDcwTebvTxZ7PZJftwI6O3KjSFGcxP6pN16cvtCJaOV
bt+CkiBjkFl7gNWhFiwa
=3A1e
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.13/intc-ldp-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
From Tony Lindgren:
Fix a regression for wrong interrupt numbers for some devices after
the sparse IRQ conversion, fix DRA7 console output for earlyprintk,
and fix the LDP LCD backlight when DSS is built into the kernel and
not as a loadable module.
* tag 'omap-for-v3.13/intc-ldp-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap:
ARM: OMAP2+: Fix LCD panel backlight regression for LDP legacy booting
ARM: OMAP2+: hwmod_data: fix missing OMAP_INTC_START in irq data
ARM: DRA7: hwmod: Fix boot crash with DEBUG_LL
+ v3.13-rc5
Signed-off-by: Olof Johansson <olof@lixom.net>
* r8a7790 (R-Car H2) based Lager board
- Correct SHDI resource sizes
This bug has been present since sdhi resources were added to the r8a7790 by
8c9b1aa418 ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT
templates") in v3.11-rc2.
* r8a7778 (R-Car M1) based Bock-W board
- Correct DMA mask
This resolves a regression introduced by 4dcfa60071
("ARM: DMA-API: better handing of DMA masks for coherent allocations")
in v3.12-rc1.
* r8a7740 (R-Mobile A1) based Armadillo board
- Add PWM backlight power supply
This resolves a regression introduced by 22ceeee16e
("pwm-backlight: Add power supply support") in v3.12.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.14 (GNU/Linux)
iQIcBAABAgAGBQJSuQF7AAoJENfPZGlqN0++83IP/3AyhSixjpxUagqxsOkI8FJu
uL5Z5gNVfV+/inNWptM94L/T5pZ9IL2uhcoDGKyISs78UMGCTh5gqwC8ZsXGm0IZ
3Y2nkgx4Ohgx+62KJLYt/by6RX+Hrx/O09E+1o7BAyF26Lq6ncKczrIR5+n7Sak5
mHea7P+uk2njVjj7oM1Sbvk+3wJ1yoEdRkI/s4iORA7sCgQTEyxMbIS2aDHOkRx1
3jwlA/BbXUCEeWf45TC7MQCd7OuHEj1bGGocdSC59wqvTLd+IFQviK+EHjAXgUIf
vnuTLpXZMihJ19FZbcOrEndjlM9W+opZ775x1IrKU+w/C9JmlI9Gf1D5IWxbTdD2
bQ/mXBHmFo9IMO+i/Q2mqfPYzAGCBpz7ITyt1IVzXd6EYVsPXYWzQsW+j+BE4vsp
XGhQ+vh0Au7o3KABnvjxVQvWIkZUpqGr4n3SKoJ74X1+eZOEyNQ31kg14zr5Xsz3
rAY9taP2r3uNZiaQJzFOsbaPKxe81pjbx34TmHiKEKzmdAhwKjeb94o2HkoY90z2
us3tBVjjIr9f4Yyc3JLB0VLRsfW4fu6ovzJYdxe2lo5EFpq8zlMVY4XbgP0QUFxD
tAHvO9FeS2jtxxk0OS7N2MiqWBmTTsluUuxu9cXyBO0afHVqWhhWR3Upkt82f46u
BGEKCgd9mXKP8M5FHTZE
=6ai1
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
From Simon Horman:
Second Round of Renesas ARM based SoC Fixes for v3.13
* r8a7790 (R-Car H2) based Lager board
- Correct SHDI resource sizes
This bug has been present since sdhi resources were added to the r8a7790 by
8c9b1aa418 ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT
templates") in v3.11-rc2.
* r8a7778 (R-Car M1) based Bock-W board
- Correct DMA mask
This resolves a regression introduced by 4dcfa60071
("ARM: DMA-API: better handing of DMA masks for coherent allocations")
in v3.12-rc1.
* r8a7740 (R-Mobile A1) based Armadillo board
- Add PWM backlight power supply
This resolves a regression introduced by 22ceeee16e
("pwm-backlight: Add power supply support") in v3.12.
* tag 'renesas-fixes2-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: fix shdi resource sizes
ARM: shmobile: bockw: fixup DMA mask
ARM: shmobile: armadillo: Add PWM backlight power supply
Signed-off-by: Olof Johansson <olof@lixom.net>
Signed-off-by: Olof Johansson <olof@lixom.net>
After commit 88f718e3fa
"ARM: pxa: delete the custom GPIO header" a compilation
error was introduced in the PXA25x gadget driver.
An attempt to fix the problem was made in
commit b144e4ab1e
"usb: gadget: fix pxa25x compilation problems"
by explictly stating the driver needs the <mach/hardware.h>
header, which solved the compilation for a few boards,
such as the pxa255-idp and its defconfig.
However the Lubbock board has this special clause in
drivers/usb/gadget/pxa25x_udc.c:
This include file has an implicit dependency on
<mach/irqs.h> having been included before <mach/lubbock.h>
was included.
Before commit 88f718e3fa
"ARM: pxa: delete the custom GPIO header" this implicit
dependency for the pxa25x_udc compile on the Lubbock was
satisfied by <linux/gpio.h> implicitly including
<mach/gpio.h> which was in turn including <mach/irqs.h>,
apart from the earlier added <mach/hardware.h>.
Fix this by having the PXA25x <mach/lubbock.h> explicitly
include <mach/irqs.h>.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Cc: Greg Kroah-Hartmann <gregkh@linuxfoundation.org>
Cc: Felipe Balbi <balbi@ti.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Olof Johansson <olof@lixom.net>
- remove <mach/regs-clock.h> for exynos
- remove <mach/regs-irq.h> for exynos
- local <mach/regs-pmu.h> into mach-exynos
- select PM_GENERIC_DOMAINS for ARCH_EXYNOS4
instead of each SOC_EXYNOS4XXX in Kconfig
- call pm_genpd_poweroff_unused() instead of via
exynos_pm_late_initcall() because no need to
handle whether CONFIG_PM_GENERIC_DOMAINS is enalbed
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStdAiAAoJEA0Cl+kVi2xqNQ4P/j+t1mbZWnn8n5iwDyEkS0cQ
xYH97eewSFFgbiO54eFCNM1xQoAyJhASxPuxi8wIVvYriOjgZ+IGsWXQqyGf0un9
Zui4v6dinuoQFqxhMsy10qSm4BH5URNlf8ApFFPdhReO3zNTD0SWzou3PAsFSoE4
DMCboHQ6z7ku+tELjN56fQHcDRmUx4MpHc4Mj57ESr4LXMHbajTQhfq1M+F//SWh
wnsuD1lFDDS2MnpRclhVajT7Rogl7CXVpXB8FYN6/ZxdwraJbPh3qpubsYVJpcwQ
Z0h0dXXPplw2HQRcruhSO5POEK16Q5TtFRw2YlUdN+Zd9rljwwlc5tBDl6UMi+RQ
6p82BMl+LGpt2tAI3R1Tgj/V9BX5ijmLpXQAG9dLi/6CQAEKEGJJhsUWZV8DIo6g
4BARQNR+I13izvI1MYLg4QS2Yx2H5jvR1ewPyMuSH6DuK7ZrHICQhSbslyqfAKH4
xGie6HVPAm+t0dhUrwppcDDI9TWE4TFeiilV+Tl8nLHAnSBdZvDSMKW94nYxzlsb
uQJZHXMI+OgzgND4HCyE7vc7PCwvkF1YPtmt6/zkH4D++gk64LIxojyVAiEm8bAJ
7a2vCnIjOLaaC3/s5hN2dZQG6IeXX70eqG0NE1cHqwTxlj5dCxmNds1nHUgBiyHq
FJ/S/ns7cGNkOgbHB9LV
=NgIt
-----END PGP SIGNATURE-----
Merge tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/cleanup
From Kukjin Kim:
Samsung cleanup 2nd for v3.14
- remove <mach/regs-clock.h> for exynos
- remove <mach/regs-irq.h> for exynos
- local <mach/regs-pmu.h> into mach-exynos
- select PM_GENERIC_DOMAINS for ARCH_EXYNOS4
instead of each SOC_EXYNOS4XXX in Kconfig
- call pm_genpd_poweroff_unused() instead of via
exynos_pm_late_initcall() because no need to
handle whether CONFIG_PM_GENERIC_DOMAINS is enalbed
* tag 'samsung-cleanup-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: EXYNOS: Kill exynos_pm_late_initcall()
ARM: EXYNOS: Consolidate selection of PM_GENERIC_DOMAINS for Exynos4
PM / devfreq: use inclusion <mach/map.h> instead of <plat/map-s5p.h>
ARM: EXYNOS: remove <mach/regs-clock.h> for exynos
ARM: EXYNOS: local definitions for cpuidle.c into mach-exynos dir
cpufreq: exynos: move definitions for exynos-cpufreq into drivers/cpufreq/
ARM: EXYNOS: local definitions for pm.c into mach-exynos dir
PM / devfreq: move definitions for exynos4_bus into drivers/devfreq
ARM: EXYNOS: cleanup <mach/regs-clock.h>
ARM: EXYNOS: cleanup <mach/regs-irq.h>
ARM: EXYNOS: local regs-pmu.h header file
ARM: EXYNOS: remove inclusion <mach/regs-pmu.h> into another headers
ARM: EXYNOS: cleanup <mach/regs-pmu.h>
Signed-off-by: Olof Johansson <olof@lixom.net>
mbus is the memory bus clock, and it is present on both sun5i and sun7i
machines. Its register layout is compatible with the mod0 one.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds all the mod0 clocks available on A20 to its device
tree. This list was created by looking at AW's code release.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds all the mod0 clocks available on A10 and A13. The list
has been constructed by looking at the Allwinner code release for A10S
and A13.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds all the mod0 clocks present on sun4i to its device tree
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds PLL5 and PLL6 nodes to the sun4i, sun5i and sun7i
device trees.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This commit adds the PLL4 definition to the sun4i, sun5i and sun7i
device trees. PLL4 is compatible with PLL1.
Signed-off-by: Emilio López <emilio@elopez.com.ar>
Acked-by: Maxime Ripard <maxime.ripard@free-electrons.com>
This branch contains changes to tegra_defconfig that came in after
I sent the previous pull-request/tag tegra-for-3.14-defconfig. We enable:
* DRM_PANEL/DRM_PANEL_SIMPLE, which implements the built-in LCD panel
support for Harmony, Cardhu, and Dalmore.
This branch is based on tag tegra-for-3.14-defconfig, for which I sent a
previous pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStIafAAoJEMzrak5tbycx92QQAL3LyEJIAp3zUkT4QJXVEowh
OnnwMiedwQZg07pT03VENznPGXkmP3jdvZv/QCe2UAdA02luyvX7ukWBnEuF43IY
88VcgwXwObUsrdMYfJR6OtW7qOxobTN9lcuVjctixgI+mHrul0GnV6b7kYDNTa1m
lWI9g12Tk2UFbvCzhXPFcU3es4S4g7F8Ffs8KHjTf/kpolXlXu1WcGoTgrYhr1mn
qvI2FVsLnBcxbDZb5Prv0RO8pr9efgoXU4eDY30Od+/NYqWL4iVT56M6VdmFo/5P
Ne3Plsg7LajJKilliUo/WPuKWsU1RepfG+6LNY+4WJAQNEhrrN2iSpUWfKOVbK4+
Au7M/y1ObbtpnZLO0pzj7KBLOLPXXrhtkJm7NetuNcb7J57/HjPtq9y7FgouOdfz
vpxjc1KRbZPXIS+QYFUfkmq6giS72hXRv4psySWUjwoLfojnsXx9E5YUoyQO7k1H
SBulEUEQVy+l9VBssl6hrMaLqx4iN9hJ10nGsimjgwUxSZyTiYng8E/1D4wlkZrm
4uakuYYKeLWVODURJNRpVBxmZe0U6MO7dzQkRZX1M/fAMtCqBUB94tdtCrKoq6o3
xyRma7dUWeN/ohIckRRN5BPjfJ7m0Hg4Z/QlJ3+2EUH8FFnDcClbOxGbDbrM0SZW
I7mL461zb1K8pW+8X8Y/
=6BvU
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-defconfig-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/boards
From Stephen Warren:
ARM: tegra: second set of defconfig changes
This branch contains changes to tegra_defconfig that came in after
I sent the previous pull-request/tag tegra-for-3.14-defconfig. We enable:
* DRM_PANEL/DRM_PANEL_SIMPLE, which implements the built-in LCD panel
support for Harmony, Cardhu, and Dalmore.
This branch is based on tag tegra-for-3.14-defconfig, for which I sent a
previous pull request.
* tag 'tegra-for-3.14-defconfig-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Enable DRM panel support
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch contains changes to Tegra's device tree that came in after
I sent the previous pull-request/tag tegra-for-3.14-dt. Changes are:
* Set up aliases for RTCs, so that the correct RTC is chosen to
initialize the system date/time.
* Venice2 pinctrl and regulator configuration.
* Built-in panel enablement for Harmony, Cardhu, Dalmore.
* HDMI enablement for Dalmore.
* USB2 port enablement for Beaver.
* Keyboard and power key enablement for Venice2.
This branch is based on tag tegra-for-3.14-dt, for which I sent a
previous pull request.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStIY4AAoJEMzrak5tbycxv2gP/AmghgUu2S3JJLTBfwpRLcz9
Cwppop9MtHDSg+PnZgDdX3wZEJhGXSBad0GUa+blaThJjpvtxGr7wdQFI2QYM0/9
DuSaeqnl9Vw+dRoVugWJSu78DXBs5mwxaGSOJi5PO+dPJtPc+wro/+aZLCqYxegH
hIMyHqIW8jpv0cRTcwoPxwwFbfH9NTCIbcOK1N2xyZa7QTrxCZJKHuJNqhaimPdx
9B+hqMCcx9Y+Uzg6PFHq27RIA5LWqIpM/5gsBV9+FJcUZWvYLWlkI3sxFaC238LB
YMqv0t1T18ZbPhr/z+ixY+rPOzHGLjqcq2HCpZU/irYS7ysmoMHhFeDXrF5y2Kqr
fEIac40GsohxX9DxJJ+f1Xb1tKc9s8ynG84QHJfqhBUafjXHeKBofYYK+XZ8OMna
D15vnaDtA2nujLzJA4FGCttAgkADYLaoNE7TRyyPLGaSuA4DTJJtVApy97YJAWMS
qNsLDkGWgj6fTwpG7WRACAAmxfGK6ARXjQGKjyXicC5LP135lRdTufrKCTG7gIqS
C3wlEEgxNlFuigLqhsvWiIkMCBfyTujmApUgDMBotSApwVF5l2wuMMdB31AL3SYI
YU7IMcvRXi41La9JOAuVXcPT92/S+YVqt5KlemxEcGy6hl2vzuOv6JcUBgv4WnSU
A+qsKuhPFJd5BzLMGRov
=CUm7
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
From Stephen Warren:
ARM: tegra: second set of device tree changes
This branch contains changes to Tegra's device tree that came in after
I sent the previous pull-request/tag tegra-for-3.14-dt. Changes are:
* Set up aliases for RTCs, so that the correct RTC is chosen to
initialize the system date/time.
* Venice2 pinctrl and regulator configuration.
* Built-in panel enablement for Harmony, Cardhu, Dalmore.
* HDMI enablement for Dalmore.
* USB2 port enablement for Beaver.
* Keyboard and power key enablement for Venice2.
* tag 'tegra-for-3.14-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Enable power key on Venice2
ARM: tegra: Enable Venice2 keyboard
ARM: tegra: enable USB2 on Tegra30 Beaver
ARM: tegra: modify Tegra30 USB2 default phy_type to UTMI
ARM: tegra: Enable HDMI support on Dalmore
ARM: tegra: Enable DSI support on Dalmore
ARM: tegra: Add Tegra114 gr3d support
ARM: tegra: Add Tegra114 gr2d support
ARM: tegra: Add Tegra114 DSI support
ARM: tegra: Add host1x, DC and HDMI to Tegra114 device tree
ARM: tegra: Add MIPI calibration DT entries for Tegra114
ARM: tegra: Enable LVDS on Cardhu
ARM: tegra: Enable LVDS on Harmony
ARM: tegra: set up /aliases for RTCs on Venice2
ARM: tegra: add ams AS3722 device to Venice2 DT
ARM: tegra: fix missing pincontrol configuration for Venice2
ARM: tegra: set up /aliases entries for RTCs
Signed-off-by: Olof Johansson <olof@lixom.net>
In preparation to the introduction of the support for additional SoC,
the mvebu/common.h should be clear of Armada 370/XP-specific
definitions. Therefore, move the Armada 370/XP SMP specific
definitions to the armada-370-xp.h file.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The mach-mvebu/common.h file contains prototypes of functions that
have been removed, so this commit removes the corresponding
prototypes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
problems with GPMC, RNG, and ISP/IVA MMUs on OMAP2/3. The other fixes
some problems with DEBUG_LL on DRA7xx.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/hwmod_fixes_b_v3.13-rc/20131226021920/
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSvANxAAoJEMePsQ0LvSpLd0AP/1Toh0oIX7xdj9zaTosZgovZ
UsNbkzilxKWVGwyjEHj0510YL/v3YuYYPmF+UtZcOVEybz+EWP21BXJc0y+jX7QV
ma21i3abK0uKJ1Dq0CGmolnq9NRswvS2TR9SKgXmG/1HGF1wo5MIjzx3ZCtFdni4
+PZYG1RFJEFUBWtQoWnkqm16QS6wwzfIHlfLBy5kEu70ueFuAyLd7yKWgtjDkpWP
Yvf5mjvIdbDlK6sn9388UydYq4Puy8k0KWHlcQn/jA0uQecjt7gcsk6B24RPhPzt
l9H2wMRxoTBgx6di8ywGdU0XV6pa6A7DWQGhve2AjQlBZ5hug7i4oEOO4Iod6cMm
c3lqA2DEbLLt3Xwjj97EZYKiIlIxnYbqFdw/Ql0KdnlAwtZw333EkcRKW5+15Jsg
qcYU2GtsvGRqBgUD13eE7OLM9Ovgdkt18PYLEs5Vzsi08n+LDwuoZj4lpCHOsBZl
1xO38Q3M9NCmMUubfxbY0HvzW3EqgBZHFGgf3hWsbxkV89htCrDD+kwo1OTXCLXE
s3FFIAaa7HDdWJCD/CPfKoaY0upqv/DwsHwKNpvT8SiiVb90mNXumJauC1H8GeW9
gQqscy2u+UhtXtuPiYpG2h4tEGC95ySwzbolT4d84fbqmkMQLcfzSofgJ98iYg2N
vRGMA2I8U142M2HaCxZx
=kOrX
-----END PGP SIGNATURE-----
Merge tag 'for-v3.13-rc/hwmod-fixes-b' of git://git.kernel.org/pub/scm/linux/kernel/git/pjw/omap-pending into debug-ll-and-ldp-backlight-fix
A few OMAP hwmod fixes for v3.13-rc. One patch fixes some IRQ
problems with GPMC, RNG, and ISP/IVA MMUs on OMAP2/3. The other fixes
some problems with DEBUG_LL on DRA7xx.
Basic build, boot, and PM test logs are available here:
http://www.pwsan.com/omap/testlogs/hwmod_fixes_b_v3.13-rc/20131226021920/
Looks like the LCD panel on LDP has been broken quite a while, and
recently got fixed by commit 0b2aa8bed3 (gpio: twl4030: Fix regression
for twl gpio output). However, there's still an issue left where the panel
backlight does not come on if the LCD drivers are built into the
kernel.
Fix the issue by registering the DPI LCD panel only after the twl4030
GPIO has probed.
Reported-by: Russell King <rmk+kernel@arm.linux.org.uk>
Acked-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
[tony@atomide.com: updated per Tomi's comments]
Signed-off-by: Tony Lindgren <tony@atomide.com>
Enable new features required by the Venice2 board.
This branch is based on v3.13-rc1, and shouldn't cause any conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3LxAAoJEMzrak5tbycxEl4P/0in5tXY+k4ZxR2OyiBtCcgr
sJLsaCCUE3vW1WpxKD/HlxFWxoAF1nC7jB0PlQsH0R/AFzGchrWRBZ+9OFe4jdcn
PpN199r0kEk3cyniGlftbvvubbqPYrHO9RmeUtRIGN2BWZiYy2/IUhjdWMFOnlBD
uSXNNCiTJtPPSjIhj02V1jmIMHNhDCi6Sk4Wzb079EAFA8kRC8a5fbuz78Q/W2wU
3MAlL5MVBI2pfUeBk4c0B006hrES4cpErg/QtZSsWdpPEDowid0Zmg7hqWeKg8X2
0N3gQo0UJfj5qc/CjzJ5nUr4qKCcaC8hXpKt6gkOqQnt0cZh6xBxaCxkphJoxFvJ
/08A11UXsBw1iNeGMP2nv+bxlkECdgE2n7+IfB52eDszq7lAJGoE5Wvp2GHyvVkQ
9uwQ7Lb5FL2mO27ASwnihcK7ND65XztyqJuO22oS/sEF99rrGLxXDeNOwgqCvCUi
j39I4u064O/jtotza9K1yOhMdo3JW0n8qAyxM8/aljYvSF50lvQiuEyXgvwezSRr
r6a4QiDpvDN964WxRNr/ALqKRu1mymz0oiQ0acc7f+0QAK37RFVpVJaJwzONHIY/
+/PiseBRskDzqK/Rc1hTLquMRGCmzyQGeWSdgD52OAjWF98xtlLAFQsuFf7QZfAz
Mnn5fB+GfiiSKMkyJ/ZU
=8cB3
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/boards
From Stephen Warren:
ARM: tegra: defconfig changes
Enable new features required by the Venice2 board.
This branch is based on v3.13-rc1, and shouldn't cause any conflicts.
* tag 'tegra-for-3.14-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: tegra_defconfig updates
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch contains all the changes to Tegra's device tree. The
highlights are:
* Many patches for Tegra124 SoC support, and the Venice2 board which
uses that SoC.
* Conversion to use more headers providing named constants for pinctrl
and key codes, which improves readability.
* A few cleanups.
This branch is based on tag tegra-for-3.14-dmas-resets-rework in order
to avoid conflicts with the DT changes required to use the common
bindings for DMAs and resets.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3KtAAoJEMzrak5tbycxWpIP/A1zpgEBb8f0k/6aBRmiKisW
G97QGbKVGL9ZJzi/CC12nD68URwN8mVfSRn9d+r7jN5zcEh+RAnCflj6LzX5c0nV
XZndE9GnnpqpbsoWY+ubDPRvJnG2ZWPciMoR1p/ftNOHweELPG/5qTCoZLvi3abI
7L0EzMcNY6pC5RB0unCkTHWbmCsgTjDFQ0UI/iKJy+WYzSt0YLFW7TCMkEUBDfcg
ElD2qhNYEZI5eRWO/ccl5lsoBwg47YSCXFti1rAZEyp7/SXRGm7gbdW0d/UpywoY
66V2GMP6mHeAMk6RFHSo1R2XGP5uxTY/n9UThtX5YuKTFYUwy541+xK4qWlVlpf+
SIukOFbHexPqvBbZWSB7lgdUemh2Cw/RTSDkp//hAHDcxMN5exjswgJIo9eIjzdi
W78JaBZVBmsfJx+jEan6kNTV0TEbNLLnEhDdulLZjF2XxbGcWsYeJa3BmEGP8Lf1
VlzEOMXCkbar9kO8nJxCLXCK7JFR+GGZr2pF0hV9PIjrAao67INqDZpXvIZg5TnB
aNoT+vzO19AoA7vj/aGmjVoahr/U3z+wFeHWoWyagq2Kxmx8RdYuV8IAo7CK9wo0
ok6J/MSdqq8WZYhIA/5BZffSl0RrlY2fHOpj3Jga72fjzgoH4BGmUQaWrHjQlzhh
uqLwJymOSLsFIUD6itof
=3M5I
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/dt
From Stephen Warren:
ARM: tegra: device tree changes
This branch contains all the changes to Tegra's device tree. The
highlights are:
* Many patches for Tegra124 SoC support, and the Venice2 board which
uses that SoC.
* Conversion to use more headers providing named constants for pinctrl
and key codes, which improves readability.
* A few cleanups.
This branch is based on tag tegra-for-3.14-dmas-resets-rework in order
to avoid conflicts with the DT changes required to use the common
bindings for DMAs and resets.
* tag 'tegra-for-3.14-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (24 commits)
ARM: tegra: Add SPI controller nodes for Tegra124
ARM: tegra: Fix misconfiguration of pin PH2 on Venice2
ARM: tegra: fix pinctrl misconfiguration on Venice2
ARM: tegra: add default pinctrl nodes for Venice2
ARM: tegra: correct Colibri T20 regulator settings
ARM: tegra: convert dts files of Tegra30 platforms to use pinctrl defines
ARM: tegra: convert dts files of Tegra20 platforms to use pinctrl defines
ARM: tegra: convert dts files of Tegra114 platforms to use pinctrl defines
ARM: tegra: Add header file for pinctrl constants
ARM: tegra: convert device tree files to use key defines
ARM: tegra: Enable PWM on Venice2
ARM: tegra: Add Tegra124 PWM support
ARM: tegra: add sound card to Venice2 DT
ARM: tegra: add audio-related device to Tegra124 DT
ARM: tegra: enable I2C controllers on Venice2
ARM: tegra: add I2C controllers to Tegra124 DT
ARM: tegra: add MMC controllers to Tegra124 DT
ARM: tegra: add Tegra124 pinmux node to DT
ARM: tegra: add APB DMA controller to Tegra124 DT
ARM: tegra: add reset properties to Tegra124 DTs
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Bringing in the tegra dma/reset framework cleanup as a base for the DT changes.
* tegra/dma-reset-rework: (320 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3IGAAoJEMzrak5tbycxVVUP/09VfeFYOidIm6mgbWSMlL4l
DEPzrGBOvyO60og4LIbDIgwDzkcEsxIF9erlrVTz1Fvh2p0P0sQycIKjvyhvNXeh
Ft9TQ1kDHjoJcfHI9f8tapkmwhOG+6vy2gDrTPmyxjnLpiE5ccM18CCr5CMK+y2v
Ojzmf2paPBFyI84gcdWuwF4Ze2YmwdHmG7TksG/PZrpicizSxe+d9wNVDBMkJnP6
QFicMU6DEFZVwwDkFx4qPYrFDJPk8dqcAmNl+F+9jGEqTmxA+7M8eOF/SQa62lwa
OJrVugD8YigT5NjRW/9btOVY/jUHbg0Ekj5DXd7Q9rO5KNUrFDRSia5XiWmms/S8
QNJezmjNgA83OQDefuAkpsKydf1XGoyIQ9EjDUb4i807PRwTO4En+1pD0EpEWSet
0c1mfDvU5uC6L9A5VvR0pzyGz2U2EhNhkUz03WAqtWYdrR68vIZHNZVIvHOLuwWF
fDkS26KxziOmKM1ePdL7wemuNOod8ACeyzXMa2dhR68l6LH1X1pnMaoxvk2AjETk
SMat9tsxY827+TtQlAQ+4bdR3qXqYsQLD7VWOPO0V3fs5T08jVZrpJ9pHDRYW88K
dGHmIW4sHXKXP4Qw9rDGWSkWZeOVJYr72U6uH9vbg8hK6Wi2eAMxZ27ngFiqahSK
PIhnAfsdM2/FX+C+vu58
=Oztt
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: SoC-specific core code changes
This branch contains various miscellaneous changes to code in the
mach-tegra/ directory. It is baased on v3.13-rc1, and shouldn't conflict
with anything else.
* tag 'tegra-for-3.14-soc' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: select PINCTRL_TEGRA124 for Tegra124 SoC
ARM: tegra: use section-sized static mappings for LPAE too
ARM: tegra: don't hard-code DEBUG_LL baud rate
ARM: tegra: fix DEBUG_LL combined with LPAE
ARM: tegra: switch FUSE clock on before usage
Signed-off-by: Olof Johansson <olof@lixom.net>
Add support for the Trusted Foundations secure-mode firmware, as found
on NVIDIA SHIELD. This allows Linux to run in non-secure mode on this
board; all previous Tegra support has assumed the kernel is running in
secure mode.
This branch is based on v3.13-rc1, and shouldn't cause any merge
conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3NgAAoJEMzrak5tbycxRXkP/imK6IQn5cAtXY7nfKnn4Rke
RjvERwURDpi6QDrXaRe6NUVg3PgZ0Z7kXLqSuj/cAPinMyhQDR5DxlJVjYiduJ50
CmMhV+RWkA/cmaU2oPjpD3YEm68txYXTyf3iWfX1ScFSuNNN0yGel3eY2rFjX/aT
RgAWm8HbQTR7NDazAAt9gOqeJUtfs3msXwMxtZvD6OhRougyaPlqfuafjVpfM9vK
JLDAbJuMEl6/dI2UYVvDBJvL//TOOjnwy6YFwQCZsqhYGHhT3Xc9hQABilUQmJ1d
mbu29cPBrRgGiu3anpjZeh0KxVB3xDPp1a+o4lSH0iJztAPy4WTUZ1Sc3y2qwKaS
qZ5Zu5SXVI1O/ywv1FChL2syuJbgOH+HGBMFslacVniQ/U1o4PmKZCJOB0pnpf8B
dESAQgvDqIZeyt2eXxsAMAOw01xMTotngAaJpAtYFv0plP+PxAhr+dkHHjCwwkde
7+OKeVE5TDDwlhz5PE35/4EWdWM0622aL3sK1IxrR2q66LGpKAoQpFeKaAUr0d6z
OQnQiS+uNSNrCvAEeyEL2bQfv1xsjOFpFy6PV7ShrUrAgPVR3+wj82RvwTciMdbd
tv3Y7LXCugSUOdq/abc3VgAnlgMzlhH5vlj6CMcKSSPbzZ3lbRB37iBmxpJLm9qa
o3Ah/MaWSqtqmIueFrpa
=c5t/
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-trusted-foundations' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/drivers
From Stephen Warren:
ARM: tegra: Trusted Foundations firmware support
Add support for the Trusted Foundations secure-mode firmware, as found
on NVIDIA SHIELD. This allows Linux to run in non-secure mode on this
board; all previous Tegra support has assumed the kernel is running in
secure mode.
(The base TF support has been discussed back and forth a lot; for now
the most logical place for it seems to be under arch/arm, so we're adding
it here. We can move it out to a common location in the future if needed).
* tag 'tegra-for-3.14-trusted-foundations' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: support Trusted Foundations by default
ARM: tegra: set CPU reset handler using firmware
ARM: tegra: split setting of CPU reset handler
ARM: tegra: add support for Trusted Foundations
of: add Trusted Foundations bindings documentation
of: add vendor prefix for Trusted Logic Mobility
ARM: add basic support for Trusted Foundations
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.
A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.
This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3G5AAoJEMzrak5tbycxHaEP/2YP1KIUTINzF9JlTaFWLd38
dlqCOdDjcIow6QvaI0H2xdD7OhWqbiK2gAKz10PH0TYVr5AJZKyC7uxAw1gvV5bI
2hgP9ZBVQY8qfveZuyQhL9jCwAg52TfG2LBO4Iw3wng9tO00uo8knjoHURmiewuY
fLY8CQxYydwK8MmqabPI/L0gQhSlswyDByaeB0ixHJncSVT8KHmbSX8kx7FnYsI6
/r/D7IQtMyx52XJRbInN83UIdONKP9vkPAXmptKBU2SGwdXOzqPqfxFuNRKN85Gq
a4wlJUQAfBAndiemaZIH5O7gmmUht1lB0L9JWDFw9nBr6EHDVOpgRgi/OgVFaFE+
Qer3LdrpEvyXsRe3AjeQgta8716KaRMW3IbaqkdS0F+HwyFGL9/nGRttu9JLHSCR
oo7FVscaE7tC2d/LGNqI0y4pprgbrjROT70hWoNDF8oS5qDsI3rxEjB0FXyzE2by
Bd702Sc9heh60Hnov/vZy9WFcWETEKVEF5hgIL3lrjA6pMKdH7fEylOD+bxVAmE2
t5wePXc7OSdciaLN/D1GhtCD+R58u+idHadKnU9uRYB1wmeIAeJMi9D/ZnpKftX4
M5Ts7t8k1jxZlRXXgiara3SwJ6tIOlc5vEvhQWEeInzL0yishFDy2mmq1lMaV0mJ
cFgQUdhufycI0Yprfwjt
=jJOV
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/soc
From Stephen Warren:
ARM: tegra: powergate driver changes
This branch includes all the changes to Tegra's powergate driver for 3.14.
These are separate out, since the Tegra DRM changes for 3.14 rely on the
new APIs introduced here.
A few cleanups and fixes are included, plus additions of Tegra124 SoC
support, and a new API for manipulating Tegra's IO rail deep power down
states.
This branch is based on tag tegra-for-3.14-dmas-resets-rework, in order
to avoid conflicts with the addition of common reset controller support
to the powergate driver.
* tag 'tegra-for-3.14-powergate' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux:
ARM: tegra: Add IO rail support
ARM: tegra: Special-case the 3D clamps on Tegra124
ARM: tegra: Add Tegra124 powergate support
ARM: tegra: Export tegra_powergate_remove_clamping()
ARM: tegra: Export tegra_powergate_power_off()
ARM: tegra: Rename cpu0 powergate to crail
ARM: tegra: Fix some whitespace oddities
Signed-off-by: Olof Johansson <olof@lixom.net>
Bringing in the tegra dma/reset rework as a base for new SoC branches.
* tegra/dma-reset-rework: (81 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.
This conversion relies on a few sets of patches in branches from outside
the Tegra tree:
1) A patch to add an DMA channel request API which allows deferred probe
to be implemented.
2) A patch to implement a common part of the of_xlate function for DMA
controllers.
3) Some ASoC patches (which in turn rely on (1) above), which support
deferred probe during DMA channel allocation.
4) The Tegra clock driver changes for 3.14.
Consequently, this branch is based on a merge of all of those external
branches.
In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:
a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
conflicts.
b) The DRM tree, which introduces new code that relies on the reset
controller framework introduced in this branch, and to avoid
conflicts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSr3AnAAoJEMzrak5tbycxfMwQAMeffTFreJqDiQ4Vj0XmuhSn
RFlXiZQsWtQ6gGgNfKyDsXzDMaz1KDAabcUYRcZwrluxuSCPBcK1JirCj5R8uRY7
LDZFX92CO8zRgiij0mhgokV4zzuEQ56q1uhPxqI3o+wG3v44jlMSMgFHQJUevdET
aKr2Pss8Hb00XDztnpxprs6FUoU/W99NRH0i/5znbBwuHqYFP37zlKe2MRwbqDwR
AMgkrnGoawe85Stz4p/iR9pCLpAMa0dH94V4JrAP4+IQrl0DEKWbrolpQHii4gzh
NCGazMELTqkaZaorC/n1SmczH1kTj4vcjbbmeB8dwS8Vqhr+uf7W1oLlJ46TUOsp
ESO0uD2GfpHKQQwLxEfgjfmwsIUMbdWHef8f2HUuvl6Js+LCpaPkxd52Pt/qL4sU
0sKqTbldRZXzGhvwa0/MK32WhmH4v31s7IZAg5A2YxqDR6yWryl7legWyvrI96C0
OlmVe1C/2NGk0QCfK0G/xTa9V7YzMfj8k4ICSZOgUoF4BeGGj6d3svWvLbKbbrU1
0fVvR7aCm78pRXixI6kURpj9D0mEfqus9Hx7VoWcL0TS4QH2dSYlGI+jDCiliQmj
+kWrZWHsASSvPmUZk4RBNaviCbnGU8/t5nNdJSdFIUM/PIswzZ4GaAu6gdVksIY8
hcx410PyAzTZL2lENamE
=8T7+
-----END PGP SIGNATURE-----
Merge tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux into next/cleanup
From Stephen Warren:
ARM: tegra: implement common DMA and resets DT bindings
This series converts the Tegra DTs and drivers to use the common/
standard DMA and reset bindings, rather than custom bindings. It also
adds complete documentation for the Tegra clock bindings without
actually changing any binding definitions.
This conversion relies on a few sets of patches in branches from outside
the Tegra tree:
1) A patch to add an DMA channel request API which allows deferred probe
to be implemented.
2) A patch to implement a common part of the of_xlate function for DMA
controllers.
3) Some ASoC patches (which in turn rely on (1) above), which support
deferred probe during DMA channel allocation.
4) The Tegra clock driver changes for 3.14.
Consequently, this branch is based on a merge of all of those external
branches.
In turn, this branch is or will be pulled into a few places that either
rely on features introduced here, or would otherwise conflict with the
patches:
a) Tegra's own for-3.14/powergate and for-4.14/dt branches, to avoid
conflicts.
b) The DRM tree, which introduces new code that relies on the reset
controller framework introduced in this branch, and to avoid
conflicts.
* tag 'tegra-for-3.14-dmas-resets-rework' of git://git.kernel.org/pub/scm/linux/kernel/git/tegra/linux: (30 commits)
spi: tegra: checking for ERR_PTR instead of NULL
ASoC: tegra: update module reset list for Tegra124
clk: tegra: remove bogus PCIE_XCLK
clk: tegra: remove legacy reset APIs
ARM: tegra: remove legacy DMA entries from DT
ARM: tegra: remove legacy clock entries from DT
USB: EHCI: tegra: use reset framework
Input: tegra-kbc - use reset framework
serial: tegra: convert to standard DMA DT bindings
serial: tegra: use reset framework
spi: tegra: convert to standard DMA DT bindings
spi: tegra: use reset framework
staging: nvec: use reset framework
i2c: tegra: use reset framework
ASoC: tegra: convert to standard DMA DT bindings
ASoC: tegra: allocate AHUB FIFO during probe() not startup()
ASoC: tegra: call pm_runtime APIs around register accesses
ASoC: tegra: use reset framework
dma: tegra: register as an OF DMA controller
dma: tegra: use reset framework
...
Signed-off-by: Olof Johansson <olof@lixom.net>
Commit 4dcfa60071 ("ARM: DMA-API: better
handing of DMA masks for coherent allocations") added an additional
check to the coherent DMA mask that results in an error when the mask is
larger than what dma_addr_t can address.
Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix
the problem.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 4dcfa60071 ("ARM: DMA-API: better
handing of DMA masks for coherent allocations") added an additional
check to the coherent DMA mask that results in an error when the mask is
larger than what dma_addr_t can address.
Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix
the problem.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 4dcfa60071 ("ARM: DMA-API: better
handing of DMA masks for coherent allocations") added an additional
check to the coherent DMA mask that results in an error when the mask is
larger than what dma_addr_t can address.
Set the LCDC coherent DMA mask to DMA_BIT_MASK(32) instead of ~0 to fix
the problem.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This reverts commit b652896b02.
Unfortunately this commit prevents multiplatform from booting to
the point where a serial console is available. Revert it while
a solution is sought.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This reverts commit 6dea2c1ebc.
Unfortunately this commit prevents multiplatform from booting to
the point where a serial console is available. Revert it while
a solution is sought.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 7d7e1eb (ARM: OMAP2+: Prepare for irqs.h removal) and commit
ec2c082 (ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ)
updated the way interrupts for OMAP2/3 devices are defined in the
HWMOD data structures to being an index plus a fixed offset (defined
by OMAP_INTC_START).
Couple of irqs in the OMAP2/3 hwmod data were misconfigured completely
as they were missing this OMAP_INTC_START relative offset. Add this
offset back to fix the incorrect irq data for the following modules:
OMAP2 - GPMC, RNG
OMAP3 - GPMC, ISP MMU & IVA MMU
Signed-off-by: Suman Anna <s-anna@ti.com>
Fixes: 7d7e1eba7e ("ARM: OMAP2+: Prepare for irqs.h removal")
Fixes: ec2c0825ca ("ARM: OMAP2+: Remove hardcoded IRQs and enable SPARSE_IRQ")
Cc: Tony Lindgren <tony@atomide.com>
Signed-off-by: Paul Walmsley <paul@pwsan.com>
With commit '7dedd34: ARM: OMAP2+: hwmod: Fix a crash in _setup_reset() with
DEBUG_LL' we moved from parsing cmdline to identify uart used for earlycon
to using the requsite hwmod CONFIG_DEBUG_OMAPxUARTy FLAGS.
On DRA7 though, we seem to be missing this flag, and atleast on the DRA7 EVM
where we use uart1 for console, boot fails with DEBUG_LL enabled.
Reported-by: Lokesh Vutla <lokeshvutla@ti.com>
Tested-by: Lokesh Vutla <lokeshvutla@ti.com> # on a different base
Signed-off-by: Rajendra Nayak <rnayak@ti.com>
Fixes: 7dedd34694 ("ARM: OMAP2+: hwmod: Fix a crash in _setup_reset() with DEBUG_LL")
Signed-off-by: Paul Walmsley <paul@pwsan.com>
As the davinci-gpio driver is migrated to use irqdomain
there is no need to pass the irq base for the gpio driver.
This patch removes this variable from davinci_gpio_platform_data
and also the refrences from the machine file.
Signed-off-by: Lad, Prabhakar <prabhakar.csengg@gmail.com>
Acked-by: Linus Walleij <linus.walleij@linaro.org>
Signed-off-by: Sekhar Nori <nsekhar@ti.com>
This patch adds DT board setup for the LaCie NAS LaPlug.
Chipset list:
- CPU MARVELL 88FR131 800Mhz
- SDRAM memory: 128MB DDR2-800 400Mhz
- 1 Ethernet Gigabit port (PHY MARVELL 88E1318)
- 1 Mini PCI-Express port
- 1 NAND 512 MB
- 1 push button
- 2 LEDs (red and blue)
- 4 USB Ports
Signed-off-by: Maxime Hadjinlian <maxime.hadjinlian@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
This file is mainly a copy of kirkwood-6281.dtsi.
The pinctrl seems to be the same.
These platforms differs only with their CPU, memory capabilities and the
number of GPIO available (36 on 6192, 50 on 6281).
Signed-off-by: Maxime Hadjinlian <maxime.hadjinlian@gmail.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The per-CPU PMSU registers documented in the datasheet start at
0x22100 and the last register for CPU3 is at 0x22428. However, the DT
informations use <0x22100 0x430>, which makes the region end at
0x22530 and not 0x22430.
Moreover, looking at the datasheet, we can see that the registers for
CPU0 start at 0x22100, for CPU1 at 0x22200, for CPU2 at 0x22300 and
for CPU3 at 0x22400. It seems clear that 0x100 bytes of registers have
been used per CPU.
Therefore, this commit reduces the length of the PMSU per-CPU register
area from the incorrect 0x430 bytes to a more logical 0x400 bytes.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
The ARMADA_XP_MAX_CPUS definition was in common.h, which as its name
says, is common to all mvebu SoCs. It is more logical to have this XP
specific definition in the already existing armada-370-xp.h header
file, especially in preparation to the addition of the support for
other SOCs in mach-mvebu.
Signed-off-by: Thomas Petazzoni <thomas.petazzoni@free-electrons.com>
Acked-by: Gregory CLEMENT <gregory.clement@free-electrons.com>
Acked-by: Andrew Lunn <andrew@lunn.ch>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that the DTS file r8a7790-koelsch.dts can be used with
board-koelsch.c and board-koelsch-reference.c, proceed with removing
r8a7790-koelsch-reference.dts.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Tested with RIIC2 on a genmai board. Others untested but hopefully
trivial enough to be added.
Signed-off-by: Wolfram Sang <wsa@sang-engineering.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The field will be removed from the sh-sci driver. Don't set it and let
the driver handle baud rate calculation internally.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Passing the register base address and IRQ through platform data is
deprecated. Use resources instead.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The SCIF driver is transitioning to platform resources. Board code will
thus need to define an array of resources for each SCIF device. This is
incompatible with the macro-based SCIF platform data definition as an
array. Rework the macro to define platform data as individual
structures.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace copy-n-paste SCIF platform data and device declaration with a
macro. This reduces the amount of code and improves readability.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace copy-n-paste SCIF platform data and device declaration with a
macro. This reduces the amount of code and improves readability.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace copy-n-paste SCIF platform data and device declaration with a
macro. This reduces the amount of code and improves readability.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Replace copy-n-paste SCIF platform data and device declaration with a
macro. This reduces the amount of code and improves readability.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
This is needed to use SRC (= Sampling Rate Converter)
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
- Correct HSMMC1 card detection type for s3c6410-mini6410
- Fix different key mapping backslash and search key for exynos5250-snow
- Fix definitions of div_mmc_pre4 divider for CLK_SET_RATE_PARENT
- Fix clock provider for mshc on exynos4412
- Fix definitions of mshc dt nodes for exynos4x12
- use mshc controller for eMMC for exynos4412-trats2
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStdJKAAoJEA0Cl+kVi2xq3JwQAKBmII+LxTO5GPYHfXa1lXq+
xJD48qkDJf8VXM1LfoFR6Hv5hq/76TjxW9WnkLQtdZNT7g6sBysSP83AVCx1cmVj
stvn1j3pqG4FAh3z6tALx6D/SqtgZjE3tqNMV8+5sadZ6g3k1D2cHqvCNfvac2a9
Sf0igi1SmHnVhuFbwjOfDtgDmhyYyLsiCQTtaCbz5raikYeAY5LLSEEYykPiOqSp
4cGtyOnfIoOS7+1JK4WKz38FYag9AN3nTVhcST70tdKRk5yhZdDOGgERS1DB3kcc
14hZQ1YIm/Z/xHA9fqbY337ttSMyE2yt8rYYxwYZ/25y0RkqGMbLj3w/Prrccfn/
14JU6mogBZQgZg08cST8lvxjBfCsYPo2iOeSOEIs2QB5ZLsmN4BleG6G8Pw6Vz2D
S2cU3Y43vxcnTDLzR3SzyYSWKMArY5wEFl7Z07eZ16pJp6a5G+rBSJF7MCQ1/Rtn
KH1+jKzuNmHhFw2sxUC4t3m0ED+kHSEmhy+v7xaU2rHqB2Gjfs4512migR6cLhks
Lj2S7MEmMKcTFsT25TToU/GKhtN6VljbAMdB2kYJqJBMYNpZMqJqZ7faL6/k2SE6
OwlvY9x2975I0w+JFm11IPxUTDfTvXC7Ga9i12gabxmiq8yy3aIL1kiAqsGYI+KT
DDeSqKAdcGNlTRKmcFQ+
=GEJ/
-----END PGP SIGNATURE-----
Merge tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/fixes-non-critical
From Kukjin Kim:
Samsung non-critical 2nd fixes for v3.14
- Correct HSMMC1 card detection type for s3c6410-mini6410
- Fix different key mapping backslash and search key for exynos5250-snow
- Fix definitions of div_mmc_pre4 divider for CLK_SET_RATE_PARENT
- Fix clock provider for mshc on exynos4412
- Fix definitions of mshc dt nodes for exynos4x12
- use mshc controller for eMMC for exynos4412-trats2
* tag 'samsung-fixes-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2
ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12
ARM: dts: add clock provider for mshc node for Exynos4412 SOC
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
ARM: dts: Fix exynos5250-snow's search key to be L_META
ARM: dts: Add the missing "\" key in non-US keyboards for exynos5250-snow
ARM: S3C64XX: Correct card detect type for HSMMC1 for MINI6410
Signed-off-by: Olof Johansson <olof@lixom.net>
- add DMA controller, SPI, and TMU DT nodes for exynos5420
- add PWM DT nodes for exynos5250 and exynos5420
- drop interrupt controller properties from MCT nodes
because MCT is not an interrupt controller
- move MCT nodes to exynos4x12 from board because it is
a per-processor interrupt and same 4212 and 4412
- use one cell for MCT interrupt map for exynos4 SoCs
- update Exynos MCT DT bindings accordingly
- fix missing spaces after labels for exynos
- fix mmc status property for exynos5250-snow
- add MCLK for codec for exynos5250-smdk5250
- disable SPI and I2C by default for exynos5250 SoC
and enable into requiring some boards
- rename cros5250-common to exynos5250-cros-common
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStdZ4AAoJEA0Cl+kVi2xqKLoQAJ8olXLjuttLfQ/devNh/d3T
Asm2d0Ure05aGBij0TnjeBpjc7nxqBVWTrmDAbFWVT5ySKy/q3ujlk0OUdybDBZE
iclvgmX8TnQYLxM4uxVljv6SUrf82fDFyYmuhVVG0YnouZmc0CPNmtJITdsk5b4g
HagFfCzcigWYMULsByADL7REOSa4qzB1pwHAI/cQTH0KkYbmBgFCVTCnW9DnTCD0
jH30MwDgdb9P7c9ZD7DfDngs7hmAiB6++syx9/o1DkjtoGl2GFsOUI8Er8bqwxF/
5j/fm1DYz194T9DT9PF143xKiOuxNUvZkP9azWfVPg7w8PwPrDsk+W5XBZ4flH9z
M9Qm/onQAkZI7kiQz0sSoYukZ76Cm8pLt8XlYrwg1+s5lD/UAjolr312w9ZOOP3I
M/36W7PUcfYSbi3DNJJThiRU9q5kySSfs0128AKzO/8P2qiXXUq3wtZAQsOAjeBn
oHsPypdyv43dCC2spVop87ZRCk9uocLEWV54imJsVBrUX/MPWJLvcz33/GMqCCNq
H5R+QJQrDhiDi/O5rvs+Nnlv5NRzS6HP6ZSFFvqrnZ7ilpYSEUNbKDe+gaP5gXbV
iIAaKgMj8lRe57eC1Vpa3PnBRoitI80x50ABNcxztX9BqW9jW3e0bnE1dsh0B80O
WzTYqfT7hsNpXFYseyMv
=YqMd
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
Samsung DT 2nd updates for v3.14
- add DMA controller, SPI, and TMU DT nodes for exynos5420
- add PWM DT nodes for exynos5250 and exynos5420
- drop interrupt controller properties from MCT nodes
because MCT is not an interrupt controller
- move MCT nodes to exynos4x12 from board because it is
a per-processor interrupt and same 4212 and 4412
- use one cell for MCT interrupt map for exynos4 SoCs
- update Exynos MCT DT bindings accordingly
- fix missing spaces after labels for exynos
- fix mmc status property for exynos5250-snow
- add MCLK for codec for exynos5250-smdk5250
- disable SPI and I2C by default for exynos5250 SoC
and enable into requiring some boards
- rename cros5250-common to exynos5250-cros-common
* tag 'samsung-dt-2' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung: (27 commits)
ARM: dts: Rename Exynos5250 ChromeOS common file to have exynos prefix
ARM: dts: Disable I2C controllers by default on Exynos5250
ARM: dts: Leave Exynos5250 SPI controller disabled by default
ARM: dts: Add CODEC MCLK for SMDK5250
ARM: dts: Add device nodes for TMU blocks for exynos5420
ARM: dts: Fix status property of mmc nodes for snow board
ARM: dts: Fix missing spaces after labels for exynos
ARM: dts: Simplify MCT interrupt map for exynos4 SoCs
ARM: dts: Move MCT node to exynos4x12.dtsi
ARM: dts: Drop interrupt controller properties from MCT nodes for exynos4 SoCs
Documentation: devicetree: Update Exynos MCT bindings description
ARM: dts: add pwm DT nodes to Exynos5250 and Exynos5420
ARM: dts: Add SPI nodes to the exynos5420 device tree file
ARM: dts: Add DMA controller node info on Exynos5420
ARM: dts: Use MSHC controller for eMMC memory for exynos4412-trats2
ARM: dts: Fix definition of MSHC device tree nodes for exynos4x12
ARM: dts: add clock provider for mshc node for Exynos4412 SOC
clk: samsung: exynos4: Fix definition of div_mmc_pre4 divider
ARM: dts: Fix exynos5250-snow's search key to be L_META
ARM: dts: Add the missing "\" key in non-US keyboards for exynos5250-snow
...
Signed-off-by: Olof Johansson <olof@lixom.net>
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSt1TYAAoJEHm+PkMAQRiGvWgH/iWg8TmEWz4KUKuHthuUi0uh
9+2YDN+4k577Xa0obaG24giQeqkCdxMr3oJrS3FO9jeAmaNRHEGhxUPneisb7RtN
9jIVsz5bPa9/DcK9nqtaUQdvA0O5AWTE6AAPmwleTVy+8CygBo987T2uGELnQCSR
FrKCrMePc7Pj0uthMVXrpJ17Ffm/j7jkfRtPhrxHJyngh3jEux+tPbpynH/aKuO2
47unsSQimoFk7n2SPFvNu3E/vZE2xVbu5SH9MCl5yyiCifFjpi3B71LV/FW51lvm
cK8Jzn2BmYDygRFjnZfq4zJHqYJCBHzpjCLWmR37Dm/JS91aGq3+Cg0stDP8UTs=
=+Hcn
-----END PGP SIGNATURE-----
Merge tag 'v3.13-rc5' into next
Linux 3.13-rc5
* tag 'v3.13-rc5': (231 commits)
Linux 3.13-rc5
aio: clean up and fix aio_setup_ring page mapping
aio/migratepages: make aio migrate pages sane
aio: fix kioctx leak introduced by "aio: Fix a trinity splat"
Don't set the INITRD_COMPRESS environment variable automatically
mm: fix build of split ptlock code
pstore: Don't allow high traffic options on fragile devices
mm: do not allocate page->ptl dynamically, if spinlock_t fits to long
mm: page_alloc: revert NUMA aspect of fair allocation policy
Revert "mm: page_alloc: exclude unreclaimable allocations from zone fairness policy"
mm: Fix NULL pointer dereference in madvise(MADV_WILLNEED) support
qla2xxx: Fix scsi_host leak on qlt_lport_register callback failure
target: Remove extra percpu_ref_init
arm64: ptrace: avoid using HW_BREAKPOINT_EMPTY for disabled events
ARC: Allow conditional multiple inclusion of uapi/asm/unistd.h
target/file: Update hw_max_sectors based on current block_size
iser-target: Move INIT_WORK setup into isert_create_device_ib_res
iscsi-target: Fix incorrect np->np_thread NULL assignment
mm/hugetlb: check for pte NULL pointer in __page_check_address()
fix build with make 3.80
...
Conflicts:
drivers/usb/phy/Kconfig
Adds USB OTG/PHY and clock support to BCM281xx and enables
UDC support on the bcm11351-brt and bcm28155-ap boards.
Signed-off-by: Matt Porter <mporter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Tim Kryger <tim.kryger@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Specify the external clock label in the timer node.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Specify the external clock label in each SDHCI node.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
The frequency property in "snps,dw-apb-uart" entries are no longer
required if the rate of the external clock can be determined using the
clk api (see e302cd9 serial: 8250_dw: add support for clk api).
This patch replaces the frequency property in the UART nodes of
bcm11351.dtsi with references to the relevant clocks following the
common clock binding.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Add the DTS nodes for all the i2c busses in the SoC.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Declare clocks that are enabled and configured by bootloaders as fixed
rate clocks in the DTS such that device drivers may use standard clock
function calls.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
Enable all available i2c busses.
Signed-off-by: Tim Kryger <tim.kryger@linaro.org>
Reviewed-by: Christian Daudt <csd@broadcom.com>
Reviewed-by: Matt Porter <matt.porter@linaro.org>
Reviewed-by: Markus Mayer <markus.mayer@linaro.org>
Signed-off-by: Christian Daudt <bcm@fixthebug.org>
- now that PWM driver is on its way to mainline,
we can integrate the DT entries
- As an example, use PWM for at91sam9m10g45ek leds
- Addition of clock specification for newly introduced
crypto DT entries
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQEcBAABAgAGBQJSs3m1AAoJEAf03oE53VmQCDoIAKZ/pNYodYajIozdsYb0+WEw
VKYMkwBwA02tq2XNcbIty5no47kt4516bm6rQ+KWwtMeWXnQChbh1d/cZQSu0xQi
ULbJX5HgRmtgYWR38+T4CkdqG2RmP4UOQjBv4nB0O1vuIEx6CAXbI3NU5zrcgsJu
AbzpR5oImwsQJjjeRQ5qpuRSAfcUZVmDKN7f/SG3s77xNJYhBcVhWAshZDy67sMY
ZYs+2dihUZH2CbZS/Cd6lx2tg5EkTFsZzdX3ZccotE858EMHIF3Ft/1OtuKOXFpm
t3Q6pzOLgOTFzMQbZzZz3jd0kG9GAxiqx5ownPSklV6boUXoLllXR5LzdwQ13qs=
=vTcc
-----END PGP SIGNATURE-----
Merge tag 'at91-dt2' of git://github.com/at91linux/linux-at91 into next/dt
From Nicolas Ferre:
Second DT pull-request for 3.14
- now that PWM driver is on its way to mainline,
we can integrate the DT entries
- As an example, use PWM for at91sam9m10g45ek leds
- Addition of clock specification for newly introduced
crypto DT entries
* tag 'at91-dt2' of git://github.com/at91linux/linux-at91:
ARM: at91/dt: add clk properties to sama5d3 TDES device node
ARM: at91/dt: add clk properties to sama5d3 AES device node
ARM: at91/dt: add clk properties to sama5d3 SHA device node
ARM: at91: at91sam9m10g45ek: switch to PWM leds
ARM: at91: add PWM device node
Signed-off-by: Olof Johansson <olof@lixom.net>
- Add support Octa Cores for exynos5420
: populate CPU node entries to 8 Cores
: extend mct to support 8 local interrupts
- Update dwmmc nodes for exynos5250 and exynos5420
: change status property of dwmmc nodes for exynos5250
: move dwmmc nodes from exynos5 to exynos5250 because
it's different between exynos5250 and exynos5420
: rename mmc nodes from dwmmc for exynos5 SoCs
: add dwmmc nodes for exynos5420
- Add G-Scaler nodes for exynos5420
- Add HS-i2c nodes in exynos5420
: High Speed I2C 7 channels (4 to 10)
- Update sysreg binding and node name in exynos4
- Update min voltage on exynos5250-arndale
- Move fifo-depth property from boards to exynos5250 SoC
: because the fifo-depth property is SoC specific
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSrgntAAoJEA0Cl+kVi2xqfUIP/1eXRFBrF2l6CB27MwdAW3hk
MXNYNwGhftKW/rvZJSMhfkqd3LIuJf707T5gLhfhC1yDi7ahK0BNa8UE1zoaRFC4
IaLvG+8jWiZkvunxOA504FEmO3EMw1ed0bV5Odo74Eelz1qqWwYT4pXcBgY+/Lyi
tqxzSVaN9api3PxvY/RLy8sR9phF4jJ/hXrHMVf0L7CIuPpWyWKcUmav6uo3oJNv
xYYK6xBGuLGr/LgWAwqj+4lPDx3dJtqMUkFV8p7UzhK0mSG3MnQCOFDd6FwznYkR
Exy4KqIMZZLBv8ZnyA69QApOk3x2K9SqeUG7aXiqV751idjKy7s8/UPZ3fNhWiaq
ytExM0VTSVArR9M/Qym2DDCvI4x0u80SeMTcR/igLAySnY2e4Hf61T7JJcmYiWOU
V3cuoVVe6wzMK/Ng31UkYaUlFTPg5N7YJoyD1wXQa9fZcwxFYFHpA35M/68rUdMp
5SsYTFSK5wMwYdup7QsqqbylUAiydzICiFZ1SFBFL2NPpMyIRFVxowChimkKnx6/
BjVtkDd9LaM1sNHHWFO+BavOvlxRmivSbIv6q+50Ax7FO7f4aGr2KnJI9Npao859
5+wCVTxTZPZJecRlcjx/XGjX+kvnb5MqqVVGy0JbYcpElN+0ZLUPDnttwlr9Rxm1
i64VkezAAGVNeLWqX+LS
=6e6p
-----END PGP SIGNATURE-----
Merge tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/dt
From Kukjin Kim:
Samsung DT updates for v3.14
- Add support Octa Cores for exynos5420
: populate CPU node entries to 8 Cores
: extend mct to support 8 local interrupts
- Update dwmmc nodes for exynos5250 and exynos5420
: change status property of dwmmc nodes for exynos5250
: move dwmmc nodes from exynos5 to exynos5250 because
it's different between exynos5250 and exynos5420
: rename mmc nodes from dwmmc for exynos5 SoCs
: add dwmmc nodes for exynos5420
- Add G-Scaler nodes for exynos5420
- Add HS-i2c nodes in exynos5420
: High Speed I2C 7 channels (4 to 10)
- Update sysreg binding and node name in exynos4
- Update min voltage on exynos5250-arndale
- Move fifo-depth property from boards to exynos5250 SoC
: because the fifo-depth property is SoC specific
* tag 'samsung-dt' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Update Samsung sysreg binding document
ARM: dts: Fix sysreg node name in exynos4.dtsi
ARM: dts: Add hs-i2c nodes to exynos5420
ARM: dts: Update min voltage for vdd_arm on Arndale
ARM: dts: populate cpu node entries to 8 cpus for exynos5420
clocksource: mct: extend mct to support 8 local interrupts for Exynos5420
ARM: dts: Add device nodes for GScaler blocks for exynos5420
ARM: dts: Add dwmmc DT nodes for exynos5420 SOC
ARM: dts: rename mmc dts node for exynos5 series
ARM: dts: Move fifo-depth property from exynos5250 board dts
ARM: dts: change status property of dwmmc nodes for exynos5250
ARM: dts: Move dwmmc nodes from exynos5.dtsi to exynos5250.dtsi
Signed-off-by: Olof Johansson <olof@lixom.net>
- Skip eint_init() for pinctrl-exynos because of re-executing
- Use CPU_V6K for S3C64XX(ARM1176JZF-s) instead of CPU_V6
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSrf9BAAoJEA0Cl+kVi2xq7WgP/1/OiO9HmRZS9KfPhHvTIWzv
EqQD/EN17C9oCQuEGIU218BwGnzXUuf3zV4q29nxxEAqQMwx2Fd+cMkmGD+Sx+OY
GKl36akYv0/4zvXh2epCZ8lZsZPlsGyGihHUbbhghvZYf0G60QC0oUf5jGcGsjy2
OYqUntF+I0AUhzkwlCRSNp5fi9hzGH3zNwWEHFIsXdt1S79EpCrVckKUU6ES+gKq
PmMgPSbttJqxIU+KQ8WdAc8xgqgJIWw1KZoOqtnLxxqKEqO6L89AT/EO5WT1+QSs
1a3c8jkZxkVpy2j2o8DRiK6/G40sYs2AVydHzIT9k4o2WMGWeRWy6GTqDUupj2w6
qFHkMm6QhMyiCxqwIaXzNGjfHVPcjQ8YwS6zuQHDyIzzHvm2VbbFEX+ZJpVbIjx8
xCC00cxI+JVVJRtTm9uIuiWj4OrbP5CQvmgByglyWW0t2bRI4BX7jRTAT/87Ausz
zq4MKhxLA/A/DPPek8gq7r7/0WQhgw1MyqVl43W287Ex5gYEOzNPfBAkPxJvYEk3
lX5F3P++a/XFKGq/CWKuc2DhMEw3geeG66WTaCXzh1jWnDLoa9NsZrugRkwfvK4M
dLlG/iS4LWyplzVDjIP4P+2t+SKzNxlB5nD7nQClm54t6gKThh4N9EXkBm+MS/qT
ZeD1xfD6QCLssFa2zkf2
=030e
-----END PGP SIGNATURE-----
Merge tag 'samsung-dev' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/soc
From Kukjin Kim:
Samsung updates for v3.14
- Skip eint_init() for pinctrl-exynos because of re-executing
- Use CPU_V6K for S3C64XX(ARM1176JZF-s) instead of CPU_V6
* tag 'samsung-dev' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: S3C64XX: Select CPU_V6K instead of CPU_V6
ARM: SAMSUNG: if detected device tree skip irq init for S5P
Signed-off-by: Olof Johansson <olof@lixom.net>
- increase number of CPU to 8 for EXYNOS SoCs
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSrf2OAAoJEA0Cl+kVi2xqGRwP/RRwDYNSz+0Es/DQUVFfFKVE
+4vdZsGwlVtzt78Ns4VsNDi7XHqD3i4c4SQw/LB9jlFxxVSb3WNJbrKdZrhn6sFE
WoWpYs+2LHjiItCanUOy0Mnqj72Dg6Gdh8JM7zmCy9RLlrDuALAuC5Md4WpoPnpp
lKx8MzBt9x9hgFWtpnFBRPfVHKFmNvKoWGfLdu8kUmf//uJvNvGL4hURpC0zQgBd
Ii9j6r3EQhLsb/CV7Hr8Fyojmf8YWD5Y5COxT1EzHOUY3Qn7z1ZCKI3pCyNVGBrL
5Lurpaxo3M26Ibjm9yG2pz26tZSvm795ffCoN273jq2TKWu9Q+XOY8N+wAD/DuEY
CyH71VYFp0CgDiFcLbQw49aa8iS7bVKLzIsU3MbebG1HzDrLQ8ZEHAIUiTnQs/y7
WUTs8VKmLqYyg9CkQMhIDr5Fa4kkEFKUtNFSQKvThAiGqiZKQEnyV4PXkvYb9MhK
/LWPjYfGgXEd4t7a3O1g8ZY/u2hqOqMmkYnwSYEgb6/MDympPOIppCDgBrIuNDpY
VxksI2jno2CGtCph9OE4lFJjrexIBoK665sIEk+t0C5zpefdJCj5tEjN94vBm6EL
aH0pMep11cLhnjsK1W/OpnjheP56B7sAuT4vE8JFlXu9IjarUi3jUVOdAZK/902Y
fskRjxCczAV2pYUfxhnr
=Lz/U
-----END PGP SIGNATURE-----
Merge tag 'samsung-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/boards
From Kukjin Kim:
exynos_defconfig updates for v3.14
- increase number of CPU to 8 for EXYNOS SoCs
* tag 'samsung-defconfig' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: exynos_defconfig: increase CONFIG_NR_CPUS value to 8
Signed-off-by: Olof Johansson <olof@lixom.net>
- Switch FIFO mode for arch_enable_uart_fifo()
- Add missing op_mode for PMIC on exynos5250-arndale
- Add missing clock-frequency for CPU on exynos5250
- Fix typo samaung to samsung for exynos5420-pinctrl
- Fix display clock-frequency for exynos4210/exynos4412-origen
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJSrgY0AAoJEA0Cl+kVi2xqNw8P+wUQdgTwRIUlXVh18WDrhHE2
V0DlHeG0vsejIm5l/IC72kXDJWs6kvjqAEeEmo8W5V2JH+aEKCuqIZNrsszXo7v8
/PCjgukGTmmJWgmwzT8rSH18xH90IcpVe0S6mOAoRnqu2RWsnZF/YQ0iUsITzd4k
xfRnkedhxXmT9QL7nXM57acFhMg04vZpaBJtjEoV1suYhUOgf031AhnKsQuZpSev
ldvcKrZrGLr1plXdOk5Gd+mRtwjTaF4HadvvNIy3Kch1s2w4hu9Mvr8UqGk5cbha
GVlJ/10ESYV/p2HLtwjJvUGeRkVvywC+dtQrn0KWZ7ZHSn+Yq+hwmzuyeTw7yCb3
dYp8o+ry0BDgAGs7nLHe/COTJz4XroYwNFvMGqLePMdyDv2VHvnS0yGaOA5VN11U
2BUuqgkOuhCrvLeN2bYRjGKHRQg87sOh3v5vDnU9DSNo9gTzU2K5W8A1mkvNKMgG
MwQwUodsHVLCzHylt9JDaE2r5/HBj+LYU+4bGbrWhwKGz7SUYvFYwNKzW2TAE3sq
PZ+FckZd95wIA9Imo/JYSF306q/83m7Thmy6/zhjlWmSLZEhe/FAUCc6Ys3tZSit
TmduB8Uvu3l2ToOI5R2QHCJRN7BMP1zOvnWVDSHSN6P4g3MoT71dZZ1GAhG3y6kX
HoSLzj1AiFjtBs713fVo
=9LEO
-----END PGP SIGNATURE-----
Merge tag 'samsung-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung into next/fixes-non-critical
From Kukjin Kim:
Samsung non-critical fixes for v3.14
- Switch FIFO mode for arch_enable_uart_fifo()
- Add missing op_mode for PMIC on exynos5250-arndale
- Add missing clock-frequency for CPU on exynos5250
- Fix typo samaung to samsung for exynos5420-pinctrl
- Fix display clock-frequency for exynos4210/exynos4412-origen
* tag 'samsung-fixes' of git://git.kernel.org/pub/scm/linux/kernel/git/kgene/linux-samsung:
ARM: dts: Update display clock frequency for Origen-4412
ARM: dts: Update display clock frequency for Origen-4210
ARM: dts: Fix a typo in exynos5420-pinctrl.dtsi
ARM: dts: Add missing frequency property to exynos5250
ARM: dts: Add missing op_mode property to PMIC on Arndale
ARM: SAMSUNG: Fix switching FIFO in arch_enable_uart_fifo function
Signed-off-by: Olof Johansson <olof@lixom.net>
Add a generic (dtsi) include file for MOXA ART SoCs.
Also add a file for UC-7112-LX.
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
The MOXA ART SoC is based on Faraday's FA526. This is a ARMv4 32-bit
192 MHz CPU with MMU and 16KB/8KB D/I-cache.
Add platform support for this SoC.
Also add UC-7112-LX as a machine.
Signed-off-by: Jonas Jensen <jonas.jensen@gmail.com>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Olof Johansson <olof@lixom.net>
This branch contains these fixes:
- SMP cleanups
- platform initialization cleanup
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.10 (GNU/Linux)
iEYEABECAAYFAlKnFY4ACgkQykllyylKDCFl5QCeLkO5Cbsye59zgq54MaB2W+TE
r8wAn2ghJvZvHMdAAg1nfleknY/W7nJx
=atEt
-----END PGP SIGNATURE-----
Merge tag 'zynq-cleanup-for-3.14' of git://git.xilinx.com/linux-xlnx into next/cleanup
From Michal Simek:
ARM: Xilinx Zynq cleanup patches for v3.14
This branch contains these fixes:
- SMP cleanups
- platform initialization cleanup
* tag 'zynq-cleanup-for-3.14' of git://git.xilinx.com/linux-xlnx:
ARM: zynq: remove unnecessary setting of cpu_present_mask
arm: zynq: Set proper GIC flags
arm: zynq: Use of_platform_populate instead of bus_probe
arm: zynq: Add support for zynq_cpu_kill function
arm: zynq: Invalidate L1 in secondary boot
arm: zynq: platsmp: Remove CPU presence check
Signed-off-by: Olof Johansson <olof@lixom.net>
Much smaller batch of fixes this week.
Biggest one is a revert of an OMAP display change that removed some non-DT
pinmux code that was still needed for 3.13 to get DSI displays to work.
There's also a fix that resolves some misdescribed GPIO controller
resources on shmobile. The rest are mostly smaller fixes, a couple of
MAINTAINERS updates, etc.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.11 (GNU/Linux)
iQIcBAABAgAGBQJStx0EAAoJEIwa5zzehBx3G+gP/3qH83dbelntB3R7Ve3KbT41
YT0q4G8s4Kper+qSXK2eJRTcEUfZBhtXw2GytnEjwdj6xRtTYmdzUIE/7awwzxQx
EkcwyCKiMLhVqjBgYg0fr11RBmbvQxKV0L2iIHoV5N/VJa/I7DN4N1J0PwB/7tuQ
OVpy3UOuutvtV3k4/G4tminixx1Y6JjPy7vEs8oiQoc7MRrMwe4zC2pgRF5eVfFG
uNfRk1IEpvoFM+ir+ZmKJYVsEGXlC/bLwO7KPql6801n7987uQni9YoyUy+7cLGp
CVCSaD7iGVPde8ijfUN84C8IezjfkA/wA9cxaGBj9lD7EdcvXEdtvDiFXpQcZDYY
NZX9p7+ZzTNzKSRIPKET8Ky3GNqDGCoaCoV9YTpUGwMHXmoK66QJpNy1boW0fZ2B
yy3gT0fxJYRKMTiFdV+y77BFpLDNkDGnjuVQEovKC8mX2YfqjR0sOTFjHBhPWk8P
gZ2Lzq1V/j0gd6/YxNStVngQK6/CiA9/qBUeBgiIU6vAzPcpk4HcwapFCcUeU4mU
l8Iga63cBu3iSobSNTcF7EB1iHwOQOTH7txtD1RtPsWxZgXG74kwmtWC336aEhlJ
fixoZIQvzPdQLqtZIMm87jJHXYsBZJnnqCTmFTgfn26Wb79qnS4WMt2tahCLGrkO
RGDjdfaXw46WbJZ25kcJ
=6Nj7
-----END PGP SIGNATURE-----
Merge tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc
Pull ARM SoC fixes from Olof Johansson:
"Much smaller batch of fixes this week.
Biggest one is a revert of an OMAP display change that removed some
non-DT pinmux code that was still needed for 3.13 to get DSI displays
to work.
There's also a fix that resolves some misdescribed GPIO controller
resources on shmobile. The rest are mostly smaller fixes, a couple of
MAINTAINERS updates, etc"
* tag 'fixes-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
Revert "ARM: OMAP2+: Remove legacy mux code for display.c"
MAINTAINERS: Add keystone clock drivers
MAINTAINERS: Add keystone git tree information
ARM: s3c64xx: dt: Fix boot failure due to double clock initialization
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
We recently sorted the nodes in dove, orion5x, kirkwood, and armada
370/xp. However, I missed this file. -6281 is fine.
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add nodes for the two SATA PHYs on kirkwood.
Add node for the one SATA PHY on Dove.
Add pHandles to the PHYs in the sata nodes.
Signed-off-by: Andrew Lunn <andrew@lunn.ch>
Acked-by: Kishon Vijay Abraham I <kishon@ti.com>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add infrastructure to handle distributor and cpu interface register
accesses through the KVM_{GET/SET}_DEVICE_ATTR interface by adding the
KVM_DEV_ARM_VGIC_GRP_DIST_REGS and KVM_DEV_ARM_VGIC_GRP_CPU_REGS groups
and defining the semantics of the attr field to be the MMIO offset as
specified in the GICv2 specs.
Missing register accesses or other changes in individual register access
functions to support save/restore of the VGIC state is added in
subsequent patches.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The arch-generic KVM code expects the cpu field of a vcpu to be -1 if
the vcpu is no longer assigned to a cpu. This is used for the optimized
make_all_cpus_request path and will be used by the vgic code to check
that no vcpus are running.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Support setting the distributor and cpu interface base addresses in the
VM physical address space through the KVM_{SET,GET}_DEVICE_ATTR API
in addition to the ARM specific API.
This has the added benefit of being able to share more code in user
space and do things in a uniform manner.
Also deprecate the older API at the same time, but backwards
compatibility will be maintained.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Support creating the ARM VGIC device through the KVM_CREATE_DEVICE
ioctl, which can then later be leveraged to use the
KVM_{GET/SET}_DEVICE_ATTR, which is useful both for setting addresses in
a more generic API than the ARM-specific one and is useful for
save/restore of VGIC state.
Adds KVM_CAP_DEVICE_CTRL to ARM capabilities.
Note that we change the check for creating a VGIC from bailing out if
any VCPUs were created, to bailing out if any VCPUs were ever run. This
is an important distinction that shouldn't break anything, but allows
creating the VGIC after the VCPUs have been created.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Rework the VGIC initialization slightly to allow initialization of the
vgic cpu-specific state even if the irqchip (the VGIC) hasn't been
created by user space yet. This is safe, because the vgic data
structures are already allocated when the CPU is allocated if VGIC
support is compiled into the kernel. Further, the init process does not
depend on any other information and the sacrifice is a slight
performance degradation for creating VMs in the no-VGIC case.
The reason is that the new device control API doesn't mandate creating
the VGIC before creating the VCPU and it is unreasonable to require user
space to create the VGIC before creating the VCPUs.
At the same time move the irqchip_in_kernel check out of
kvm_vcpu_first_run_init and into the init function to make the per-vcpu
and global init functions symmetric and add comments on the exported
functions making it a bit easier to understand the init flow by only
looking at vgic.c.
Acked-by: Marc Zyngier <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
For migration to work we need to save (and later restore) the state of
each core's virtual generic timer.
Since this is per VCPU, we can use the [gs]et_one_reg ioctl and export
the three needed registers (control, counter, compare value).
Though they live in cp15 space, we don't use the existing list, since
they need special accessor functions and the arch timer is optional.
Acked-by: Marc Zynger <marc.zyngier@arm.com>
Signed-off-by: Andre Przywara <andre.przywara@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Initialize the cntvoff at kvm_init_vm time, not before running the VCPUs
at the first time because that will overwrite any potentially restored
values from user space.
Cc: Andre Przywara <andre.przywara@linaro.org>
Acked-by: Marc Zynger <marc.zyngier@arm.com>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
The current KVM implementation of PSCI returns INVALID_PARAMETERS if the
waitqueue for the corresponding CPU is not active. This does not seem
correct, since KVM should not care what the specific thread is doing,
for example, user space may not have called KVM_RUN on this VCPU yet or
the thread may be busy looping to user space because it received a
signal; this is really up to the user space implementation. Instead we
should check specifically that the CPU is marked as being turned off,
regardless of the VCPU thread state, and if it is, we shall
simply clear the pause flag on the CPU and wake up the thread if it
happens to be blocked for us.
Further, the implementation seems to be racy when executing multiple
VCPU threads. There really isn't a reasonable user space programming
scheme to ensure all secondary CPUs have reached kvm_vcpu_first_run_init
before turning on the boot CPU.
Therefore, set the pause flag on the vcpu at VCPU init time (which can
reasonably be expected to be completed for all CPUs by user space before
running any VCPUs) and clear both this flag and the feature (in case the
feature can somehow get set again in the future) and ping the waitqueue
on turning on a VCPU using PSCI.
Reported-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Christoffer Dall <christoffer.dall@linaro.org>
Make it easier to notice the common file for ChromeOS devices based on
the Exynos5250 by giving it the exynos5250 prefix that the boards have.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Ensure that unused I2C controllers are not activated, causing problems due
to inappropriate pinmuxing or similar, by marking the controllers as
disabled by default and requiring boards to explicitly enable those that
are in use.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Rather than requiring each board to explicitly disable the SPI controllers
it is not using instead require boards to enable those that they are using.
This is less work overall since normally at most one of the controllers is
in use and avoids issues caused by inappropriate pinmuxing.
Signed-off-by: Mark Brown <broonie@linaro.org>
Acked-by: Tomasz Figa <t.figa@samsung.com>
Reviewed-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There is a 16.934MHz fixed rate clock connected to MCLK1 on the CODEC, add
this to the device tree bindings.
Signed-off-by: Mark Brown <broonie@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Exynos5420 SoC has per core thermal management unit.
5 TMU channels 4 for CPUs and 5th for GPU.
This patch adds the device tree nodes to the DT device list.
Nodes carry the misplaced second base address and the second
clock to access the misplaced base address.
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Naveen Krishna Chatradhi <ch.naveen@samsung.com>
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Commit e908d5c5 ("ARM: dts: change status property of dwmmc nodes
for exynos5250") missed out handling the exynos5250 snow dts file.
Signed-off-by: Abhilash Kesavan <a.kesavan@samsung.com>
Signed-off-by: Yuvaraj Kumar C D <yuvaraj.cd@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For consistency with other device tree nodes, this patch adds missing
spaces after node labels.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
There is no need to use two cells for interrupt specifiers inside the
MCT interrupt map, so this patch simplifies the map to use one cell.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
For MCT block compatible with "samsung,exynos4412-mct", that uses PPI
interrupts for local timers, only one local interrupt needs to be
specified, since it is a per-processor interrupt.
This allows moving MCT node of Exynos4x12 SoCs back to common
exynos4x12.dtsi, since they have the same set of interrupts to be
specified, which was the only difference.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
MCT is not an interrupt controller and so there is no point for device
tree nodes representing it to contain interrupt-controller
and #interrupt-cells properties.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Reviewed-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add the device-tree binding for the PWM controller to Exynos5250 and Exynos5420
Signed-off-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Olof Johansson <olofj@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Add SPI device tree nodes to Exynos5420 SoC
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Reviewed-by: Andrew Bresticker <abrestic@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch adds dma controller node info on Exynos5420.
Exynos5420 has adma for audio IPs. As adma clk is dependent
on audss clk provider that will be added later.
Signed-off-by: Padmavathi Venna <padma.v@samsung.com>
Signed-off-by: Leela Krishna Amudala <l.krishna@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This patch removes device tree node of SDHCI0 controller and replaces
it with MSHC to enable support MMC 4.4 and improve performance of eMMC
memory.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
All SoCs from Exynos4x12 series contain the MSHC block, so its node can
be located in exynos4x12.dtsi. In addition, missing clock specifiers
are added, generic SoC attributes are moved from board dts files
to common dtsi file of SoC family and the node is renamed to a more
generic name to follow node naming recommendations.
Signed-off-by: Tomasz Figa <t.figa@samsung.com>
Acked-by: Kyungmin Park <kyungmin.park@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Clock lookup information is required as driver can manipulate
clock rate properly.
Signed-off-by: Seungwon Jeon <tgih.jun@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The only thing exynos_pm_late_initcall() does is calling
pm_genpd_poweroff_unused(), which is already stubbed when
CONFIG_PM_GENERIC_DOMAINS is not enabled. So replace
exynos_pm_late_initcall() with a direct call to
pm_genpd_poweroff_unused().
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
Instead of repeating "select PM_GENERIC_DOMAINS" for all Exynos4
variants add relevant entry in the Kconfig section common to the
SoC series.
Signed-off-by: Sylwester Nawrocki <s.nawrocki@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The device tree sent upstream for exynos5250-snow encoded the search
key as CAPSLK. However in all ChromeOS kernels it is L_META. One can
certainly have long debates about which it ought to be, but I'm
proposing setting it to L_META because:
* That's how _all_ ChromeOS kernels do it and will do it.
* There is no L_META key on the board, so it's nice to have.
* For those people who really want it to be caps lock, they can use
xmodmap or somesuch.
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
When the exynos5250 device tree was sent upstream the keyboard mapping
was missing the 2nd instance of the "\" key. There are two copies of
the "\" because it simply has a different row and column on US and
non-US keyboards.
For more details, see the previous patch in this series: (mkbp: Fix
problems with backslash).
Signed-off-by: Doug Anderson <dianders@chromium.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
* Global
- Use interrupt macros
- Use #include in device tree sources
- Tidyup DT node naming
* emev2 (Emma Mobile EV2) SoC
- Setup internal peripheral interrupts as level high
- Use interrupt macros in DT files
- Add clock tree description in DT
* r8a7791 (R-Car M2) SoC
- Correct GPIO resources
* r8a7791 (R-Car M2) based Koelsch board
- Configure PFC and GPO
- Use r8a7791 suffix for IRQC compat string
- Add DT reference
* r8a7790 (R-Car H2) based Lager board
- Include all 4 GiB of memory
- Use r8a7790 suffix for IRQC and MMCIF compat strings
- Enable MMCIF
- Add default PFC settings
* r8a7778 (R-Car M1) SoC
- Suffix for INTC compat string
- Add HSPI, MMCIF, SDHI and I2C suppport on DTSI
- Correct pin control device addresses
* r8a7778 (R-Car M1) based Bock-W board
- Use falling edge IRQ for LAN9221 in DT reference
- Enable I2C, HSPI0, MMCIF and SDHI
- Correct MMC pin conflict
- Remove manual PFC settings from DT reference
- Add default PFC settings
* r8a7779 (R-Car H1) SoC
- Add HSPI and SDHI support
- Suffix for INTC compat string
* r8a7779 (R-Car H1) based Marzen board
- Enable HSPI0 and SDHI in DTS
- Remove SDHI0 WP pin setting
- Use falling edge IRQ for LAN9221 in DT reference
- Add SDHI support
* r8a7740 (R-Mobile A1) SoC
- Suffix for INTC compat string
- Add FSI support via DTSI
- Use interrupt macros
* r8a7740 based Armadillo board
- Add FSI support for DTS
- Use low level IRQ for ST1231 in DT reference
* r8a73a4 (SH-Mobile APE6) SoC
- Use interrupt macros in DT files
* r8a73a4 (R-Mobile APE6) based ape6evm board
- Include all 2 GiB of memory
* r8a73a0 (SH-Mobile AG5) SoC
- Correct SDHI compat string
* r8a73a0 (SH-Mobile AG5) based kzm9d board
- Add GPIO keys and Add PCF8575 GPIO extender to DT
- Enable DSW2 with gpio-keys
- Use falling edge IRQ for LAN9221 in DT reference
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSqm6XAAoJENfPZGlqN0++pOoQAIgdo3M/CCP56+wAop/nYOfx
DDdozpEt+V6RcNytVwGEkQboIDMqnekiAvhLiJ7GHT7sMHmf7au2KFkNPpxN+noU
QVgmJaMsi2AoaoV6T+rc0ice7sve+3gbHE0S49frNVlabNlo69y5Y3prYBzLmfdt
hefvngIUx6vhosaH00elYhsRTSTd1i5Pkj+jAYQNil1sI+QBJKC61buZrlLPMOfh
WBMZXKROSN+jIYsqwmz+O7LvqNZa+Wjm9M8NFQnKWkv4fj9on+RZtkLuNo62Yy2P
AaOM5Z0B2q5q35a7QcsLX23QiHOtkGOXIXehzjakzA56L5kUaZMWdfSUWGXPE+DU
B163SndwQhRPiYFrb8//Ri5+GQxls6Pw6UKtT7owDMmqkqsYUrJHm7zfu88RcX1O
UcDrtd3ZlF4XMmr3iNxIRzscFx8faQbIErfG2VornRRkEKLT+ILRvcAedZxkhGLk
6fs8efTcxR7lvY+7pDtJ1N/xyGGykSnsf0LiCp5BkADamSyhGhqUcr8CjUfjMhKD
r7WhzbHEQ7FdQ7B4Y8QmxKyH9dC1wNPxB8kZ4m6YjEKFYC95XCehMQhWvbUsx9vM
jBrvvG7414+t3M2CmROwrs9NujJ0Kf0i6078Hvi06l+w4XYe55ytLUGMnXsJAuCL
B7aAaVRIAt3UYK7tncK+
=jkNE
-----END PGP SIGNATURE-----
Merge tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into next/dt
From Simon Horman:
Renesas ARM based SoC DT updates for v3.14
* Global
- Use interrupt macros
- Use #include in device tree sources
- Tidyup DT node naming
* emev2 (Emma Mobile EV2) SoC
- Setup internal peripheral interrupts as level high
- Use interrupt macros in DT files
- Add clock tree description in DT
* r8a7791 (R-Car M2) SoC
- Correct GPIO resources
* r8a7791 (R-Car M2) based Koelsch board
- Configure PFC and GPO
- Use r8a7791 suffix for IRQC compat string
- Add DT reference
* r8a7790 (R-Car H2) based Lager board
- Include all 4 GiB of memory
- Use r8a7790 suffix for IRQC and MMCIF compat strings
- Enable MMCIF
- Add default PFC settings
* r8a7778 (R-Car M1) SoC
- Suffix for INTC compat string
- Add HSPI, MMCIF, SDHI and I2C suppport on DTSI
- Correct pin control device addresses
* r8a7778 (R-Car M1) based Bock-W board
- Use falling edge IRQ for LAN9221 in DT reference
- Enable I2C, HSPI0, MMCIF and SDHI
- Correct MMC pin conflict
- Remove manual PFC settings from DT reference
- Add default PFC settings
* r8a7779 (R-Car H1) SoC
- Add HSPI and SDHI support
- Suffix for INTC compat string
* r8a7779 (R-Car H1) based Marzen board
- Enable HSPI0 and SDHI in DTS
- Remove SDHI0 WP pin setting
- Use falling edge IRQ for LAN9221 in DT reference
- Add SDHI support
* r8a7740 (R-Mobile A1) SoC
- Suffix for INTC compat string
- Add FSI support via DTSI
- Use interrupt macros
* r8a7740 based Armadillo board
- Add FSI support for DTS
- Use low level IRQ for ST1231 in DT reference
* r8a73a4 (SH-Mobile APE6) SoC
- Use interrupt macros in DT files
* r8a73a4 (R-Mobile APE6) based ape6evm board
- Include all 2 GiB of memory
* r8a73a0 (SH-Mobile AG5) SoC
- Correct SDHI compat string
* r8a73a0 (SH-Mobile AG5) based kzm9d board
- Add GPIO keys and Add PCF8575 GPIO extender to DT
- Enable DSW2 with gpio-keys
- Use falling edge IRQ for LAN9221 in DT reference
* tag 'renesas-dt-for-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas: (102 commits)
ARM: shmobile: marzen: enable HSPI0 in DTS
ARM: shmobile: r8a7779: add HSPI support to DTSI
ARM: shmobile: Use r8a7779 suffix for INTC compat string
ARM: shmobile: Use r8a7778 suffix for INTC compat string
ARM: shmobile: Use r8a7740 suffix for INTC compat string
ARM: shmobile: Use sh73a0 suffix for INTC compat string
ARM: shmobile: armadillo: add FSI support for DTS
ARM: shmobile: r8a7740: add FSI support via DTSI
ARM: shmobile: emev2: Setup internal peripheral interrupts as level high
ARM: shmobile: emev2: Use interrupt macros in DT files
ARM: shmobile: Use interrupt macros in r8a73a4 and r8a7778 DT files
ARM: shmobile: Fix r8a7791 GPIO resources in DTS
ARM: shmobile: Include all 4 GiB of memory on Lager DT Ref
ARM: shmobile: Include all 4 GiB of memory on Lager
ARM: shmobile: Include all 2 GiB of memory on APE6EVM
ARM: shmobile: Include all 2 GiB of memory on APE6EVM DT Ref
ARM: shmobile: kzm9g-reference: Add GPIO keys to DT
ARM: shmobile: kzm9g-reference: Add PCF8575 GPIO extender to DT
ARM: shmobile: Koelsch DT reference GPIO LED support
ARM: shmobile: Enable DSW2 with gpio-keys on KZM9D
...
Signed-off-by: Kevin Hilman <khilman@linaro.org>
* r8a7790 (R-Car H1) SoC
- Correct GPIO resources in DT.
This problem has been present since GPIOs were added to the r8a7790 SoC
by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
devices to device tree") in v3.12-rc1.
* irqchip renesas-intc-irqpin
- Correct register bitfield shift calculation
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1
* Lager board
- Do not build the phy fixup unless CONFIG_PHYLIB is enabled
This problem was introduced by 48c8b96f21
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSqmcQAAoJENfPZGlqN0++VTgP/3II1c6Wge1s9TjQ2FnD874X
wVMLAY8oJp+mNiiov+iNtnP0deyjgWr2XfwQ8QNsWTVEAPQjvInOydr7B24SFb7e
FnA5gscGQr49xMorR+x8yUnlyIE6UAbwwgbP2GljsrTZFURo9ohfUA3LP9wSPHJ9
MYRopGb7ZlNaTwxEi5t6rZV3mrBSzbSUZ0YbQbN5vAhm1zoZ7hzfXUsk9ZwhVNnI
RFHOy01DDCb0EM8Yut4DfWMri9VgsMcR+bo73Js1ljpkUujCzJsr5fNlpzCi2unX
Xw9s6WCSNaNGLzgGbbLojAUIkrtMUEp/XT2iATIalKHT0zULqe6kNcnonFJ8GmQk
nrNBF4/rn45S4QFSEiqavrWpmVE78pMEzPTBpmR15+KloLuutdYrqb/HUM60lVh3
zVeL2cG9fTFx2CUODNX9ABGlO7CCDz4MgK5RgSpnnxjIgunLEb4gA+6ncqaQ4XhM
Ldicte6ppq26PNQemiL61PbfVVNE6hcW//IZreFUEQkP2Ls/DzWfBVtOQaWj3fpb
DEK/kvHGA1HVrLTt43WVM5kPy5OMKDGFv6w7NRayTMvUDguuwp5QeGxSFsi/104Z
q5Qaekvi0wIGaWfkRGHB/8o9z/zL/ifW/cqNXqW1Yxf2+KZGuRWIpxZLzMwBfhzb
LoENHwKcU/D7YhzXIGHG
=Vbzt
-----END PGP SIGNATURE-----
Merge tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas into fixes
From Simon Horman:
Renesas ARM based SoC fixes for v3.13
* r8a7790 (R-Car H1) SoC
- Correct GPIO resources in DT.
This problem has been present since GPIOs were added to the r8a7790 SoC
by f98e10c88a ("ARM: shmobile: r8a7790: Add GPIO controller
devices to device tree") in v3.12-rc1.
* irqchip renesas-intc-irqpin
- Correct register bitfield shift calculation
This bug has been present since the renesas-intc-irqpin driver was
introduced by 443580486e ("irqchip: Renesas INTC External IRQ pin
driver") in v3.10-rc1
* Lager board
- Do not build the phy fixup unless CONFIG_PHYLIB is enabled
This problem was introduced by 48c8b96f21
* tag 'renesas-fixes-for-v3.13' of git://git.kernel.org/pub/scm/linux/kernel/git/horms/renesas:
ARM: shmobile: r8a7790: Fix GPIO resources in DTS
irqchip: renesas-intc-irqpin: Fix register bitfield shift calculation
ARM: shmobile: lager: phy fixup needs CONFIG_PHYLIB
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Contrary to the rest of the keyboard, which is connected to the ChromeOS
embedded controller, the power key is hooked up to a GPIO. Add a device
tree node to handle it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The keyboard on Venice2 is attached to the ChromeOS embedded controller.
Add the corresponding device tree nodes and use the MATRIX_KEY define to
encode keycodes.
Signed-off-by: Rhyland Klein <rklein@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
- Fix balloon driver for auto-translate guests (PVHVM, ARM) to not use
scratch pages.
- Fix block API header for ARM32 and ARM64 to have proper layout
- On ARM when mapping guests, stick on PTE_SPECIAL
- When using SWIOTLB under ARM, don't call swiotlb functions twice
- When unmapping guests memory and if we fail, don't return pages which
failed to be unmapped.
- Grant driver was using the wrong address on ARM.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSsdFEAAoJEFjIrFwIi8fJDQwIAL1ygSTwSXdH6TlqtD9GVdsE
G6kiCM7G6VXrKMf8zBtgbGpcl6FT0zOIz4cRcXbyDniuHTjdWuH9dlmZOzFMAirE
uMWwOB1EfmRBEJRsd2pW0Gj0O6VABWh8BHklFCeWUvk/Stlw9uXqIwf7Pjcj6wPT
XW+ZywqsAve4MM60Rz/nMsakLcTK4i5SCRgPPFgAnPKUod3f/QbEHwci/lpinJFv
AuQp2JytCsDc2nehEi1kMwEx7LLBlUcjXTqPG5lhQnXrFleDtMdCJd9dGjeze7Qu
F5sftfdlp18ojQwegv1PGiVI4jV8rIq29ybaef/y9DLd3nC3rmi8B8/m9RG2qyI=
=dUsw
-----END PGP SIGNATURE-----
Merge tag 'stable/for-linus-3.13-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip
Pull Xen bugfixes from Konrad Rzeszutek Wilk:
- Fix balloon driver for auto-translate guests (PVHVM, ARM) to not use
scratch pages.
- Fix block API header for ARM32 and ARM64 to have proper layout
- On ARM when mapping guests, stick on PTE_SPECIAL
- When using SWIOTLB under ARM, don't call swiotlb functions twice
- When unmapping guests memory and if we fail, don't return pages which
failed to be unmapped.
- Grant driver was using the wrong address on ARM.
* tag 'stable/for-linus-3.13-rc4-tag' of git://git.kernel.org/pub/scm/linux/kernel/git/xen/tip:
xen/balloon: Seperate the auto-translate logic properly (v2)
xen/block: Correctly define structures in public headers on ARM32 and ARM64
arm: xen: foreign mapping PTEs are special.
xen/arm64: do not call the swiotlb functions twice
xen: privcmd: do not return pages which we have failed to unmap
XEN: Grant table address, xen_hvm_resume_frames, is a phys_addr not a pfn
Select the GPIOLIB and PL061 in the Versatile defconfig, as this
is present on all boards, and so we get compile and test coverage
for this.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This updates the Versatile defconfig to the thing saved by
savedefconfig so we don't get confusing diffs when trying to
modify other options.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
Move GPIO2 and GPIO3 to be registered from the core as this is
certainly available on Versatile AB as well, not just the PB.
GPIO2 is used for reading board status and GPIO3 is unused,
but it does not hurt to register it anyway.
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This isolates the custom S3C64xx GPIO definition table to
<linux/platform_data/gpio-samsung-s3x64xx.h> as this is
used in a few different places in the kernel, removing the
need to depend on the implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> and thus getting rid of a few nasty
cross-dependencies.
Also delete the CONFIG_SAMSUNG_GPIO_EXTRA stuff. Instead
roof the number of GPIOs for this platform:
First sum up all the GPIO banks from A to Q: 187 GPIOs.
Add the 16 "board GPIOs" and the roof for SAMSUNG_GPIO_EXTRA,
128, so in total maximum 187+16+128 = 331 GPIOs, so let's
take the same roof as for S3C24XX: 512. This way we can do
away with the GPIO calculation macros for GPIO_BOARD_START,
BOARD_NR_GPIOS and the definition of ARCH_NR_GPIOS.
Cc: Mark Brown <broonie@kernel.org>
[on Mini6410 board]
Tested-by: Tomasz Figa <t.figa@samsung.com>
[for changes in mach-s3c64xx]
Acked-by: Tomasz Figa <t.figa@samsung.com>
Tested-by: Mark Brown <broonie@linaro.org>
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
This isolates the custom S3C24xx GPIO definition table to
<linux/platform_data/gpio-samsung-s3x24xx.h> as this is
used in a few different places in the kernel, removing the
need to depend on the implicit inclusion of <mach/gpio.h>
from <linux/gpio.h> and thus getting rid of a few nasty
cross-dependencies.
We also delete the nifty CONFIG_S3C24XX_GPIO_EXTRA stuff.
The biggest this can ever be for the S3C24XX is
CONFIG_S3C24XX_GPIO_EXTRA = 128, and then for CPU_S3C2443 or
CPU_S3C2416 32*12 GPIOs are added, so 32*12+128 = 512
is the absolute roof value on this platform. So we set
the size of ARCH_NR_GPIO to this and the GPIOs array will
fit any S3C24XX platform, as per pattern from other archs.
ChangeLog v2->v3:
- Move the movement of the S3C64XX gpio.h file out of
this patch and into the follow-up patch where it belongs.
ChangeLog v1->v2:
- Added an #ifdef ARCH_S3C24XX around the header inclusion
in drivers/gpio/gpio-samsung.c as we would otherwise
have colliding definitions when compiling S3C64XX.
- Rename inclusion guard in the header file.
Cc: Tomasz Figa <tomasz.figa@gmail.com>
Cc: Sylwester Nawrocki <sylvester.nawrocki@gmail.com>
Cc: Ben Dooks <ben-linux@fluff.org>
Cc: linux-samsung-soc@vger.kernel.org
Acked-by: Kukjin Kim <kgene.kim@samsung.com>
Acked-by: Heiko Stuebner <heiko@sntech.de>
Tested-by: Heiko Stuebner <heiko@sntech.de>
Signed-off-by: Linus Walleij <linus.walleij@linaro.org>
From Santosh Shilimkar:
* keystone/soc:
ARM: keystone: defconfig: enable USB support
ARM: keystone: Avoid calling of_clk_init() twice
ARM: keystone: Make PM bus ready before populating platform devices
ARM: keystone: enable DMA zone for LPAE
ARM: keystone: enable big endian support
Signed-off-by: Kevin Hilman <khilman@linaro.org>
From Uwe Kleine-König:
* efm32/soc: (1003 commits)
ARM: device trees for Energy Micro's EFM32 Cortex-M3 SoCs
ARM: new platform for Energy Micro's EFM32 Cortex-M3 SoCs
+Linux 3.13-rc4
Signed-off-by: Kevin Hilman <khilman@linaro.org>
From Sebastian Hesselbarth:
* berlin/soc:
ARM: add initial support for Marvell Berlin SoCs
ARM: add Armada 1500-mini and Chromecast device tree files
ARM: add Armada 1500 and Sony NSZ-GS7 device tree files
ARM: add Marvell Berlin UART0 lowlevel debug
ARM: add Marvell Berlin SoCs to multi_v7_defconfig
ARM: add Marvell Berlin SoC familiy to Marvell doc
MAINTAINERS: add ARM Marvell Berlin SoC
irqchip: add DesignWare APB ICTL interrupt controller
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Enable USB2 on Beaver, exposed via the mini-PCIe connector.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Modify Tegra30 default USB2 phy_type to UTMI; this matches
power-on-reset defaults and is expected to be the common case.
The current implementation is likely an incorrect
carry-over from Tegra20, where USB2 does default to ULPI.
Signed-off-by: Eric Brower <ebrower@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
dead code as omap4 has been booting with device tree only since
v3.10. Turns out I also removed some display related mux code,
so let's revert that except for the dead code parts.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSsd7KAAoJEBvUPslcq6Vz19gQAK6IyA51RxgyTF6ads5SyNny
HAl7AO/O4yoverXibgdGEe3V6Caye8QbsAVE0qyZAVgtPCattCclRGYUGy8fcy00
mV/KhW6EcQXxApU37f+6uyAm7RrkMPzTP6glqH9IllvFZYsOTNlt6W5+W0juW97n
1xZMvx75bz6aiOvox5mRmSySr0+D3nHGfWhixmPAF09afUWlow2RGMZlPKtEZ27x
wKEV6uxBjGrQoBKIkM1INwB6PzcYsoxwMVDfIzIiGU3Ck/59yVmKqT2UfaqkneXC
poGA9FZ2eeSmh/0fxPue4gDRNYW5f7rjzjjf+x5kKTJi8+G5dX9TpaZhDd7cwvAy
U0hnBWz6P3x0XRDzAAIuUeZP2S9JzedXbBKgAE3447r8MNH74TRA2y07ERpakS45
DpyfepUcueEs9EMSgW/gPbG79cbdA9AiK9dPFVGchlvyk8eUD0KCRoBBPCuv99Z6
mQzcSrQ7XBJV4zq7zomlsL9ERd8R9DjgF89ZWUeiQKbFFxceldkclaVX7s5m2H5h
HzHYTKKNhcP+ZBwoX/IabRhE/N6hNMDKsrnz2GllVHfpocWRJXOZYnosVI/AS/iR
5lLwIdsX6EQYHX1ZrVR8ROJ3R0ft52kNwS6bKt10hor0D/Y5DVpb2i9D34uYMjPj
QBAIwd4yXIJhBwv+ldHp
=gI+4
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.13/display-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into fixes
I accidentally removed some mux code for omap4 that I thought was
dead code as omap4 has been booting with device tree only since
v3.10. Turns out I also removed some display related mux code,
so let's revert that except for the dead code parts.
* tag 'omap-for-v3.13/display-fix' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (439 commits)
Revert "ARM: OMAP2+: Remove legacy mux code for display.c"
+Linux 3.13-rc4
We want to follow the name style of DTS that is SoC-board.dts.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Since init_time in machine descriptor is already covered by
arch/arm/kernel/time.c by default. We needn't to append it any more.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Since some new Hisilicon SoCs are not named as hi3xxx, rename mach-hi3xxx
to mach-hisi instead. And the pronounciation of "hisi" is similar to the
chinese pronounciation of Hisilicon. So Hisilicon guys like this name.
ARCH_HI3xxx will be renamed later since other drivers are using it and
they are still in linux-next git tree. So rename ARCH_HI3xxx later.
Signed-off-by: Haojian Zhuang <haojian.zhuang@gmail.com>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This changes the stack protector config option into a choice of
"None", "Regular", and "Strong":
CONFIG_CC_STACKPROTECTOR_NONE
CONFIG_CC_STACKPROTECTOR_REGULAR
CONFIG_CC_STACKPROTECTOR_STRONG
"Regular" means the old CONFIG_CC_STACKPROTECTOR=y option.
"Strong" is a new mode introduced by this patch. With "Strong" the
kernel is built with -fstack-protector-strong (available in
gcc 4.9 and later). This option increases the coverage of the stack
protector without the heavy performance hit of -fstack-protector-all.
For reference, the stack protector options available in gcc are:
-fstack-protector-all:
Adds the stack-canary saving prefix and stack-canary checking
suffix to _all_ function entry and exit. Results in substantial
use of stack space for saving the canary for deep stack users
(e.g. historically xfs), and measurable (though shockingly still
low) performance hit due to all the saving/checking. Really not
suitable for sane systems, and was entirely removed as an option
from the kernel many years ago.
-fstack-protector:
Adds the canary save/check to functions that define an 8
(--param=ssp-buffer-size=N, N=8 by default) or more byte local
char array. Traditionally, stack overflows happened with
string-based manipulations, so this was a way to find those
functions. Very few total functions actually get the canary; no
measurable performance or size overhead.
-fstack-protector-strong
Adds the canary for a wider set of functions, since it's not
just those with strings that have ultimately been vulnerable to
stack-busting. With this superset, more functions end up with a
canary, but it still remains small compared to all functions
with only a small change in performance. Based on the original
design document, a function gets the canary when it contains any
of:
- local variable's address used as part of the right hand side
of an assignment or function argument
- local variable is an array (or union containing an array),
regardless of array type or length
- uses register local variables
https://docs.google.com/a/google.com/document/d/1xXBH6rRZue4f296vGt9YQcuLVQHeE516stHwt8M9xyU
Find below a comparison of "size" and "objdump" output when built with
gcc-4.9 in three configurations:
- defconfig
11430641 kernel text size
36110 function bodies
- defconfig + CONFIG_CC_STACKPROTECTOR_REGULAR
11468490 kernel text size (+0.33%)
1015 of 36110 functions are stack-protected (2.81%)
- defconfig + CONFIG_CC_STACKPROTECTOR_STRONG via this patch
11692790 kernel text size (+2.24%)
7401 of 36110 functions are stack-protected (20.5%)
With -strong, ARM's compressed boot code now triggers stack
protection, so a static guard was added. Since this is only used
during decompression and was never used before, the exposure
here is very small. Once it switches to the full kernel, the
stack guard is back to normal.
Chrome OS has been using -fstack-protector-strong for its kernel
builds for the last 8 months with no problems.
Signed-off-by: Kees Cook <keescook@chromium.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Cc: linux-arch@vger.kernel.org
Link: http://lkml.kernel.org/r/1387481759-14535-3-git-send-email-keescook@chromium.org
[ Improved the changelog and descriptions some more. ]
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Instead of duplicating the CC_STACKPROTECTOR Kconfig and
Makefile logic in each architecture, switch to using
HAVE_CC_STACKPROTECTOR and keep everything in one place. This
retains the x86-specific bug verification scripts.
Signed-off-by: Kees Cook <keescook@chromium.org>
Cc: Arjan van de Ven <arjan@linux.intel.com>
Cc: Michal Marek <mmarek@suse.cz>
Cc: Russell King <linux@arm.linux.org.uk>
Cc: Ralf Baechle <ralf@linux-mips.org>
Cc: Paul Mundt <lethal@linux-sh.org>
Cc: James Hogan <james.hogan@imgtec.com>
Cc: Stephen Rothwell <sfr@canb.auug.org.au>
Cc: Shawn Guo <shawn.guo@linaro.org>
Cc: Linus Torvalds <torvalds@linux-foundation.org>
Cc: Andrew Morton <akpm@linux-foundation.org>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Thomas Gleixner <tglx@linutronix.de>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-mips@linux-mips.org
Cc: linux-arch@vger.kernel.org
Link: http://lkml.kernel.org/r/1387481759-14535-2-git-send-email-keescook@chromium.org
Signed-off-by: Ingo Molnar <mingo@kernel.org>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 2120 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 104 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Now that support for Intersil ISL12057 RTC chip is available
upstream, let's enable it in NETGEAR ReadyNAS 102 .dts file
so that the device stop believing it's the 70's.
Signed-off-by: Arnaud Ebalard <arno@natisbad.org>
Signed-off-by: Jason Cooper <jason@lakedaemon.net>
Add HDMI node to the Dalmore device tree and hook up the VDD and PLL
regulators as well as the I2C adapter used for DDC and the GPIO used
for hotplug detection.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Dalmore has a 10.1" WUXGA panel connected to one of the DSI outputs of
the Tegra114.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the gr3d device tree node. The gr3d block on Tegra114 is backwards-
compatible with the one on Tegra20.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the device tree for the gr2d hardware found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add device tree nodes for the DSI controllers found on Tegra114 SoCs.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add host1x, DC (display controller) and HDMI devices to Tegra114
device tree.
Signed-off-by: Mikko Perttunen <mperttunen@nvidia.com>
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add a device node for the MIPI calibration block on Tegra114. There is
no need to disable it by default because it only enables the clock while
performing calibration and therefore shouldn't be consuming any power
when unused.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, add unit address to new DT node name]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The d6 and d7 is connected to PWM, we can use PWM to control it,
so switch to PWM leds.
Signed-off-by: Bo Shen <voice.shen@atmel.com>
Signed-off-by: Nicolas Ferre <nicolas.ferre@atmel.com>
Enable DRM panel core support along with support for various simple
panels.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add backlight and panel nodes for the Harmony TFT LCD panel.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add ams AS3722 entry for gpio/pincontrol and regulators
to venice2 DT.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Compare the initial population of default pinmux configuration of Venice2
with the chrome branch and add/fix the missing configurations.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
- kirkwood
- use symbolic names for gpios and key inputs
- mvebu
- add the pxa nand controller to the ReadyNAS and A370-RD boards
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v2.0.22 (GNU/Linux)
iQIcBAABAgAGBQJSrNh/AAoJEP45WPkGe8ZnXFoP/jlCWdq7sjHgeEVq086xjcRq
altKZbk4VcfbQmZoM+LSdVsMXhxjOvRrsOUG06uzQftzE6YgZ6TuypB++sEIkfzL
qAyu+DDDZGTeK35JDbM9MhjUCHdhCoBoQW8LUAgXk77p/FSccOvHAGINRiWZ5xib
a/Eb5YR8Of4anNOqG1Tl/Uji8A2cGTMo4yQcWXo//A9XHPg3zsDgXYmkYJHs80ce
8bgOChAF5tjAjchbYncRkQyZhGVLEBZ6dFMLDFW/4NQtSYUu7CopTTOJnYbj5w//
wxDrr222DXcMQ4Po6NYJHzsewu6QmRYBqZLG2HSfCN3sGVRzmq7B6OQaif8N8j9g
9WmfD7PCVhcSCMx6N4FGtnJobSP3H3oZuEOAmsy5MVFF22c8SwwBMIwF+UVwP9wR
mny1FhZbWREgyDDbKEYwuc13PgjIrP5DoJ5jhTuG9Mqv/fUn4ZS5XOPTe2AIbBO3
UBZRLUsUirYMyGJxy2Yz08ovIOfBb6ilQFvvli2BWDcyiqdpxZ5HTYtQSKd8YLnQ
Q2B28n4Gxi8QC9OpObeyU2y03wiI/jYTGKDDgS5Ar8SKEZg479QK0lAGuaZPFSdo
09mRkY3OF521+2LfAByw8AFIBW945XzJLDUx0L9Qv9OFTkJof3VB4S3DTF8PILQB
SWXQHTLNhJLF4fVxd1B0
=ux36
-----END PGP SIGNATURE-----
Merge tag 'mvebu-dt-3.14-3' of git://git.infradead.org/linux-mvebu into next/dt
From Jason Cooper:
mvebu DT changes for v3.14 (incr. #3)
- kirkwood
- use symbolic names for gpios and key inputs
- mvebu
- add the pxa nand controller to the ReadyNAS and A370-RD boards
* tag 'mvebu-dt-3.14-3' of git://git.infradead.org/linux-mvebu:
ARM: mvebu: Enable NAND controller in A370 Reference Design board
ARM: mvebu: Enable NAND controller in ReadyNAS 2120 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 104 .dts file
ARM: mvebu: Enable NAND controller in ReadyNAS 102 .dts file
ARM: DT: Kirkwood: Use symbolic names from gpio.h
ARM: DT: Kirkwood: Use symbolic names from input.h
Signed-off-by: Kevin Hilman <khilman@linaro.org>
- Drop 0x prefixes
- Get rid of explicit GPIO management
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSq6K8AAoJEEEQszewGV1zFkkP/jZEnJ/pBEcdiCVZGc6UGcIk
ITGpqkY6Baq9W3j4g8BINEcT1h8zPk/ZxICE+GpzgeKd3K2u00p44mMixZXVFHaI
umP98AbzvTP3ZdBL+v93uNm5dTcIEG1jdvC8BsgJs80KsYv/6HKPvT2RfF1vfsri
S2ZrbIlWXRGeCqERfctilOrGD0HUbAM7tD4LuiBd14LWfc40OswHjweUsKvqESj9
DS3F6Eo9y1oZcdOZJ2zOqep61rBiuJ8yyQ/TGG1/fKcKDrS+pd21bOn4DKkq3OMw
Of1OHvylxjiId060kgbEpBvRtH2GsjO4rd9jLzcuzg+/apSqoxHoYaRuWucOeTF3
5PQ2FMjlkcRMJMZjNHg6v3I/OFy1KXiWpSN6IN7p/VgB7V9krNQFxruxS/bW/Mzu
DTtvJV3YoNXVl5Krf9oEAjLn3mEn2SXKxlgtaMuvElQF2V1xZ4KzH0fvlJIpZJTn
O38UoalNDJKJDZ/Db+TnNmFN28ApoT+wXdUPRRuyojhwcHwmNMuqEwGP1Jtjc9ts
yFEH6Hohdli0Uvgfj4lBU2pZIRqq2qIIehLJ/MyO4sCN4BNV5ZJRynDLmbCQ4DXM
H2gJxvm6pY3ORN+Ry2ii4PXmvmc3X5ihU6ejVXtfyO77ZD81Z8fcRqiH5iFqNJ0/
+Tzr9G+dE5DFOv+Jw2Ml
=QVcj
-----END PGP SIGNATURE-----
Merge tag 'nomadik-dt-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik into next/dt
From Linus Walleij:
Some Nomadik Device Tree updates for the v3.14 cycle:
- Drop 0x prefixes
- Get rid of explicit GPIO management
* tag 'nomadik-dt-v3.14' of git://git.kernel.org/pub/scm/linux/kernel/git/linusw/linux-nomadik:
ARM: nomadik: get rid of explicit ethernet GPIO management
ARM: nomadik: Remove '0x's from nomadik stn8815 DTS file
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQEcBAABAgAGBQJSrhGrAAoJEHm+PkMAQRiGsNoH/jIK3CsQ2lbW7yRLXmfgtbzz
i2Kep6D4SDvmaLpLYOVC8xNYTiE8jtTbSXHomwP5wMZ63MQDhBfnEWsEWqeZ9+D9
3Q46p0QWuoBgYu2VGkoxTfygkT6hhSpwWIi3SeImbY4fg57OHiUil/+YGhORM4Qc
K4549OCTY3sIrgmWL77gzqjRUo+pQ4C73NKqZ3+5nlOmYBZC1yugk8mFwEpQkwhK
4NRNU760Fo+XIht/bINqRiPMddzC15p0mxvJy3cDW8bZa1tFSS9SB7AQUULBbcHL
+2dFlFOEb5SV1sNiNPrJ0W+h2qUh2e7kPB0F8epaBppgbwVdyQoC2u4uuLV2ZN0=
=lI2r
-----END PGP SIGNATURE-----
Merge tag 'v3.13-rc4' into next
Linux 3.13-rc4
* tag 'v3.13-rc4': (1001 commits)
Linux 3.13-rc4
null_blk: mem garbage on NUMA systems during init
radeon_pm: fix oops in hwmon_attributes_visible() and radeon_hwmon_show_temp_thresh()
Revert "selinux: consider filesystem subtype in policies"
igb: Fix for issue where values could be too high for udelay function.
i40e: fix null dereference
ARM: fix asm/memory.h build error
dm array: fix a reference counting bug in shadow_ablock
dm space map: disallow decrementing a reference count below zero
mm: memcg: do not allow task about to OOM kill to bypass the limit
mm: memcg: fix race condition between memcg teardown and swapin
thp: move preallocated PTE page table on move_huge_pmd()
mfd/rtc: s5m: fix register updating by adding regmap for RTC
rtc: s5m: enable IRQ wake during suspend
rtc: s5m: limit endless loop waiting for register update
rtc: s5m: fix unsuccesful IRQ request during probe
drivers/rtc/rtc-s5m.c: fix info->rtc assignment
include/linux/kernel.h: make might_fault() a nop for !MMU
drivers/rtc/rtc-at91rm9200.c: correct alarm over day/month wrap
procfs: also fix proc_reg_get_unmapped_area() for !MMU case
...
Signed-off-by: Felipe Balbi <balbi@ti.com>
Correct spelling typo in various part of kernel
Signed-off-by: Masanari Iida <standby24x7@gmail.com>
Acked-by: Randy Dunlap <rdunlap@infradead.org>
Signed-off-by: Jiri Kosina <jkosina@suse.cz>
Now that the DTS file r8a7790-lager.dts can be used with board-lager.c
and board-lager-reference.c, proceed with removing
r8a7790-lager-reference.dts.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The external crystal frequency is 20MHz on the Koelsch board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The external crystal frequency is 20MHz on the Lager board. Specify it
in the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Copy the device nodes from Koelsch reference into the Koeslch device
tree file. This will allow us to use a single DTS file regarless of
kernel configuration. In case of legacy C board code the device nodes
may or may not be used, but in the multiplatform case all the DT device
nodes are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Copy the device nodes from Lager reference into the Lager device tree
file. This will allow us to use a single DTS file regarless of kernel
configuration. In case of legacy C board code the device nodes may or
may not be used, but in the multiplatform case all the DT device nodes
are used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7791 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Reference clocks using a "clocks" property in all nodes corresponding to
devices that require a clock.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Declare all core clocks and DIV6 clocks, as well as all MSTP clocks
currently used by r8a7790 boards.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The board had 4 buttons connected to GPIOs, add a corresponding
gpio-keys device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Armadillo 800 EVA panel module has a backlight enable signal
connected to GPIO 61. Report this in the backlight DT node.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 22ceeee16e ("pwm-backlight: Add
power supply support") added a mandatory power supply for the PWM
backlight. Add a fixed 5V regulator and reference it for the backlight
power supply.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Fix a typo in the USBHS1 pinconf entry that prevented the pull-down from
being enabled.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Koelsch support boot with the legacy DTS for
Koelsch as well as the Koelsch reference DTS.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Let the multiplatform Lager support boot with the legacy DTS for Lager
as well as the Lager reference DTS.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that r8a7791 has CCF support remove the legacy Koelsch reference
Kconfig bits CONFIG_MACH_KOELSCH_REFERENCE for the non-multiplatform
case.
Starting from this commit Koelsch board support is always enabled via
CONFIG_MACH_KOELSCH, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-koelsch.c and board-koelsch-reference.c
The file board-koelsch-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
[horms+renesas@verge.net.au: Dropped arch/arm/boot/dts/Makefile portion]
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that r8a7790 has CCF support remove the legacy Lager reference
Kconfig bits CONFIG_MACH_LAGER_REFERENCE for the non-multiplatform
case.
Starting from this commit Lager board support is always enabled via
CONFIG_MACH_LAGER, and CONFIG_ARCH_MULTIPLATFORM is used to select
between board-lager.c and board-lager-reference.c
The file board-lager-reference.c can no longer be used together with
the legacy sh-clk clock framework, instead CCF is used.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7791.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.
Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Now that the common clock framework is supported, the clock lookup
entries in clock-r8a7790.c are not registered anymore. Devices must
instead reference their clocks in the device tree. However, SCIF and CMT
devices are still instantiated through platform code, and thus need a
clock lookup entry.
Retrieve the SCIF and CMT clock entries by name and register clkdevs for
the corresponding devices. This will be removed when the SCIF and CMT
devices will be instantiated from the device tree.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The common clock framework is initialized in the rcar_gen2_init_timer()
function, remove the of_clk_init() call.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Enable multiplaform ARM architecture support for the Lager reference
board. Common clock framework initialization will be handled by the
rcar_gen2_init_timer() call, we just need to remove the legacy clock
code initialization.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The Armadillo 800 EVA panel module has a backlight enable signal
connected to GPIO 61. Instead of requesting the GPIO in board code and
setting it to a high level unconditionally, pass the GPIO number to the
PWM backlight driver as the backlight enable GPIO.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Register Ether platform device and pin data on the Koelsch board.
Register platform fixup for Micrel KSZ8041 PHY, just like on the Lager board.
Signed-off-by: Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Only the LVDS output is currently supported.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Acked-by: Magnus Damm <damm@opensource.se>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The r8a7790.dtsi file has four sdhi nodes which the first two have the wrong
resource size for their register block. This causes the sh_modbile_sdhi driver
to fail to communicate with card at-all.
Change sdhi{0,1} node size from 0x100 to 0x200 to correct these nodes
as per Kuninori Morimoto's response to the original patch where all four
nodes where changed. sdhi{2,3} are the correct size.
This bug has been present since sdhi resources were added to the r8a7790 by
8c9b1aa418 ("ARM: shmobile: r8a7790: add MMCIF and SDHI DT
templates") in v3.11-rc2.
Signed-off-by: Ben Dooks <ben.dooks@codethink.co.uk>
Tested-by: William Towle <william.towle@codethink.co.uk>
Acked-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
4dcfa60071
(ARM: DMA-API: better handing of DMA masks for coherent allocations)
exchanged DMA mask check method.
Below warning will appear without this patch
asoc-simple-card asoc-simple-card.0: \
Coherent DMA mask 0xffffffffffffffff is larger than dma_addr_t allows
asoc-simple-card asoc-simple-card.0: \
Driver did not use or check the return value from dma_set_coherent_mask()?
Signed-off-by: Kuninori Morimoto <kuninori.morimoto.gx@renesas.com>
Acked-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
CONFIG_INOTIFY_USER and CONFIG_UNIX are required for udev to function.
This change brings the koelsch defconfig into line with
other shmobile defconfigs.
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
CONFIG_PACKET is required for the ISC dhcpd daemon function.
This change brings the koelsch defconfig into line with
other shmobile defconfigs.
Signed-off-by: Simon Horman <horms@verge.net.au>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The koelsch board uses has an SH ethernet controller which uses a Micrel
phy. Select MICREL_PHY for koelsch if SH_ETH is enabled to make use of the
Micrel-specific phy driver rather than relying on the generic phy driver.
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
When CONFIG_COMMON_CLOCK is enabled, call rcar_gen2_clocks_init() in the
timer init function to initialize the common clock framework before
initializing the clock sources. This will take care of clock
initialization when the r8a779[01] boards will be switched to
multiplatform kernels.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Commit 22ceeee16e ("pwm-backlight: Add
power supply support") added a mandatory power supply for the PWM
backlight. Add a fixed 5V regulator to board code with a consumer supply
entry for the backlight device.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
(cherry picked from commit ad11cb9a5cf96346f1240995c672cdbb5501785c)
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
The backlight is controlled by a PWM signal generated by the TPU.
Signed-off-by: Laurent Pinchart <laurent.pinchart+renesas@ideasonboard.com>
Signed-off-by: Simon Horman <horms+renesas@verge.net.au>
Conflicts:
drivers/net/ethernet/intel/i40e/i40e_main.c
drivers/net/macvtap.c
Both minor merge hassles, simple overlapping changes.
Signed-off-by: David S. Miller <davem@davemloft.net>
This adds support for CompuLab SBC-T3530, also known as cm-t3730:
http://compulab.co.il/products/sbcs/sbc-t3530/
It seems that with the sbc-3xxx mainboard is also used on
SBC-T3517 and SBC-T3730 with just a different CPU module:
http://compulab.co.il/products/sbcs/sbc-t3517/http://compulab.co.il/products/sbcs/sbc-t3730/
So let's add a common omap3-sb-t35.dtsi and then separate SoC
specific omap3-sbc-t3730.dts, omap3-sbc-t3530.dts and
omap3-sbc-t3517.dts.
I've tested this with SBC-T3730 as that's the only one I have.
At least serial, both Ethernet controllers, MMC, and wl12xx WLAN
work.
Note that WLAN seems to be different for SBC-T3530. And SBC-T3517
may need some changes for the EMAC Ethernet if that's used
instead of the smsc911x.
Cc: devicetree@vger.kernel.org
Cc: Mike Rapoport <mike@compulab.co.il>
Acked-by: Igor Grinberg <grinberg@compulab.co.il>
Signed-off-by: Tony Lindgren <tony@atomide.com>
This ensures that the PMIC RTC provides the system time, rather than
the on-SoC RTC, which is not battery-backed.
tegra124-venice2.dts isn't touched yet since we haven't added any off-
SoC RTC device to its device tree.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This moves definitions for cpuidle into mach-exynos/cpuidle.c,
because we don't need to keep them in the <mach/regs-clock.h>.
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
This moves regarding exynos-cpufreq definitions into drivers/cpufreq/
exynos-cpufreq.h because they are used only for the cpufreq driver.
Cc: Rafael J. Wysocki <rjw@rjwysocki.net>
Acked-by: Viresh Kumar <viresh.kumar@linaro.org>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
We don't need to keep the definitions for exynos4_bus into
mach-exynos/ so this moves them into drviers/devfreq with
adding header file.
Acked-by: MyungJoo Ham <myungjoo.ham@samsung.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
According to board schematics, for HSMMC1 a GPIO line is used to detect
card presence, while currently it is being configured for internal card
detect line, which is multiplexed with card detect line of HSMMC0 and
thus breaking it.
This patch adds proper sdhci platform data setting card detect type to
external GPIO and fixing operation of HSMMC0.
Signed-off-by: Tomasz Figa <tomasz.figa@gmail.com>
Signed-off-by: Kukjin Kim <kgene.kim@samsung.com>
The supply list is needed by the platform driver, but not by the usb driver.
So this information belongs to the platform data and should not be hardcoded
in the subdevice driver.
Signed-off-by: Hans Verkuil <hans.verkuil@cisco.com>
Tested-by: Eduardo Valentin <edubezval@gmail.com>
Acked-by: Eduardo Valentin <edubezval@gmail.com>
Signed-off-by: Mauro Carvalho Chehab <m.chehab@samsung.com>
Add default config for arch-hi3xxx. It's used for Hisilicon Hi3xxx SoC.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Enable Hisilicon Hi4511 development platform with device tree support.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Add board support with device tree for Hisilicon Hi3620 SoC platform.
Signed-off-by: Haojian Zhuang <haojian.zhuang@linaro.org>
[khilman: fix checkpatch errors]
[khilman: fold in patch which selects GPIO in Kconfig]
Signed-off-by: Kevin Hilman <khilman@linaro.org>
Commit e30b06f4d5 (ARM: OMAP2+: Remove
legacy mux code for display.c) removed non-DT DSI and HDMI pinmuxing.
However, DSI pinmuxing is still needed, and removing that caused DSI
displays not to work.
This reverts the DSI parts of the commit.
Signed-off-by: Tomi Valkeinen <tomi.valkeinen@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
for removing omap3 legacy booting support.
We can make omap2420 and 2430 boot in device tree only mode by keeping
board-n8x0.c around until Menelaus has device tree and regulator support
so devices still work. For the omap2430-sdp we have omap2430-sdp.dts,
and there's also a minimal support for H4 in omap2420-h4.dts.
For omap3, let's not drop the legacy platform booting quite yet so
people have a little time to update their booting system.
With the fixes going into v3.13, thing should behave pretty much the
same way for legacy booting and device tree based booting for omap3.
So people using omap3 based boards, please update your systems to
boot in device tree mode as omap3 is the last SoC in mach-omap2
that boots in the legacy mode.
-----BEGIN PGP SIGNATURE-----
Version: GnuPG v1.4.15 (GNU/Linux)
iQIcBAABAgAGBQJSp27yAAoJEBvUPslcq6Vz5GcQAMFZwVcwYq1szKDDeZNhDaoK
HQK3DPbh7zWlRAmNQhr4LVqy7IGlYiaPGvsG5BBsiXVNt0nxM90SREx42j2zpAwG
yH8SXRlDKvHCP/hbRYUjfiG4H8y7TqHWklSxWWQ0qQ63316Pngg2ppzCizlYP5Kz
ACKETyORUJbCBmcw9XwHP7+lCa1feBq4U8nEdT7OMOfzHn5rGNqrslEHtpqbm6dp
XgEYN+reDDTUPaoAW+knURgERASsqx/o0YZWQ4OeImAuxtD0Dk0V5PeCEYiCDqLQ
nJpZlqhWDeo/llfbY7T1gL3Fr70+uYSed3iE8YfVkfC235cadd8nhw11K5hNyyvT
xv+n5meS7762HOIh9nZ9sGi4vW6B3HbpL39tRW1fIKT8LQ46BL0LpfhnWdcsUHKZ
9OmCiBM9hkB/s3a+3zYGpry1rrdHe9l6KIm701yWmmk70cCl8ELGJutvG5qWurNb
lFxy6+ZtuSCvAsa3H5KtJJGiKZs5A2IEOIuEUL3XnbJPGUSz3Rj7jMr0NS7fPYhB
jK5vfguz+ok01pi304AbNzVvv3Fothb3lff5JjWK8C9WuipA8lPWdKP/pcqVdA7P
OnqdXqgx5d4efykvN5WQN67AfjXXj0nzB3v17xF3Y31APZ/O7T7XTNFGybXgNKgf
8SN7JJejgiI3deWdltnz
=uez2
-----END PGP SIGNATURE-----
Merge tag 'omap-for-v3.14/board-removal-safe' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap into next/boards
From Tony Lindgren:
Make omap2420 and 2430 boot in device tree only mode and prepare things
for removing omap3 legacy booting support.
We can make omap2420 and 2430 boot in device tree only mode by keeping
board-n8x0.c around until Menelaus has device tree and regulator support
so devices still work. For the omap2430-sdp we have omap2430-sdp.dts,
and there's also a minimal support for H4 in omap2420-h4.dts.
For omap3, let's not drop the legacy platform booting quite yet so
people have a little time to update their booting system.
With the fixes going into v3.13, thing should behave pretty much the
same way for legacy booting and device tree based booting for omap3.
So people using omap3 based boards, please update your systems to
boot in device tree mode as omap3 is the last SoC in mach-omap2
that boots in the legacy mode.
* tag 'omap-for-v3.14/board-removal-safe' of git://git.kernel.org/pub/scm/linux/kernel/git/tmlind/linux-omap: (299 commits)
ARM: dts: Add basic devices on am3517-evm
ARM: OMAP2+: Use pdata quirks for emac on am3517
ARM: OMAP2+: Add support for legacy auxdata for twl
ARM: dts: Fix booting for secure omaps
ARM: OMAP2+: Fix the machine entry for am3517
ARM: dts: Fix missing entries for am3517
ARM: OMAP2+: Fix overwriting hwmod data with data from device tree
+Linux 3.13-rc3
Signed-off-by: Kevin Hilman <khilman@linaro.org>
This is a complex patch for refactoring CLPS711X serial driver.
Major changes:
- Eliminate <mach/hardware.h> usage.
- Devicetree support.
Signed-off-by: Alexander Shiyan <shc_work@mail.ru>
Acked-by: Arnd Bergmann <arnd@arndb.de>
Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
This reverts commit 3581fe0ef3.
Fixes to the handling of PERF_EVENT_IOC_PERIOD in the core code mean
we no longer have to play this horrible game.
Signed-off-by: Will Deacon <will.deacon@arm.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Link: http://lkml.kernel.org/r/1385560479-11014-2-git-send-email-will.deacon@arm.com
Signed-off-by: Ingo Molnar <mingo@kernel.org>
The SPI controllers on Tegra124 are compatible with those found on the
Tegra114 SoC.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
This pin needs to be configured in pull-down, non-tristate mode in order
for the backlight to work correctly.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Other boards use PULL_NONE for their debug UART pins, and without this
change, the board doesn't accept any serial input.
Don't set the I2S port pins to tristate mode, or no audio signal will
be sent out.
Fixes: 605ae5804385 ("ARM: tegra: add default pinctrl nodes for Venice2")
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Add the default pinmux configuration for the Tegra124 based
Venice2 platform.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Set the parent of the regulators LDO2 to LDO9 according to the
schematic. Set the base voltage to 3.3V, there is only 3.3V on the
module itself.
Set the Core and CPU voltage to the specified voltages of 1.2V and
1.0V respectivly.
LDO6 should deliver 2.85V. The attached peripherals were not in
use so far.
Signed-off-by: Stefan Agner <stefan@agner.ch>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra30 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra20 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use Tegra pinconrol dt-binding macro to set the values of different pinmux
properties of Tegra114 platforms.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Use key code macros for all key code refernced for keys.
For tegra20-seaboard.dts and tegra20-harmony.dts:
The key comment for key (16th row and 1st column) is KEY_KPSLASH but
code is 0x004e which is the key code for KEY_KPPLUS. As there other
key exist with KY_KPPLUS, I am assuming key code is wrong and comment
is fine. With this assumption, I am keeping the key code as KEY_KPSLASH.
Signed-off-by: Laxman Dewangan <ldewangan@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Subsequent patches will need to reference a PWM channel for backlight
support, so enable the PWM device and assign a label to it.
Signed-off-by: Thierry Reding <treding@nvidia.com>
Signed-off-by: Stephen Warren <swarren@nvidia.com>
The PWM controller on Tegra124 is the same as the one on earlier SoC
generations.
Signed-off-by: Thierry Reding <treding@nvidia.com>
[swarren, added reset properties]
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Venice2 uses the MAX98090 audio CODEC, and supports built-in speakers,
and a combo headphones/microphone jack. Add a top-level sound card node
to represent this.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 contains a similar set of audio devices to previous Tegra chips.
Specifically, there is an AHUB device which contains DMA FIFOs and audio
routing, and which hosts various audio-related components such as I2S
controllers.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Enable all the I2C controllers that are wired up on Venice2. I don't
know the correct I2C bus clock rates, so set them all to a conservative
100KHz for now.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 has 6 I2C controllers. The first 5 have identical configuration
to Tegra114, but the sixth obviously has different interrupt/... IDs.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Tegra124 has 4 MMC controllers just like previous versions of the SoC.
Note that there are some non-backwards-compatible HW differences, and
hence a new DT compatible value must be used to describe the HW.
Also enable the relevant controllers in the Venice2 board DT.
power-gpios property suggested by Thierry Reding.
Signed-off-by: Stephen Warren <swarren@nvidia.com>
Reviewed-by: Thierry Reding <treding@nvidia.com>
Tested-by: Thierry Reding <treding@nvidia.com>
Stephen Boyd